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403edfa436
The driver used to truncate several 64-bit registers such as PMCEID[n]
registers used to describe whether architectural and microarchitectural
events in range 0x4000-0x401f exist. Due to discarding the bits, the
driver made the events invisible, even if they existed.
Moreover, PMCCFILTR and PMCR registers have additional bits in the upper
32 bits. This patch makes them available although they aren't currently
used. Finally, functions handling PMXEVCNTR and PMXEVTYPER registers are
removed as they not being used at all.
Fixes: df29ddf4f0 ("arm64: perf: Abstract system register accesses away")
Reported-by: Carl Worth <carl@os.amperecomputing.com>
Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
Acked-by: Will Deacon <will@kernel.org>
Closes: https://lore.kernel.org/..
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20231102183012.1251410-1-ilkka@os.amperecomputing.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
141 lines
2.5 KiB
C
141 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_PMUV3_H
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#define __ASM_PMUV3_H
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#include <linux/kvm_host.h>
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#include <asm/cpufeature.h>
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#include <asm/sysreg.h>
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#define RETURN_READ_PMEVCNTRN(n) \
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return read_sysreg(pmevcntr##n##_el0)
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static inline unsigned long read_pmevcntrn(int n)
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{
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PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
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return 0;
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}
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#define WRITE_PMEVCNTRN(n) \
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write_sysreg(val, pmevcntr##n##_el0)
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static inline void write_pmevcntrn(int n, unsigned long val)
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{
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PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
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}
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#define WRITE_PMEVTYPERN(n) \
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write_sysreg(val, pmevtyper##n##_el0)
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static inline void write_pmevtypern(int n, unsigned long val)
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{
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PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
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}
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static inline unsigned long read_pmmir(void)
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{
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return read_cpuid(PMMIR_EL1);
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}
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static inline u32 read_pmuver(void)
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{
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u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
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return cpuid_feature_extract_unsigned_field(dfr0,
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ID_AA64DFR0_EL1_PMUVer_SHIFT);
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}
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static inline void write_pmcr(u64 val)
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{
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write_sysreg(val, pmcr_el0);
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}
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static inline u64 read_pmcr(void)
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{
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return read_sysreg(pmcr_el0);
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}
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static inline void write_pmselr(u32 val)
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{
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write_sysreg(val, pmselr_el0);
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}
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static inline void write_pmccntr(u64 val)
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{
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write_sysreg(val, pmccntr_el0);
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}
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static inline u64 read_pmccntr(void)
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{
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return read_sysreg(pmccntr_el0);
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}
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static inline void write_pmcntenset(u32 val)
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{
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write_sysreg(val, pmcntenset_el0);
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}
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static inline void write_pmcntenclr(u32 val)
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{
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write_sysreg(val, pmcntenclr_el0);
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}
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static inline void write_pmintenset(u32 val)
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{
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write_sysreg(val, pmintenset_el1);
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}
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static inline void write_pmintenclr(u32 val)
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{
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write_sysreg(val, pmintenclr_el1);
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}
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static inline void write_pmccfiltr(u64 val)
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{
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write_sysreg(val, pmccfiltr_el0);
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}
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static inline void write_pmovsclr(u32 val)
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{
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write_sysreg(val, pmovsclr_el0);
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}
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static inline u32 read_pmovsclr(void)
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{
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return read_sysreg(pmovsclr_el0);
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}
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static inline void write_pmuserenr(u32 val)
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{
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write_sysreg(val, pmuserenr_el0);
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}
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static inline u64 read_pmceid0(void)
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{
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return read_sysreg(pmceid0_el0);
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}
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static inline u64 read_pmceid1(void)
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{
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return read_sysreg(pmceid1_el0);
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}
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static inline bool pmuv3_implemented(int pmuver)
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{
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return !(pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF ||
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pmuver == ID_AA64DFR0_EL1_PMUVer_NI);
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}
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static inline bool is_pmuv3p4(int pmuver)
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{
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return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4;
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}
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static inline bool is_pmuv3p5(int pmuver)
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{
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return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5;
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}
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#endif
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