mirror of
https://git.proxmox.com/git/mirror_ubuntu-kernels.git
synced 2025-11-21 20:58:16 +00:00
6c1561fb90
The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for each
SoC vendor, following the same scheme that is used on arm64, mips and
riscv. This has been discussed for many years, but so far we never did
this as there was a plan to move the files out of the kernel entirely,
which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along
with their device drivers.
* The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the time.
* Amlogic C3 is a Cortex-A35 based smart IP camera chip
* Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
* Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
* Qualcomm SDX75 is the latest generation modem chip that is used
as a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
* Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie
C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those included
there are 39 new board files, but only five more 32-bit this time, probably
a new low:
* Marantec Maveo board based on dhcor imx6ull module
* Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
* Epson Moverio BT-200 AR glasses based on TI OMAP4
* PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
* ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than
we had in the recent releases:
* Three boards based on NXP i.MX8: Emtop SoM & Baseboard,
NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice
gw7905-2x device.
* NVIDIA IGX Orin and Jetson Orin Nano boards, both based on
tegra234
* Qualcomm gains support for 6 reference boards on various members
of their IPQ networking SoC series, as well as the Sony Xperia M4
Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board
on top of the various reference platforms for their new chips.
* Rockchips support for several newer boards: Indiedroid Nova (rk3588),
Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C
Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S
(rk3568)
* TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin
family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
* continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
* support for devicetree overlays on at91, bcm283x
* significant additions to existing SoC support on mediatek, qualcomm,
ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1
As usual, a lot more detail is available in the individual merge
commits.
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Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC devicetree updates from Arnd Bergmann:
"The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for
each SoC vendor, following the same scheme that is used on arm64, mips
and riscv. This has been discussed for many years, but so far we never
did this as there was a plan to move the files out of the kernel
entirely, which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along with
their device drivers.
- The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the
time.
- Amlogic C3 is a Cortex-A35 based smart IP camera chip
- Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
- Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
- Qualcomm SDX75 is the latest generation modem chip that is used as
a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
- Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the
Xuantie C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those
included there are 39 new board files, but only five more 32-bit this
time, probably a new low:
- Marantec Maveo board based on dhcor imx6ull module
- Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
- Epson Moverio BT-200 AR glasses based on TI OMAP4
- PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
- ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than we had
in the recent releases:
- Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM
EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device.
- NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234
- Qualcomm gains support for 6 reference boards on various members of
their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua
phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top
of the various reference platforms for their new chips.
- Rockchips support for several newer boards: Indiedroid Nova
(rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM
NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn
Fastrhino R66S/R68S (rk3568)
- TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex
Verdin family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
- continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
- support for devicetree overlays on at91, bcm283x
- significant additions to existing SoC support on mediatek,
qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST
STM32MP1
As usual, a lot more detail is available in the individual merge
commits"
* tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits)
ARM: mvebu: fix unit address on armada-390-db flash
ARM: dts: Move .dts files to vendor sub-directories
kbuild: Support flat DTBs install
ARM: dts: Add .dts files missing from the build
ARM: dts: allwinner: Use quoted #include
ARM: dts: lan966x: kontron-d10: add PHY interrupts
ARM: dts: lan966x: kontron-d10: fix SPI CS
ARM: dts: lan966x: kontron-d10: fix board reset
ARM: dts: at91: Enable device-tree overlay support for AT91 boards
arm: dts: Enable device-tree overlay support for AT91 boards
arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller
ARM: dts: at91: use generic name for shutdown controller
ARM: dts: BCM5301X: Add cells sizes to PCIe nodes
dt-bindings: firmware: brcm,kona-smc: convert to YAML
riscv: dts: sort makefile entries by directory
riscv: defconfig: enable T-HEAD SoC
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: Add the T-HEAD SoC family Kconfig option
...
652 lines
15 KiB
Plaintext
652 lines
15 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8660.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm MSM8660";
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compatible = "qcom,msm8660";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "qcom,scorpion";
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enable-method = "qcom,gcc-msm8660";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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compatible = "qcom,scorpion";
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enable-method = "qcom,gcc-msm8660";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0>;
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};
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cpu-pmu {
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compatible = "qcom,scorpion-mp-pmu";
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interrupts = <1 9 0x304>;
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};
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clocks {
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cxo_board: cxo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "cxo_board";
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};
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pxo_board: pxo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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clock-output-names = "pxo_board";
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};
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sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "sleep_clk";
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};
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};
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/*
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* These channels from the ADC are simply hardware monitors.
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* That is why the ADC is referred to as "HKADC" - HouseKeeping
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* ADC.
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*/
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iio-hwmon {
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compatible = "iio-hwmon";
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io-channels = <&xoadc 0x00 0x01>, /* Battery */
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<&xoadc 0x00 0x02>, /* DC in (charger) */
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<&xoadc 0x00 0x04>, /* VPH the main system voltage */
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<&xoadc 0x00 0x0b>, /* Die temperature */
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<&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
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<&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
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<&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@2080000 {
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compatible = "qcom,msm-8660-qgic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = < 0x02080000 0x1000 >,
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< 0x02081000 0x1000 >;
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};
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timer@2000000 {
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 0 0x301>,
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<1 1 0x301>,
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<1 2 0x301>;
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reg = <0x02000000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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tlmm: pinctrl@800000 {
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compatible = "qcom,msm8660-pinctrl";
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reg = <0x800000 0x4000>;
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gpio-controller;
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gpio-ranges = <&tlmm 0 0 173>;
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#gpio-cells = <2>;
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interrupts = <0 16 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-msm8660";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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reg = <0x900000 0x4000>;
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clocks = <&pxo_board>, <&cxo_board>;
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clock-names = "pxo", "cxo";
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};
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gsbi1: gsbi@16000000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x16000000 0x100>;
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clocks = <&gcc GSBI1_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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status = "disabled";
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gsbi1_spi: spi@16080000 {
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compatible = "qcom,spi-qup-v1.1.1";
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reg = <0x16080000 0x1000>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsbi3: gsbi@16200000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x16200000 0x100>;
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clocks = <&gcc GSBI3_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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status = "disabled";
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gsbi3_i2c: i2c@16280000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16280000 0x1000>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsbi6: gsbi@16500000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x16500000 0x100>;
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clocks = <&gcc GSBI6_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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syscon-tcsr = <&tcsr>;
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gsbi6_serial: serial@16540000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16540000 0x1000>,
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<0x16500000 0x1000>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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gsbi6_i2c: i2c@16580000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16580000 0x1000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsbi7: gsbi@16600000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x16600000 0x100>;
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clocks = <&gcc GSBI7_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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syscon-tcsr = <&tcsr>;
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gsbi7_serial: serial@16640000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16640000 0x1000>,
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<0x16600000 0x1000>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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gsbi7_i2c: i2c@16680000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16680000 0x1000>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsbi8: gsbi@19800000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x19800000 0x100>;
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clocks = <&gcc GSBI8_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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status = "disabled";
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gsbi8_i2c: i2c@19880000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x19880000 0x1000>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsbi12: gsbi@19c00000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x19c00000 0x100>;
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clocks = <&gcc GSBI12_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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gsbi12_serial: serial@19c40000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x19c40000 0x1000>,
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<0x19c00000 0x1000>;
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interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
gsbi12_i2c: i2c@19c80000 {
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
reg = <0x19c80000 0x1000>;
|
|
interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
ebi2: external-bus@1a100000 {
|
|
compatible = "qcom,msm8660-ebi2";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x0 0x1a800000 0x00800000>,
|
|
<1 0x0 0x1b000000 0x00800000>,
|
|
<2 0x0 0x1b800000 0x00800000>,
|
|
<3 0x0 0x1d000000 0x08000000>,
|
|
<4 0x0 0x1c800000 0x00800000>,
|
|
<5 0x0 0x1c000000 0x00800000>;
|
|
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
|
|
reg-names = "ebi2", "xmem";
|
|
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
|
|
clock-names = "ebi2x", "ebi2";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssbi@500000 {
|
|
compatible = "qcom,ssbi";
|
|
reg = <0x500000 0x1000>;
|
|
qcom,controller-type = "pmic-arbiter";
|
|
|
|
pm8058: pmic {
|
|
compatible = "qcom,pm8058";
|
|
interrupt-parent = <&tlmm>;
|
|
interrupts = <88 8>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pm8058_gpio: gpio@150 {
|
|
compatible = "qcom,pm8058-gpio",
|
|
"qcom,ssbi-gpio";
|
|
reg = <0x150>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pm8058_gpio 0 0 44>;
|
|
#gpio-cells = <2>;
|
|
|
|
};
|
|
|
|
pm8058_mpps: mpps@50 {
|
|
compatible = "qcom,pm8058-mpp",
|
|
"qcom,ssbi-mpp";
|
|
reg = <0x50>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pm8058_mpps 0 0 12>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pwrkey@1c {
|
|
compatible = "qcom,pm8058-pwrkey";
|
|
reg = <0x1c>;
|
|
interrupt-parent = <&pm8058>;
|
|
interrupts = <50 1>, <51 1>;
|
|
debounce = <15625>;
|
|
pull-up;
|
|
};
|
|
|
|
pm8058_keypad: keypad@148 {
|
|
compatible = "qcom,pm8058-keypad";
|
|
reg = <0x148>;
|
|
interrupt-parent = <&pm8058>;
|
|
interrupts = <74 1>, <75 1>;
|
|
debounce = <15>;
|
|
scan-delay = <32>;
|
|
row-hold = <91500>;
|
|
};
|
|
|
|
xoadc: xoadc@197 {
|
|
compatible = "qcom,pm8058-adc";
|
|
reg = <0x197>;
|
|
interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
#io-channel-cells = <2>;
|
|
|
|
vcoin: adc-channel@0 {
|
|
reg = <0x00 0x00>;
|
|
};
|
|
vbat: adc-channel@1 {
|
|
reg = <0x00 0x01>;
|
|
};
|
|
dcin: adc-channel@2 {
|
|
reg = <0x00 0x02>;
|
|
};
|
|
ichg: adc-channel@3 {
|
|
reg = <0x00 0x03>;
|
|
};
|
|
vph_pwr: adc-channel@4 {
|
|
reg = <0x00 0x04>;
|
|
};
|
|
usb_vbus: adc-channel@a {
|
|
reg = <0x00 0x0a>;
|
|
};
|
|
die_temp: adc-channel@b {
|
|
reg = <0x00 0x0b>;
|
|
};
|
|
ref_625mv: adc-channel@c {
|
|
reg = <0x00 0x0c>;
|
|
};
|
|
ref_1250mv: adc-channel@d {
|
|
reg = <0x00 0x0d>;
|
|
};
|
|
ref_325mv: adc-channel@e {
|
|
reg = <0x00 0x0e>;
|
|
};
|
|
ref_muxoff: adc-channel@f {
|
|
reg = <0x00 0x0f>;
|
|
};
|
|
};
|
|
|
|
rtc@1e8 {
|
|
compatible = "qcom,pm8058-rtc";
|
|
reg = <0x1e8>;
|
|
interrupt-parent = <&pm8058>;
|
|
interrupts = <39 1>;
|
|
allow-set-time;
|
|
};
|
|
|
|
vibrator@4a {
|
|
compatible = "qcom,pm8058-vib";
|
|
reg = <0x4a>;
|
|
};
|
|
|
|
pm8058_led48: led@48 {
|
|
compatible = "qcom,pm8058-keypad-led";
|
|
reg = <0x48>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pm8058_led131: led@131 {
|
|
compatible = "qcom,pm8058-led";
|
|
reg = <0x131>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pm8058_led132: led@132 {
|
|
compatible = "qcom,pm8058-led";
|
|
reg = <0x132>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pm8058_led133: led@133 {
|
|
compatible = "qcom,pm8058-led";
|
|
reg = <0x133>;
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
l2cc: clock-controller@2082000 {
|
|
compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon";
|
|
reg = <0x02082000 0x1000>;
|
|
};
|
|
|
|
rpm: rpm@104000 {
|
|
compatible = "qcom,rpm-msm8660";
|
|
reg = <0x00104000 0x1000>;
|
|
qcom,ipc = <&l2cc 0x8 2>;
|
|
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "ack", "err", "wakeup";
|
|
clocks = <&gcc RPM_MSG_RAM_H_CLK>;
|
|
clock-names = "ram";
|
|
|
|
rpmcc: clock-controller {
|
|
compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
|
|
#clock-cells = <1>;
|
|
clocks = <&pxo_board>;
|
|
clock-names = "pxo";
|
|
};
|
|
|
|
regulators-0 {
|
|
compatible = "qcom,rpm-pm8901-regulators";
|
|
|
|
pm8901_l0: l0 {};
|
|
pm8901_l1: l1 {};
|
|
pm8901_l2: l2 {};
|
|
pm8901_l3: l3 {};
|
|
pm8901_l4: l4 {};
|
|
pm8901_l5: l5 {};
|
|
pm8901_l6: l6 {};
|
|
|
|
/* S0 and S1 Handled as SAW regulators by SPM */
|
|
pm8901_s2: s2 {};
|
|
pm8901_s3: s3 {};
|
|
pm8901_s4: s4 {};
|
|
|
|
pm8901_lvs0: lvs0 {};
|
|
pm8901_lvs1: lvs1 {};
|
|
pm8901_lvs2: lvs2 {};
|
|
pm8901_lvs3: lvs3 {};
|
|
|
|
pm8901_mvs: mvs {};
|
|
};
|
|
|
|
regulators-1 {
|
|
compatible = "qcom,rpm-pm8058-regulators";
|
|
|
|
pm8058_l0: l0 {};
|
|
pm8058_l1: l1 {};
|
|
pm8058_l2: l2 {};
|
|
pm8058_l3: l3 {};
|
|
pm8058_l4: l4 {};
|
|
pm8058_l5: l5 {};
|
|
pm8058_l6: l6 {};
|
|
pm8058_l7: l7 {};
|
|
pm8058_l8: l8 {};
|
|
pm8058_l9: l9 {};
|
|
pm8058_l10: l10 {};
|
|
pm8058_l11: l11 {};
|
|
pm8058_l12: l12 {};
|
|
pm8058_l13: l13 {};
|
|
pm8058_l14: l14 {};
|
|
pm8058_l15: l15 {};
|
|
pm8058_l16: l16 {};
|
|
pm8058_l17: l17 {};
|
|
pm8058_l18: l18 {};
|
|
pm8058_l19: l19 {};
|
|
pm8058_l20: l20 {};
|
|
pm8058_l21: l21 {};
|
|
pm8058_l22: l22 {};
|
|
pm8058_l23: l23 {};
|
|
pm8058_l24: l24 {};
|
|
pm8058_l25: l25 {};
|
|
|
|
pm8058_s0: s0 {};
|
|
pm8058_s1: s1 {};
|
|
pm8058_s2: s2 {};
|
|
pm8058_s3: s3 {};
|
|
pm8058_s4: s4 {};
|
|
|
|
pm8058_lvs0: lvs0 {};
|
|
pm8058_lvs1: lvs1 {};
|
|
|
|
pm8058_ncp: ncp {};
|
|
};
|
|
};
|
|
|
|
amba {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
sdcc1: mmc@12400000 {
|
|
status = "disabled";
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
reg = <0x12400000 0x8000>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <8>;
|
|
max-frequency = <48000000>;
|
|
non-removable;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
};
|
|
|
|
sdcc2: mmc@12140000 {
|
|
status = "disabled";
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
reg = <0x12140000 0x8000>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <8>;
|
|
max-frequency = <48000000>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
};
|
|
|
|
sdcc3: mmc@12180000 {
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
status = "disabled";
|
|
reg = <0x12180000 0x8000>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <4>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
max-frequency = <48000000>;
|
|
no-1-8-v;
|
|
};
|
|
|
|
sdcc4: mmc@121c0000 {
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
status = "disabled";
|
|
reg = <0x121c0000 0x8000>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <4>;
|
|
max-frequency = <48000000>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
};
|
|
|
|
sdcc5: mmc@12200000 {
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
status = "disabled";
|
|
reg = <0x12200000 0x8000>;
|
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <4>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
max-frequency = <48000000>;
|
|
};
|
|
};
|
|
|
|
tcsr: syscon@1a400000 {
|
|
compatible = "qcom,tcsr-msm8660", "syscon";
|
|
reg = <0x1a400000 0x100>;
|
|
};
|
|
};
|
|
|
|
};
|