Joshua Aberback 554ba183b1 drm/amd/display: Align cursor cache address to 2KB ... [Why] The registers for the address of the cursor are aligned to 2KB, so all cursor surfaces also need to be aligned to 2KB. Currently, the provided cursor cache surface is not aligned, so we need a workaround until alignment is enforced by the surface provider. [How] - round up surface address to nearest multiple of 2048 - current policy is to provide a much bigger cache size than necessary,so this operation is safe Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-03-23 23:03:12 -04:00
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amdgpu_dm	drm/amd/display: Fix warning	2021-03-23 23:02:43 -04:00
dc	drm/amd/display: Align cursor cache address to 2KB	2021-03-23 23:03:12 -04:00
dmub	drm/amd/display: [FW Promotion] Release 0.0.55	2021-03-23 23:02:49 -04:00
include	drm/amd/display: Add internal display info	2020-11-24 12:08:15 -05:00
modules	drm/amd/display: Add flag for building infopacket	2021-03-02 14:06:29 -05:00
Kconfig	drm/amd/display: Support crc on specific region	2021-03-05 15:11:47 -05:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards	2019-11-13 15:29:42 -05:00
TODO