Jonathan Marek 544d8b9615 drm/msm/dpu: update UBWC config for sm8150 and sm8250 ... Update the UBWC registers to the right values for sm8150 and sm8250. This removes broken dpu_hw_reset_ubwc, which doesn't work because the "force blk offset to zero to access beginning of register region" hack is copied from downstream, where mapped region starts 0x1000 below what is used in the upstream driver. Also simplifies the overly complicated change that was introduced in e4f9bbe9f8 to work around dpu_hw_reset_ubwc being broken. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>		2020-07-31 06:46:16 -07:00
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drm	drm/msm/dpu: update UBWC config for sm8150 and sm8250	2020-07-31 06:46:16 -07:00
host1x	gpu: host1x: debug: Dump push buffer state	2020-07-17 16:06:14 +02:00
ipu-v3	gpu: ipu-v3: image-convert: Wait for all EOFs before completing a tile	2020-07-20 15:16:05 +02:00
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