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Ampere SoC PMU follows CoreSight PMU architecture. It uses implementation specific registers to filter events rather than PMEVFILTnR registers. Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Link: https://lore.kernel.org/r/20230913233941.9814-5-ilkka@os.amperecomputing.com [will: Include linux/io.h in ampere_cspmu.c for writel()] Signed-off-by: Will Deacon <will@kernel.org> |
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| .. | ||
| alibaba_pmu.rst | ||
| ampere_cspmu.rst | ||
| arm_dsu_pmu.rst | ||
| arm-ccn.rst | ||
| arm-cmn.rst | ||
| cxl.rst | ||
| hisi-pcie-pmu.rst | ||
| hisi-pmu.rst | ||
| hns3-pmu.rst | ||
| imx-ddr.rst | ||
| index.rst | ||
| meson-ddr-pmu.rst | ||
| nvidia-pmu.rst | ||
| qcom_l2_pmu.rst | ||
| qcom_l3_pmu.rst | ||
| thunderx2-pmu.rst | ||
| xgene-pmu.rst | ||