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b9b721d117
TLB sync timeouts can be due to various reasons such as TBU power down or pending TCU/TBU invalidation/sync and so on. Debugging these often require dumping of some implementation defined registers to know the status of TBU/TCU operations and some of these registers are not accessible in non-secure world such as from kernel and requires SMC calls to read them in the secure world. So, add this debug support to dump implementation defined registers for TLB sync timeout issues. Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Acked-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/20220708094230.4349-1-quic_saipraka@quicinc.com Signed-off-by: Will Deacon <will@kernel.org>
143 lines
4.2 KiB
C
143 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/of_device.h>
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#include <linux/qcom_scm.h>
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#include <linux/ratelimit.h>
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#include "arm-smmu.h"
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#include "arm-smmu-qcom.h"
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enum qcom_smmu_impl_reg_offset {
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QCOM_SMMU_TBU_PWR_STATUS,
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QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
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QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
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};
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struct qcom_smmu_config {
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const u32 *reg_offset;
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};
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void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
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{
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int ret;
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u32 tbu_pwr_status, sync_inv_ack, sync_inv_progress;
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struct qcom_smmu *qsmmu = container_of(smmu, struct qcom_smmu, smmu);
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const struct qcom_smmu_config *cfg;
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static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
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DEFAULT_RATELIMIT_BURST);
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if (__ratelimit(&rs)) {
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dev_err(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n");
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cfg = qsmmu->cfg;
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if (!cfg)
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return;
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ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_TBU_PWR_STATUS],
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&tbu_pwr_status);
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if (ret)
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dev_err(smmu->dev,
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"Failed to read TBU power status: %d\n", ret);
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ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK],
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&sync_inv_ack);
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if (ret)
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dev_err(smmu->dev,
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"Failed to read TBU sync/inv ack status: %d\n", ret);
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ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR],
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&sync_inv_progress);
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if (ret)
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dev_err(smmu->dev,
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"Failed to read TCU syn/inv progress: %d\n", ret);
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dev_err(smmu->dev,
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"TBU: power_status %#x sync_inv_ack %#x sync_inv_progress %#x\n",
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tbu_pwr_status, sync_inv_ack, sync_inv_progress);
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}
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}
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/* Implementation Defined Register Space 0 register offsets */
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static const u32 qcom_smmu_impl0_reg_offset[] = {
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[QCOM_SMMU_TBU_PWR_STATUS] = 0x2204,
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[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK] = 0x25dc,
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[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR] = 0x2670,
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};
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static const struct qcom_smmu_config qcm2290_smmu_cfg = {
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.reg_offset = qcom_smmu_impl0_reg_offset,
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};
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static const struct qcom_smmu_config sc7180_smmu_cfg = {
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.reg_offset = qcom_smmu_impl0_reg_offset,
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};
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static const struct qcom_smmu_config sc7280_smmu_cfg = {
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.reg_offset = qcom_smmu_impl0_reg_offset,
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};
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static const struct qcom_smmu_config sc8180x_smmu_cfg = {
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.reg_offset = qcom_smmu_impl0_reg_offset,
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};
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static const struct qcom_smmu_config sc8280xp_smmu_cfg = {
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.reg_offset = qcom_smmu_impl0_reg_offset,
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};
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static const struct qcom_smmu_config sm6125_smmu_cfg = {
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.reg_offset = qcom_smmu_impl0_reg_offset,
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};
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static const struct qcom_smmu_config sm6350_smmu_cfg = {
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.reg_offset = qcom_smmu_impl0_reg_offset,
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};
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static const struct qcom_smmu_config sm8150_smmu_cfg = {
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.reg_offset = qcom_smmu_impl0_reg_offset,
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};
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static const struct qcom_smmu_config sm8250_smmu_cfg = {
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.reg_offset = qcom_smmu_impl0_reg_offset,
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};
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static const struct qcom_smmu_config sm8350_smmu_cfg = {
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.reg_offset = qcom_smmu_impl0_reg_offset,
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};
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static const struct qcom_smmu_config sm8450_smmu_cfg = {
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.reg_offset = qcom_smmu_impl0_reg_offset,
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};
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static const struct of_device_id __maybe_unused qcom_smmu_impl_debug_match[] = {
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{ .compatible = "qcom,msm8998-smmu-v2" },
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{ .compatible = "qcom,qcm2290-smmu-500", .data = &qcm2290_smmu_cfg },
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{ .compatible = "qcom,sc7180-smmu-500", .data = &sc7180_smmu_cfg },
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{ .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_cfg},
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{ .compatible = "qcom,sc8180x-smmu-500", .data = &sc8180x_smmu_cfg },
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{ .compatible = "qcom,sc8280xp-smmu-500", .data = &sc8280xp_smmu_cfg },
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{ .compatible = "qcom,sdm630-smmu-v2" },
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{ .compatible = "qcom,sdm845-smmu-500" },
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{ .compatible = "qcom,sm6125-smmu-500", .data = &sm6125_smmu_cfg},
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{ .compatible = "qcom,sm6350-smmu-500", .data = &sm6350_smmu_cfg},
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{ .compatible = "qcom,sm8150-smmu-500", .data = &sm8150_smmu_cfg },
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{ .compatible = "qcom,sm8250-smmu-500", .data = &sm8250_smmu_cfg },
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{ .compatible = "qcom,sm8350-smmu-500", .data = &sm8350_smmu_cfg },
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{ .compatible = "qcom,sm8450-smmu-500", .data = &sm8450_smmu_cfg },
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{ }
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};
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const void *qcom_smmu_impl_data(struct arm_smmu_device *smmu)
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{
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const struct of_device_id *match;
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const struct device_node *np = smmu->dev->of_node;
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match = of_match_node(qcom_smmu_impl_debug_match, np);
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if (!match)
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return NULL;
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return match->data;
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}
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