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21857088fa
This reverts commitafcbe252e9. The commit in question caused my sc7280-herobrine-herobrine-r1 board not to boot anymore. This shouldn't be too surprising since the driver is relying on the name "cqhci". The issue seems to be that someone decided to change the names of things when the binding moved from .txt to .yaml. We should go back to the names that the bindings have historically specified. For some history, see commitd3392339ca("mmc: cqhci: Update cqhci memory ioresource name") and commitd79100c91a("dt-bindings: mmc: sdhci-msm: Add CQE reg map"). Fixes:afcbe252e9("arm64: dts: qcom: Fix 'reg-names' for sdhci nodes") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706144706.1.I48f35820bf3670d54940110462555c2d0a6d5eb2@changeid
659 lines
13 KiB
Plaintext
659 lines
13 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2021, Martin Botka <martin.botka@somainline.org>
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*/
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#include <dt-bindings/clock/qcom,gcc-sm6125.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "xo_board";
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-output-names = "sleep_clk";
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x0 0x0>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x0 0x1>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x0 0x2>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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next-level-cache = <&L2_0>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x0 0x3>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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next-level-cache = <&L2_0>;
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};
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CPU4: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x0 0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <1638>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "cache";
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};
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};
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CPU5: cpu@101 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x0 0x101>;
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enable-method = "psci";
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capacity-dmips-mhz = <1638>;
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next-level-cache = <&L2_1>;
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};
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CPU6: cpu@102 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x0 0x102>;
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enable-method = "psci";
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capacity-dmips-mhz = <1638>;
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next-level-cache = <&L2_1>;
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};
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CPU7: cpu@103 {
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device_type = "cpu";
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compatible = "qcom,kryo260";
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reg = <0x0 0x103>;
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enable-method = "psci";
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capacity-dmips-mhz = <1638>;
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next-level-cache = <&L2_1>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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firmware {
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scm: scm {
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compatible = "qcom,scm-sm6125", "qcom,scm";
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#reset-cells = <1>;
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};
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};
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memory@40000000 {
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x40000000 0x0 0x0>;
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device_type = "memory";
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: memory@45700000 {
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reg = <0x0 0x45700000 0x0 0x600000>;
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no-map;
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};
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xbl_aop_mem: memory@45e00000 {
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reg = <0x0 0x45e00000 0x0 0x140000>;
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no-map;
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};
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sec_apps_mem: memory@45fff000 {
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reg = <0x0 0x45fff000 0x0 0x1000>;
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no-map;
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};
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smem_mem: memory@46000000 {
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reg = <0x0 0x46000000 0x0 0x200000>;
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no-map;
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};
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reserved_mem1: memory@46200000 {
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reg = <0x0 0x46200000 0x0 0x2d00000>;
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no-map;
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};
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camera_mem: memory@4ab00000 {
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reg = <0x0 0x4ab00000 0x0 0x500000>;
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no-map;
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};
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modem_mem: memory@4b000000 {
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reg = <0x0 0x4b000000 0x0 0x7e00000>;
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no-map;
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};
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venus_mem: memory@52e00000 {
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reg = <0x0 0x52e00000 0x0 0x500000>;
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no-map;
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};
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wlan_msa_mem: memory@53300000 {
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reg = <0x0 0x53300000 0x0 0x200000>;
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no-map;
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};
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cdsp_mem: memory@53500000 {
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reg = <0x0 0x53500000 0x0 0x1e00000>;
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no-map;
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};
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adsp_pil_mem: memory@55300000 {
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reg = <0x0 0x55300000 0x0 0x1e00000>;
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no-map;
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};
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ipa_fw_mem: memory@57100000 {
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reg = <0x0 0x57100000 0x0 0x10000>;
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no-map;
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};
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ipa_gsi_mem: memory@57110000 {
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reg = <0x0 0x57110000 0x0 0x5000>;
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no-map;
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};
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gpu_mem: memory@57115000 {
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reg = <0x0 0x57115000 0x0 0x2000>;
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no-map;
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};
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cont_splash_mem: memory@5c000000 {
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reg = <0x0 0x5c000000 0x0 0x00f00000>;
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no-map;
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};
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dfps_data_mem: memory@5cf00000 {
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reg = <0x0 0x5cf00000 0x0 0x0100000>;
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no-map;
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};
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cdsp_sec_mem: memory@5f800000 {
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reg = <0x0 0x5f800000 0x0 0x1e00000>;
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no-map;
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};
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qseecom_mem: memory@5e400000 {
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reg = <0x0 0x5e400000 0x0 0x1400000>;
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no-map;
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};
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sdsp_mem: memory@f3000000 {
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reg = <0x0 0xf3000000 0x0 0x400000>;
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no-map;
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};
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adsp_mem: memory@f3400000 {
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reg = <0x0 0xf3400000 0x0 0x800000>;
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no-map;
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};
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qseecom_ta_mem: memory@13fc00000 {
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reg = <0x1 0x3fc00000 0x0 0x400000>;
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no-map;
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};
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&apcs_glb 0>;
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rpm_requests: rpm-requests {
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compatible = "qcom,rpm-sm6125";
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qcom,glink-channels = "rpm_requests";
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rpmcc: clock-controller {
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compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
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#clock-cells = <1>;
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};
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rpmpd: power-controller {
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compatible = "qcom,sm6125-rpmpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmpd_opp_table>;
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rpmpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmpd_opp_ret: opp1 {
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opp-level = <RPM_SMD_LEVEL_RETENTION>;
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};
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rpmpd_opp_ret_plus: opp2 {
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opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
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};
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rpmpd_opp_min_svs: opp3 {
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opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
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};
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rpmpd_opp_low_svs: opp4 {
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opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
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};
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rpmpd_opp_svs: opp5 {
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opp-level = <RPM_SMD_LEVEL_SVS>;
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};
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rpmpd_opp_svs_plus: opp6 {
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opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
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};
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rpmpd_opp_nom: opp7 {
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opp-level = <RPM_SMD_LEVEL_NOM>;
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};
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rpmpd_opp_nom_plus: opp8 {
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opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
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};
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rpmpd_opp_turbo: opp9 {
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opp-level = <RPM_SMD_LEVEL_TURBO>;
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};
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rpmpd_opp_turbo_no_cpr: opp10 {
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opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
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};
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};
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};
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};
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};
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smem: smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x00 0xffffffff>;
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compatible = "simple-bus";
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tcsr_mutex: hwlock@340000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x00340000 0x20000>;
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#hwlock-cells = <1>;
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};
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tlmm: pinctrl@500000 {
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compatible = "qcom,sm6125-tlmm";
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reg = <0x00500000 0x400000>,
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<0x00900000 0x400000>,
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<0x00d00000 0x400000>;
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reg-names = "west", "south", "east";
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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gpio-ranges = <&tlmm 0 0 134>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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sdc2_off_state: sdc2-off-state {
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clk {
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pins = "sdc2_clk";
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drive-strength = <2>;
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bias-disable;
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};
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cmd {
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pins = "sdc2_cmd";
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drive-strength = <2>;
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bias-pull-up;
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};
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data {
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pins = "sdc2_data";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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sdc2_on_state: sdc2-on-state {
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clk {
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pins = "sdc2_clk";
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drive-strength = <16>;
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bias-disable;
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};
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cmd {
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pins = "sdc2_cmd";
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drive-strength = <10>;
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bias-pull-up;
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};
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data {
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pins = "sdc2_data";
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drive-strength = <10>;
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bias-pull-up;
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};
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};
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};
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gcc: clock-controller@1400000 {
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compatible = "qcom,gcc-sm6125";
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reg = <0x01400000 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clock-names = "bi_tcxo", "sleep_clk";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
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};
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hsusb_phy1: phy@1613000 {
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compatible = "qcom,msm8996-qusb2-phy";
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reg = <0x01613000 0x180>;
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#phy-cells = <0>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&gcc GCC_AHB2PHY_USB_CLK>;
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clock-names = "ref", "cfg_ahb";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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status = "disabled";
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};
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rpm_msg_ram: sram@45f0000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0x045f0000 0x7000>;
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};
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sdhc_1: mmc@4744000 {
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compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
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reg-names = "hc", "core";
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interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_SDCC1_APPS_CLK>,
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<&xo_board>;
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clock-names = "iface", "core", "xo";
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power-domains = <&rpmpd SM6125_VDDCX>;
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qcom,dll-config = <0x000f642c>;
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qcom,ddr-config = <0x80040873>;
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bus-width = <8>;
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non-removable;
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status = "disabled";
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};
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sdhc_2: mmc@4784000 {
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compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x04784000 0x1000>;
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reg-names = "hc";
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interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_AHB_CLK>,
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<&gcc GCC_SDCC2_APPS_CLK>,
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<&xo_board>;
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clock-names = "iface", "core", "xo";
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pinctrl-0 = <&sdc2_on_state>;
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pinctrl-1 = <&sdc2_off_state>;
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pinctrl-names = "default", "sleep";
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power-domains = <&rpmpd SM6125_VDDCX>;
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qcom,dll-config = <0x0007642c>;
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qcom,ddr-config = <0x80040873>;
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bus-width = <4>;
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status = "disabled";
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};
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usb3: usb@4ef8800 {
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compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
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reg = <0x04ef8800 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_CLK>;
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clock-names = "cfg_noc",
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"core",
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"iface",
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"sleep",
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"mock_utmi",
|
|
"xo";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <66666667>;
|
|
|
|
power-domains = <&gcc USB30_PRIM_GDSC>;
|
|
qcom,select-utmi-as-pipe-clk;
|
|
status = "disabled";
|
|
|
|
usb3_dwc3: usb@4e00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x04e00000 0xcd00>;
|
|
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&hsusb_phy1>;
|
|
phy-names = "usb2-phy";
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
maximum-speed = "high-speed";
|
|
dr_mode = "peripheral";
|
|
};
|
|
};
|
|
|
|
sram@4690000 {
|
|
compatible = "qcom,rpm-stats";
|
|
reg = <0x04690000 0x10000>;
|
|
};
|
|
|
|
spmi_bus: spmi@1c40000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x01c40000 0x1100>,
|
|
<0x01e00000 0x2000000>,
|
|
<0x03e00000 0x100000>,
|
|
<0x03f00000 0xa0000>,
|
|
<0x01c0a000 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
cell-index = <0>;
|
|
};
|
|
|
|
apcs_glb: mailbox@f111000 {
|
|
compatible = "qcom,sm6125-apcs-hmss-global";
|
|
reg = <0x0f111000 0x1000>;
|
|
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
timer@f120000 {
|
|
compatible = "arm,armv7-timer-mem";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
reg = <0x0f120000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@f121000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0f121000 0x1000>,
|
|
<0x0f122000 0x1000>;
|
|
};
|
|
|
|
frame@f123000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0f123000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f124000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0f124000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f125000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0f125000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f126000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0f126000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f127000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0f127000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@f128000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0f128000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@f200000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x0f200000 0x20000>,
|
|
<0x0f300000 0x100000>;
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 1 0xf08
|
|
GIC_PPI 2 0xf08
|
|
GIC_PPI 3 0xf08
|
|
GIC_PPI 0 0xf08>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
};
|