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907bb57aa7
Core changes:
- New helpers from Andy such as for_each_gpiochip_node() affecting both
GPIO and pin control, improving a bunch of drivers in the process.
- Pulled in Marc Zyngiers work to make IRQ chips immutable, and started
to apply fixups on top.
New drivers:
- New driver for Marvell MVEBU 98DX2530.
- New driver for Mediatek MT8195.
- Support Qualcomm PMX65 and PM6125.
- New driver for Qualcomm SC7280 LPASS pin control.
- New driver for Rockchip RK3588.
- New driver for NXP Freescale i.MXRT1170.
- New driver for Mediatek MT6795 Helio X10.
Improvements:
- Several Aspeed G6 cleanups and non-critical fixes.
- Thorought refactoring of some of the ever improving Renesas drivers.
- Clean up Mediatek MT8192 bindings a bit.
- PWM output and clock monitoring in the Ocelot LAN966x driver.
- Thorough refactoring and cleanup of the Ralink drivers such as
RT2880, RT3883, RT305X, MT7620, MT7621, MT7628 splitting these into proper
sub-drivers.
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Merge tag 'pinctrl-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Pretty big this time. Mostly due to (nice) Renesas refactorings.
Core changes:
- New helpers from Andy such as for_each_gpiochip_node() affecting
both GPIO and pin control, improving a bunch of drivers in the
process.
- Pulled in Marc Zyngiers work to make IRQ chips immutable, and
started to apply fixups on top.
New drivers:
- New driver for Marvell MVEBU 98DX2530.
- New driver for Mediatek MT8195.
- Support Qualcomm PMX65 and PM6125.
- New driver for Qualcomm SC7280 LPASS pin control.
- New driver for Rockchip RK3588.
- New driver for NXP Freescale i.MXRT1170.
- New driver for Mediatek MT6795 Helio X10.
Improvements:
- Several Aspeed G6 cleanups and non-critical fixes.
- Thorought refactoring of some of the ever improving Renesas
drivers.
- Clean up Mediatek MT8192 bindings a bit.
- PWM output and clock monitoring in the Ocelot LAN966x driver.
- Thorough refactoring and cleanup of the Ralink drivers such as
RT2880, RT3883, RT305X, MT7620, MT7621, MT7628 splitting these into
proper sub-drivers"
* tag 'pinctrl-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (161 commits)
pinctrl: apple: Use a raw spinlock for the regmap
pinctrl: berlin: bg4ct: Use devm_platform_*ioremap_resource() APIs
pinctrl: intel: Fix kernel doc format, i.e. add return sections
dt-bindings: pinctrl: qcom: Drop 'maxItems' on 'wakeup-parent'
pinctrl: starfive: Make the irqchip immutable
pinctrl: mediatek: Add pinctrl driver for MT6795 Helio X10
dt-bindings: pinctrl: Add MediaTek MT6795 pinctrl bindings
pinctrl: freescale: Add i.MXRT1170 pinctrl driver support
dt-bindings: pinctrl: add i.MXRT1170 pinctrl Documentation
dt-bindings: pinctrl: rockchip: increase max amount of device functions
dt-bindings: pinctrl: qcom,pmic-gpio: add 'gpio-reserved-ranges'
dt-bindings: pinctrl: qcom,pmic-gpio: add 'input-disable'
dt-bindings: pinctrl: qcom,pmic-gpio: describe gpio-line-names
dt-bindings: pinctrl: qcom,pmic-gpio: fix matching pin config
dt-bindings: pinctrl: qcom,pmic-gpio: document PM8150L and PMM8155AU
pinctrl: qcom: spmi-gpio: Add pm6125 compatible
dt-bindings: pinctrl: qcom-pmic-gpio: Add pm6125 compatible
pinctrl: intel: Drop unused irqchip member in struct intel_pinctrl
pinctrl: intel: make irq_chip immutable
pinctrl: cherryview: Use GPIO chip pointer in chv_gpio_irq_mask_unmask()
...
79 lines
2.5 KiB
Plaintext
79 lines
2.5 KiB
Plaintext
PDC interrupt controller
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Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
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Power Domain Controller (PDC) that is on always-on domain. In addition to
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providing power control for the power domains, the hardware also has an
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interrupt controller that can be used to help detect edge low interrupts as
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well detect interrupts when the GIC is non-operational.
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GIC is parent interrupt controller at the highest level. Platform interrupt
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controller PDC is next in hierarchy, followed by others. Drivers requiring
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wakeup capabilities of their device interrupts routed through the PDC, must
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specify PDC as their interrupt controller and request the PDC port associated
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with the GIC interrupt. See example below.
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Properties:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"
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- "qcom,sc7180-pdc": For SC7180
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- "qcom,sc7280-pdc": For SC7280
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- "qcom,sdm845-pdc": For SDM845
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- "qcom,sm6350-pdc": For SM6350
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- "qcom,sm8150-pdc": For SM8150
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- "qcom,sm8250-pdc": For SM8250
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- "qcom,sm8350-pdc": For SM8350
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: Specifies the base physical address for PDC hardware.
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- interrupt-cells:
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Usage: required
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Value type: <u32>
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Definition: Specifies the number of cells needed to encode an interrupt
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source.
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Must be 2.
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The first element of the tuple is the PDC pin for the
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interrupt.
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The second element is the trigger type.
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- interrupt-controller:
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Usage: required
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Value type: <bool>
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Definition: Identifies the node as an interrupt controller.
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- qcom,pdc-ranges:
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Usage: required
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Value type: <u32 array>
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Definition: Specifies the PDC pin offset and the number of PDC ports.
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The tuples indicates the valid mapping of valid PDC ports
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and their hwirq mapping.
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The first element of the tuple is the starting PDC port.
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The second element is the GIC hwirq number for the PDC port.
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The third element is the number of interrupts in sequence.
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Example:
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sdm845-pdc";
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reg = <0xb220000 0x30000>;
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qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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DT binding of a device that wants to use the GIC SPI 514 as a wakeup
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interrupt, must do -
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wake-device {
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interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
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};
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In this case interrupt 514 would be mapped to port 2 on the PDC as defined by
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the qcom,pdc-ranges property.
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