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48ce8f80f5
Using IRQ priority masking to enable/disable interrupts is a bit sensitive as it requires to deal with both ICC_PMR_EL1 and PSR.I. Introduce some validity checks to both highlight the states in which functions dealing with IRQ enabling/disabling can (not) be called, and bark a warning when called in an unexpected state. Since these checks are done on hotpaths, introduce a build option to choose whether to do the checking. Cc: Will Deacon <will.deacon@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Julien Thierry <julien.thierry@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
144 lines
3.3 KiB
C
144 lines
3.3 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_IRQFLAGS_H
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#define __ASM_IRQFLAGS_H
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#ifdef __KERNEL__
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#include <asm/alternative.h>
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#include <asm/ptrace.h>
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#include <asm/sysreg.h>
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/*
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* Aarch64 has flags for masking: Debug, Asynchronous (serror), Interrupts and
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* FIQ exceptions, in the 'daif' register. We mask and unmask them in 'dai'
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* order:
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* Masking debug exceptions causes all other exceptions to be masked too/
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* Masking SError masks irq, but not debug exceptions. Masking irqs has no
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* side effects for other flags. Keeping to this order makes it easier for
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* entry.S to know which exceptions should be unmasked.
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*
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* FIQ is never expected, but we mask it when we disable debug exceptions, and
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* unmask it at all other times.
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*/
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/*
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* CPU interrupt mask handling.
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*/
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static inline void arch_local_irq_enable(void)
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{
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if (system_has_prio_mask_debugging()) {
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u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1);
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WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);
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}
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asm volatile(ALTERNATIVE(
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"msr daifclr, #2 // arch_local_irq_enable\n"
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"nop",
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__msr_s(SYS_ICC_PMR_EL1, "%0")
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"dsb sy",
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ARM64_HAS_IRQ_PRIO_MASKING)
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:
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: "r" ((unsigned long) GIC_PRIO_IRQON)
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: "memory");
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}
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static inline void arch_local_irq_disable(void)
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{
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if (system_has_prio_mask_debugging()) {
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u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1);
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WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);
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}
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asm volatile(ALTERNATIVE(
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"msr daifset, #2 // arch_local_irq_disable",
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__msr_s(SYS_ICC_PMR_EL1, "%0"),
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ARM64_HAS_IRQ_PRIO_MASKING)
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:
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: "r" ((unsigned long) GIC_PRIO_IRQOFF)
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: "memory");
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}
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/*
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* Save the current interrupt enable state.
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*/
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static inline unsigned long arch_local_save_flags(void)
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{
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unsigned long flags;
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asm volatile(ALTERNATIVE(
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"mrs %0, daif",
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__mrs_s("%0", SYS_ICC_PMR_EL1),
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ARM64_HAS_IRQ_PRIO_MASKING)
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: "=&r" (flags)
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:
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: "memory");
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return flags;
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}
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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int res;
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asm volatile(ALTERNATIVE(
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"and %w0, %w1, #" __stringify(PSR_I_BIT),
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"eor %w0, %w1, #" __stringify(GIC_PRIO_IRQON),
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ARM64_HAS_IRQ_PRIO_MASKING)
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: "=&r" (res)
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: "r" ((int) flags)
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: "memory");
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return res;
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}
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static inline unsigned long arch_local_irq_save(void)
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{
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unsigned long flags;
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flags = arch_local_save_flags();
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/*
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* There are too many states with IRQs disabled, just keep the current
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* state if interrupts are already disabled/masked.
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*/
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if (!arch_irqs_disabled_flags(flags))
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arch_local_irq_disable();
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return flags;
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}
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/*
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* restore saved IRQ state
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*/
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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asm volatile(ALTERNATIVE(
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"msr daif, %0\n"
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"nop",
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__msr_s(SYS_ICC_PMR_EL1, "%0")
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"dsb sy",
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ARM64_HAS_IRQ_PRIO_MASKING)
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:
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: "r" (flags)
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: "memory");
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}
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#endif
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#endif
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