Nicholas Kazlauskas 481f576c6c drm/amd/display: Raise dispclk value for dce120 by 15% ... [Why] The DISPCLK value was previously requested to be 15% higher for all ASICs that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and the dce110 set bandwidth codepath this was removed for power saving considerations. That change caused display corruption under certain hardware configurations with Vega10. [How] The 15% DISPCLK increase is brought back but only on dce110 for now. This is should be a temporary workaround until the root cause is sorted out for why this occurs on Vega (or other ASICs, if reported). Tested-by: Nick Sarnie <sarnex@gentoo.org> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2018-09-26 21:09:08 -05:00
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amdgpu_dm	drm/amd/display: Remove mst_hotplug_work	2018-09-26 21:09:07 -05:00
dc	drm/amd/display: Raise dispclk value for dce120 by 15%	2018-09-26 21:09:08 -05:00
include	drm/amd/display: Add Raven2 definitions in dc	2018-09-14 09:36:47 -05:00
modules	drm/amd/display: Stereo 3D support in VSC	2018-09-26 21:09:07 -05:00
Kconfig	drm/amd/display: Add DC config flag for Raven2 (v2)	2018-09-14 09:36:56 -05:00
Makefile	drm/amd/display: Enable Stereo in Dal3	2018-08-27 11:10:57 -05:00
TODO	drm/amd/display: Convert remaining loggers off dc_logger	2018-07-13 14:48:42 -05:00