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Control over clock generation unit is required for further development of Synchronous Ethernet feature. Interface provides ability to obtain current state of a dpll, its sources and outputs which are pins, and allows their configuration. Co-developed-by: Milena Olech <milena.olech@intel.com> Signed-off-by: Milena Olech <milena.olech@intel.com> Co-developed-by: Michal Michalik <michal.michalik@intel.com> Signed-off-by: Michal Michalik <michal.michalik@intel.com> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Signed-off-by: Vadim Fedorenko <vadim.fedorenko@linux.dev> Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| e1000 | ||
| e1000e | ||
| fm10k | ||
| i40e | ||
| iavf | ||
| ice | ||
| idpf | ||
| igb | ||
| igbvf | ||
| igc | ||
| ixgbe | ||
| ixgbevf | ||
| e100.c | ||
| Kconfig | ||
| Makefile | ||