Jake Wang 410066d24c drm/amd/display: updated wm table for Renoir ... [Why] For certain timings, Renoir may underflow due to sr exit latency being too slow. [How] Updated wm table for renoir. Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-12-15 11:34:23 -05:00
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acp	drm: amd/acp: fix broken menu structure	2020-03-13 11:52:35 -04:00
amdgpu	drm/amdgpu: skip load smu and sdma microcode on sriov for SIENNA_CICHLID	2020-12-15 11:33:16 -05:00
amdkfd	drm/amdkfd: correct pipe offset calculation	2020-12-10 16:41:49 -05:00
display	drm/amd/display: updated wm table for Renoir	2020-12-15 11:34:23 -05:00
include	drm/amdgpu: new macro for determining 2ND_USB20PORT support	2020-12-10 16:41:49 -05:00
pm	drm/amdgpu: skip load smu and sdma microcode on sriov for SIENNA_CICHLID	2020-12-15 11:33:16 -05:00