Maíra Canal 40835624ef drm/amdgpu: Write masked value to control register ... On the dce_v6_0 and dce_v8_0 hpd tear down callback, the tmp variable should be written into the control register instead of 0. Reviewed-by: André Almeida <andrealmeid@igalia.com> Signed-off-by: Maíra Canal <mairacanal@riseup.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-07-20 16:03:59 -04:00
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acp
amdgpu	drm/amdgpu: Write masked value to control register	2022-07-20 16:03:59 -04:00
amdkfd	drm/amdkfd: correct the MEC atomic support firmware checking for GC 10.3.7	2022-07-13 11:25:16 -04:00
display	drm/amd/display: Remove unnecessary NULL check in commit_planes_for_stream()	2022-07-18 16:42:39 -04:00
include	drm/amdgpu: add umc v8_10_0 ip headers	2022-07-18 16:37:38 -04:00
pm	drm/amd/pm: enable mode1 reset for smu_v13_0_7	2022-07-18 16:42:39 -04:00