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3f3174996b
AMD Zen-based systems report memory errors through Machine Check banks representing Unified Memory Controllers (UMCs). The address value reported for DRAM ECC errors is a "normalized address" that is relative to the UMC. This normalized address must be converted to a system physical address to be usable by the OS. Support for this address translation was introduced to the MCA subsystem with Zen1 systems. The code was later moved to the AMD64 EDAC module, since this was the only user of the code at the time. However, there are uses for this translation outside of EDAC. The system physical address can be used in MCA for preemptive page offlining as done in some MCA notifier functions. Also, this translation is needed as the basis of similar functionality needed for some CXL configurations on AMD systems. Introduce a common address translation library that can be used for multiple subsystems including MCA, EDAC, and CXL. Include support for UMC normalized to system physical address translation for current CPU systems. The Data Fabric Indirect register access offsets and one of the register fields were changed. Default to the current offsets and register field definition. And fallback to the older values if running on a "legacy" system. Provide built-in code to facilitate the loading and unloading of the library module without affecting other modules or built-in code. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20240123041401.79812-2-yazen.ghannam@amd.com
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __RAS_H__
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#define __RAS_H__
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#include <asm/errno.h>
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#include <linux/uuid.h>
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#include <linux/cper.h>
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#ifdef CONFIG_DEBUG_FS
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int ras_userspace_consumers(void);
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void ras_debugfs_init(void);
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int ras_add_daemon_trace(void);
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#else
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static inline int ras_userspace_consumers(void) { return 0; }
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static inline void ras_debugfs_init(void) { }
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static inline int ras_add_daemon_trace(void) { return 0; }
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#endif
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#ifdef CONFIG_RAS_CEC
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int __init parse_cec_param(char *str);
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#endif
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#ifdef CONFIG_RAS
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void log_non_standard_event(const guid_t *sec_type,
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const guid_t *fru_id, const char *fru_text,
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const u8 sev, const u8 *err, const u32 len);
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void log_arm_hw_error(struct cper_sec_proc_arm *err);
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#else
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static inline void
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log_non_standard_event(const guid_t *sec_type,
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const guid_t *fru_id, const char *fru_text,
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const u8 sev, const u8 *err, const u32 len)
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{ return; }
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static inline void
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log_arm_hw_error(struct cper_sec_proc_arm *err) { return; }
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#endif
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struct atl_err {
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u64 addr;
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u64 ipid;
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u32 cpu;
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};
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#if IS_ENABLED(CONFIG_AMD_ATL)
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void amd_atl_register_decoder(unsigned long (*f)(struct atl_err *));
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void amd_atl_unregister_decoder(void);
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unsigned long amd_convert_umc_mca_addr_to_sys_addr(struct atl_err *err);
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#else
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static inline unsigned long
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amd_convert_umc_mca_addr_to_sys_addr(struct atl_err *err) { return -EINVAL; }
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#endif /* CONFIG_AMD_ATL */
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#endif /* __RAS_H__ */
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