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The Tegra30 USB PHY is a bit different than the Tegra20 PHY: - The EHCI controller supports the HOSTPC register extension, and some of the fields that the PHY needs to modify (PHCD and PTS) have moved to the new HOSTPC register. - Some of the UTMI PLL configuration registers have moved from the USB register space to the Clock-And-Reset controller space. In Tegra30 the clock driver is responsible for configuring the UTMI PLL. - The USBMODE register must be explicitly written to enter host mode. - Certain PHY parameters need to be programmed for optimal signal quality. Support for this will be added in the next patch. The new tegra_phy_soc_config structure is added to describe the differences between the SoCs. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Felipe Balbi <balbi@ti.com> |
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| .. | ||
| association.h | ||
| atmel_usba_udc.h | ||
| audio-v2.h | ||
| audio.h | ||
| c67x00.h | ||
| cdc_ncm.h | ||
| cdc-wdm.h | ||
| ch9.h | ||
| chipidea.h | ||
| composite.h | ||
| dwc3-omap.h | ||
| ehci_def.h | ||
| ehci_pdriver.h | ||
| ezusb.h | ||
| functionfs.h | ||
| g_hid.h | ||
| gadget_configfs.h | ||
| gadget.h | ||
| gpio_vbus.h | ||
| hcd.h | ||
| input.h | ||
| intel_mid_otg.h | ||
| iowarrior.h | ||
| irda.h | ||
| isp116x.h | ||
| isp1301.h | ||
| isp1362.h | ||
| isp1760.h | ||
| m66592.h | ||
| msm_hsusb_hw.h | ||
| msm_hsusb.h | ||
| musb-omap.h | ||
| musb-ux500.h | ||
| musb.h | ||
| net2280.h | ||
| of.h | ||
| ohci_pdriver.h | ||
| omap_control_usb.h | ||
| omap_usb.h | ||
| otg.h | ||
| phy_companion.h | ||
| phy.h | ||
| quirks.h | ||
| r8a66597.h | ||
| renesas_usbhs.h | ||
| rndis_host.h | ||
| samsung_usb_phy.h | ||
| serial.h | ||
| sl811.h | ||
| storage.h | ||
| tegra_usb_phy.h | ||
| tilegx.h | ||
| uas.h | ||
| ulpi.h | ||
| usb_phy_gen_xceiv.h | ||
| usbnet.h | ||
| wusb-wa.h | ||
| wusb.h | ||