Ville Syrjälä 3cdcdc34f3 drm/i915: Eliminate PIPECONF RMWs from .color_commit() ... Eliminate the PIPECONF RMWs from .comit_commit() so that we can finally declare the whole vblank evade part (and the noarm() part) of the pipe commit free of register reads. Or at least I hope that's the last read... Only the i9xx/ilk codepaths need this for now, but let's add the same thing for hsw+ just in case we want to start calling that during fastsets at some point (eg. to change dithering settings/etc.). Should open up the way to start experimenting with different DSB usage approaches for pipe commits. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220413192607.27533-1-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>		2022-06-27 18:31:51 +03:00
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drm	drm/i915: Eliminate PIPECONF RMWs from .color_commit()	2022-06-27 18:31:51 +03:00
host1x	gpu: host1x: Fix a memory leak in 'host1x_remove()'	2022-03-01 11:13:09 +01:00
ipu-v3	gpu: ipu-v3: Fix dev_dbg frequency output	2022-04-04 09:37:42 +02:00
trace
vga	PCI/VGA: Move vgaarb to drivers/pci	2022-03-09 18:30:46 -06:00
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