Nicholas Kazlauskas 33735c1c8d drm/amd/display: Set optimize_pwr_state for DCN31 ... [Why] We'll exit optimized power state to do link detection but we won't enter back into the optimized power state. This could potentially block s2idle entry depending on the sequencing, but it also means we're losing some power during the transition period. [How] Hook up the handler like DCN21. It was also missed like the exit_optimized_pwr_state callback. Fixes: 64b1d0e8d5 ("drm/amd/display: Add DCN3.1 HWSEQ") Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Eric Yang <Eric.Yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-12-28 16:51:24 -05:00
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amdgpu_dm	drm/amd/display: Reset DMCUB before HW init	2021-12-14 17:55:13 -05:00
dc	drm/amd/display: Set optimize_pwr_state for DCN31	2021-12-28 16:51:24 -05:00
dmub	drm/amd/display: [FW Promotion] Release 0.0.91	2021-11-03 12:32:34 -04:00
include	Linux 5.15	2021-11-12 09:23:16 +10:00
modules	drm/amd/display: Fix deadlock when falling back to v2 from v3	2021-10-28 14:26:51 -04:00
Kconfig	drm/amdgpu/display: fix dependencies for DRM_AMD_DC_SI	2021-10-05 10:55:41 -04:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards	2019-11-13 15:29:42 -05:00
TODO