Roman Li 328e34a5ad drm/amd/display: Cap pflip irqs per max otg number ... [Why] pflip interrupt order are mapped 1 to 1 to otg id. e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2... Linux DM registers pflip interrupts per number of crtcs. In fused pipe case crtc numbers can be less than otg id. e.g. if one pipe out of 3(otg#0-2) is fused adev->mode_info.num_crtc=2 so DM only registers irq_src 26,27. This is a bug since if pipe#2 remains unfused DM never gets otg2 pflip interrupt (irq_src=28) That may results in gfx failure due to pflip timeout. [How] Register pflip interrupts per max num of otg instead of num_crtc Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-02-09 15:09:42 -05:00
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acp
amdgpu	drm/amdgpu: add utcl2_harvest to gc 10.3.1	2022-02-09 15:08:05 -05:00
amdkfd	drm/amdkfd: Fix ASIC name typos	2022-01-11 15:44:28 -05:00
display	drm/amd/display: Cap pflip irqs per max otg number	2022-02-09 15:09:42 -05:00
include	drm/amdgpu: add support for IP discovery gc_info table v2	2021-12-17 12:47:29 -05:00
pm	drm/amd/pm: correct the MGpuFanBoost support for Beige Goby	2022-01-31 18:09:55 -05:00