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The clock and data lanes of the DSI PHY have a calibration circuitry feature. As per the MSM DSI PHY tuning guidelines, the drive strength tuning can be done by adjusting rescode offset for hstop/hsbot, and the drive level tuning can be done by adjusting the LDO output level for the HSTX drive. Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1643573719-32095-4-git-send-email-quic_rajeevny@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
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| .. | ||
| phy | ||
| dsi_cfg.c | ||
| dsi_cfg.h | ||
| dsi_host.c | ||
| dsi_manager.c | ||
| dsi_phy_5nm.xml.h | ||
| dsi_phy_7nm.xml.h | ||
| dsi_phy_10nm.xml.h | ||
| dsi_phy_14nm.xml.h | ||
| dsi_phy_20nm.xml.h | ||
| dsi_phy_28nm_8960.xml.h | ||
| dsi_phy_28nm.xml.h | ||
| dsi.c | ||
| dsi.h | ||
| dsi.xml.h | ||
| mmss_cc.xml.h | ||
| sfpb.xml.h | ||