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7bea67a994
A recent change affecting the behaviour of phys_to_dma() to
actually require the device tree ranges to work unmasked a
bug in the Integrator DMA ranges.
The PL110 uses the CMA allocator to obtain coherent allocations
from a dedicated 1MB video memory, leading to the following
call chain:
drm_gem_cma_create()
dma_alloc_attrs()
dma_alloc_from_dev_coherent()
__dma_alloc_from_coherent()
dma_get_device_base()
phys_to_dma()
translate_phys_to_dma()
phys_to_dma() by way of translate_phys_to_dma() will nowadays not
provide 1:1 mappings unless the ranges are properly defined in
the device tree and reflected into the dev->dma_range_map.
There is a bug in the device trees because the DMA ranges are
incorrectly specified, and the patch uncovers this bug.
Solution:
- Fix the LB (logic bus) ranges to be 1-to-1 like they should
have always been.
- Provide a 1:1 dma-ranges attribute to the PL110.
- Mark the PL110 display controller as DMA coherent.
This makes the DMA ranges work right and makes the PL110
framebuffer work again.
Fixes: af6f23b88e ("ARM/dma-mapping: use the generic versions of dma_to_phys/phys_to_dma by default")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220926073311.1610568-1-linus.walleij@linaro.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
277 lines
6.0 KiB
Plaintext
277 lines
6.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree for the ARM Integrator/AP platform
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* with the IM-PD1 example logical module mounted.
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*/
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#include "integratorap.dts"
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/ {
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model = "ARM Integrator/AP with IM-PD1";
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compatible = "arm,integrator-ap";
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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impd1_ram: vram@c2000000 {
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/* 1 MB of designated video RAM on the IM-PD1 */
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compatible = "shared-dma-pool";
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reg = <0xc2000000 0x00100000>;
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no-map;
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};
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};
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};
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&lm0 {
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syscon@0 {
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compatible = "arm,im-pd1-syscon", "syscon";
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reg = <0x00000000 0x1000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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vco1: clock-controller@0 {
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compatible = "arm,impd1-vco1";
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reg = <0x00 0x04>;
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#clock-cells = <0>;
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lock-offset = <0x08>;
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vco-offset = <0x00>;
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clocks = <&sysclk>;
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clock-output-names = "IM-PD1-VCO1";
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};
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vco2: clock-controller@4 {
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compatible = "arm,impd1-vco2";
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reg = <0x04 0x04>;
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#clock-cells = <0>;
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lock-offset = <0x08>;
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vco-offset = <0x04>;
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clocks = <&sysclk>;
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clock-output-names = "IM-PD1-VCO2";
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};
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};
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/* Also used for the Smart Card Interface SCI */
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impd1_uartclk: clock@1_4 {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&vco2>;
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clock-output-names = "VCO2_DIV4";
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};
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/* For the SSP the clock is divided by 64 */
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impd1_sspclk: clock@1_64 {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <64>;
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clock-mult = <1>;
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clocks = <&vco2>;
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clock-output-names = "VCO2_DIV64";
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};
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/* Fixed regulator for the MMC */
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impd1_3v3: regulator {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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/* Push buttons on the IM-PD1 */
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gpio_keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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button@0 {
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debounce-interval = <50>;
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linux,code = <KEY_UP>;
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label = "UP";
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gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>;
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};
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button@1 {
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debounce-interval = <50>;
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linux,code = <KEY_DOWN>;
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label = "DOWN";
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gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>;
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};
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button@2 {
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debounce-interval = <50>;
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linux,code = <KEY_LEFT>;
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label = "LEFT";
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gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>;
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};
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button@3 {
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debounce-interval = <50>;
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linux,code = <KEY_RIGHT>;
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label = "UP";
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gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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button@4 {
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debounce-interval = <50>;
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linux,code = <KEY_ESC>;
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label = "ESC";
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gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>;
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};
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button@5 {
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debounce-interval = <50>;
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linux,code = <KEY_ENTER>;
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label = "ENTER";
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gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>;
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};
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};
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bridge {
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compatible = "ti,ths8134b", "ti,ths8134";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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vga_bridge_in: endpoint {
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remote-endpoint = <&clcd_pads_vga_dac>;
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};
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};
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port@1 {
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reg = <1>;
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vga_bridge_out: endpoint {
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remote-endpoint = <&vga_con_in>;
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};
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};
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};
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_con_in: endpoint {
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remote-endpoint = <&vga_bridge_out>;
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};
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};
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};
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uart@100000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x00100000 0x1000>;
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interrupts-extended = <&impd1_vic 1>;
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clocks = <&impd1_uartclk>, <&sysclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart@200000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x00200000 0x1000>;
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interrupts-extended = <&impd1_vic 2>;
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clocks = <&impd1_uartclk>, <&sysclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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spi@300000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x00300000 0x1000>;
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interrupts-extended = <&impd1_vic 3>;
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clocks = <&impd1_sspclk>, <&sysclk>;
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clock-names = "sspclk", "apb_pclk";
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};
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impd1_gpio0: gpio@400000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x00400000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts-extended = <&impd1_vic 4>;
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clocks = <&sysclk>;
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clock-names = "apb_pclk";
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};
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impd1_gpio1: gpio@500000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x00500000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts-extended = <&impd1_vic 5>;
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clocks = <&sysclk>;
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clock-names = "apb_pclk";
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};
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rtc@600000 {
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compatible = "arm,pl030", "arm,primecell";
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reg = <0x00600000 0x1000>;
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interrupts-extended = <&impd1_vic 6>;
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clocks = <&sysclk>;
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clock-names = "apb_pclk";
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};
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mmc@700000 {
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compatible = "arm,pl181", "arm,primecell";
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reg = <0x00700000 0x1000>;
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interrupts-extended = <&impd1_vic 7>,
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<&impd1_vic 8>;
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clocks = <&sysclk>, <&sysclk>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <1>;
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max-frequency = <515633>;
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vmmc-supply = <&impd1_3v3>;
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wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>;
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cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>;
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};
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aaci@800000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x00800000 0x1000>;
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interrupts-extended = <&impd1_vic 9>;
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clocks = <&sysclk>;
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clock-names = "apb_pclk";
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};
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display@1000000 {
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compatible = "arm,pl110", "arm,primecell";
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reg = <0x01000000 0x1000>;
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interrupts-extended = <&impd1_vic 11>;
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clocks = <&vco1>, <&sysclk>;
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clock-names = "clcdclk", "apb_pclk";
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/* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
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max-memory-bandwidth = <40000000>;
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memory-region = <&impd1_ram>;
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dma-ranges;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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clcd_pads_vga_dac: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vga_bridge_in>;
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arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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};
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};
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};
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impd1_vic: interrupt-controller@3000000 {
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compatible = "arm,pl192-vic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x03000000 0x1000>;
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/* Valid interrupts, 0-9 and 11 */
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valid-mask = <0x00000bff>;
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/* LM site 0 has IRQ 9 on the PIC */
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interrupts-extended = <&pic 9>;
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};
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};
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