Shanker Donthineni 30ae9610d2 irqchip/gic-v3-its: Add missing changes to support 52bit physical address ... The current ITS driver works fine as long as normal memory and GICR regions are located within the lower 48bit (>=0 && <2^48) physical address space. Some of the registers GICR_PEND/PROP, GICR_VPEND/VPROP and GITS_CBASER are handled properly but not all when configuring the hardware with 52bit physical address. This patch does the following changes to support 52bit PA. -Handle 52bit PA in GITS_BASERn. -Fix ITT_addr width to 52bits, bits[51:8]. -Fix RDbase width to 52bits, bits[51:16]. -Fix VPT_addr width to 52bits, bits[51:16]. Definition of the GITS_BASERn register when ITS PageSize is 64KB: -Bits[47:16] of the register provide bits[47:16] of the table PA. -Bits[15:12] of the register provide bits[51:48] of the table PA. -Bits[15:00] of the base physical address are 0. Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>		2017-10-13 16:30:58 +01:00
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arm-gic-common.h	irqchip/gic-v3: Advertise GICv4 support to KVM	2017-08-31 15:31:42 +01:00
arm-gic-v3.h	irqchip/gic-v3-its: Add missing changes to support 52bit physical address	2017-10-13 16:30:58 +01:00
arm-gic-v4.h	irqchip/gic-v4: Enable low-level GICv4 operations	2017-08-31 15:31:42 +01:00
arm-gic.h	KVM: arm/arm64: Fix isues with GICv2 on GICv3 migration	2017-05-24 09:44:07 +02:00
arm-vic.h
chained_irq.h
ingenic.h	MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip	2015-06-21 21:53:10 +02:00
irq-omap-intc.h	irqchip: omap-intc: Remove unused legacy interface for omap2	2015-01-26 11:38:23 +01:00
irq-partition-percpu.h	irqchip: Add per-cpu interrupt partitioning library	2016-05-02 13:42:51 +02:00
irq-sa11x0.h	ARM: 8367/1: sa1100: prepare for moving irq driver to drivers/irqchip	2015-05-28 14:40:03 +01:00
metag-ext.h
metag.h
mmp.h
mxs.h
versatile-fpga.h
xtensa-mx.h
xtensa-pic.h