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f83f86e506
Handle also I3C address header error response status as the end of DAA process in hci_cmd_v1_daa(). According to MIPI I3C HCI Specification v1.1 the NACK error during DAA process comes when the device does not accept the dynamic address. Currently code uses it for successful exit from the process and fails with any other error response. I'm unsure is this MIPI I3C HCI version specific difference or specification misunderstanding but on an early MIPI I3C HCI version compatible controller responds always with I3C address header error and not with NACK error when there is no device on the bus or no more devices participating to DAA process. Handle now both response statuses as the end of DAA. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Link: https://lore.kernel.org/r/20231109133708.653950-4-jarkko.nikula@linux.intel.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
381 lines
10 KiB
C
381 lines
10 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2020, MIPI Alliance, Inc.
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*
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* Author: Nicolas Pitre <npitre@baylibre.com>
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*
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* I3C HCI v1.0/v1.1 Command Descriptor Handling
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*/
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#include <linux/bitfield.h>
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#include <linux/i3c/master.h>
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#include "hci.h"
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#include "cmd.h"
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#include "dat.h"
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#include "dct.h"
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/*
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* Address Assignment Command
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*/
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#define CMD_0_ATTR_A FIELD_PREP(CMD_0_ATTR, 0x2)
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#define CMD_A0_TOC W0_BIT_(31)
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#define CMD_A0_ROC W0_BIT_(30)
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#define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v)
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#define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
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#define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
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#define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
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/*
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* Immediate Data Transfer Command
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*/
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#define CMD_0_ATTR_I FIELD_PREP(CMD_0_ATTR, 0x1)
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#define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v)
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#define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v)
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#define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v)
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#define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v)
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#define CMD_I1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v)
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#define CMD_I0_TOC W0_BIT_(31)
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#define CMD_I0_ROC W0_BIT_(30)
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#define CMD_I0_RNW W0_BIT_(29)
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#define CMD_I0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v)
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#define CMD_I0_DTT(v) FIELD_PREP(W0_MASK(25, 23), v)
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#define CMD_I0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
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#define CMD_I0_CP W0_BIT_(15)
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#define CMD_I0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
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#define CMD_I0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
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/*
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* Regular Data Transfer Command
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*/
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#define CMD_0_ATTR_R FIELD_PREP(CMD_0_ATTR, 0x0)
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#define CMD_R1_DATA_LENGTH(v) FIELD_PREP(W1_MASK(63, 48), v)
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#define CMD_R1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v)
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#define CMD_R0_TOC W0_BIT_(31)
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#define CMD_R0_ROC W0_BIT_(30)
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#define CMD_R0_RNW W0_BIT_(29)
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#define CMD_R0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v)
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#define CMD_R0_DBP W0_BIT_(25)
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#define CMD_R0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
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#define CMD_R0_CP W0_BIT_(15)
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#define CMD_R0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
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#define CMD_R0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
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/*
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* Combo Transfer (Write + Write/Read) Command
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*/
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#define CMD_0_ATTR_C FIELD_PREP(CMD_0_ATTR, 0x3)
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#define CMD_C1_DATA_LENGTH(v) FIELD_PREP(W1_MASK(63, 48), v)
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#define CMD_C1_OFFSET(v) FIELD_PREP(W1_MASK(47, 32), v)
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#define CMD_C0_TOC W0_BIT_(31)
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#define CMD_C0_ROC W0_BIT_(30)
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#define CMD_C0_RNW W0_BIT_(29)
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#define CMD_C0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v)
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#define CMD_C0_16_BIT_SUBOFFSET W0_BIT_(25)
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#define CMD_C0_FIRST_PHASE_MODE W0_BIT_(24)
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#define CMD_C0_DATA_LENGTH_POSITION(v) FIELD_PREP(W0_MASK(23, 22), v)
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#define CMD_C0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
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#define CMD_C0_CP W0_BIT_(15)
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#define CMD_C0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
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#define CMD_C0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
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/*
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* Internal Control Command
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*/
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#define CMD_0_ATTR_M FIELD_PREP(CMD_0_ATTR, 0x7)
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#define CMD_M1_VENDOR_SPECIFIC W1_MASK(63, 32)
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#define CMD_M0_MIPI_RESERVED W0_MASK(31, 12)
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#define CMD_M0_MIPI_CMD W0_MASK(11, 8)
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#define CMD_M0_VENDOR_INFO_PRESENT W0_BIT_( 7)
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#define CMD_M0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
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/* Data Transfer Speed and Mode */
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enum hci_cmd_mode {
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MODE_I3C_SDR0 = 0x0,
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MODE_I3C_SDR1 = 0x1,
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MODE_I3C_SDR2 = 0x2,
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MODE_I3C_SDR3 = 0x3,
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MODE_I3C_SDR4 = 0x4,
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MODE_I3C_HDR_TSx = 0x5,
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MODE_I3C_HDR_DDR = 0x6,
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MODE_I3C_HDR_BT = 0x7,
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MODE_I3C_Fm_FmP = 0x8,
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MODE_I2C_Fm = 0x0,
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MODE_I2C_FmP = 0x1,
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MODE_I2C_UD1 = 0x2,
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MODE_I2C_UD2 = 0x3,
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MODE_I2C_UD3 = 0x4,
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};
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static enum hci_cmd_mode get_i3c_mode(struct i3c_hci *hci)
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{
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struct i3c_bus *bus = i3c_master_get_bus(&hci->master);
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if (bus->scl_rate.i3c >= 12500000)
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return MODE_I3C_SDR0;
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if (bus->scl_rate.i3c > 8000000)
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return MODE_I3C_SDR1;
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if (bus->scl_rate.i3c > 6000000)
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return MODE_I3C_SDR2;
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if (bus->scl_rate.i3c > 4000000)
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return MODE_I3C_SDR3;
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if (bus->scl_rate.i3c > 2000000)
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return MODE_I3C_SDR4;
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return MODE_I3C_Fm_FmP;
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}
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static enum hci_cmd_mode get_i2c_mode(struct i3c_hci *hci)
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{
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struct i3c_bus *bus = i3c_master_get_bus(&hci->master);
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if (bus->scl_rate.i2c >= 1000000)
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return MODE_I2C_FmP;
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return MODE_I2C_Fm;
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}
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static void fill_data_bytes(struct hci_xfer *xfer, u8 *data,
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unsigned int data_len)
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{
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xfer->cmd_desc[1] = 0;
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switch (data_len) {
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case 4:
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xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_4(data[3]);
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fallthrough;
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case 3:
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xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_3(data[2]);
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fallthrough;
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case 2:
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xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_2(data[1]);
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fallthrough;
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case 1:
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xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_1(data[0]);
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fallthrough;
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case 0:
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break;
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}
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/* we consumed all the data with the cmd descriptor */
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xfer->data = NULL;
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}
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static int hci_cmd_v1_prep_ccc(struct i3c_hci *hci,
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struct hci_xfer *xfer,
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u8 ccc_addr, u8 ccc_cmd, bool raw)
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{
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unsigned int dat_idx = 0;
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enum hci_cmd_mode mode = get_i3c_mode(hci);
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u8 *data = xfer->data;
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unsigned int data_len = xfer->data_len;
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bool rnw = xfer->rnw;
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int ret;
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/* this should never happen */
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if (WARN_ON(raw))
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return -EINVAL;
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if (ccc_addr != I3C_BROADCAST_ADDR) {
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ret = mipi_i3c_hci_dat_v1.get_index(hci, ccc_addr);
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if (ret < 0)
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return ret;
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dat_idx = ret;
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}
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xfer->cmd_tid = hci_get_tid();
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if (!rnw && data_len <= 4) {
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/* we use an Immediate Data Transfer Command */
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xfer->cmd_desc[0] =
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CMD_0_ATTR_I |
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CMD_I0_TID(xfer->cmd_tid) |
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CMD_I0_CMD(ccc_cmd) | CMD_I0_CP |
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CMD_I0_DEV_INDEX(dat_idx) |
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CMD_I0_DTT(data_len) |
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CMD_I0_MODE(mode);
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fill_data_bytes(xfer, data, data_len);
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} else {
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/* we use a Regular Data Transfer Command */
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xfer->cmd_desc[0] =
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CMD_0_ATTR_R |
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CMD_R0_TID(xfer->cmd_tid) |
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CMD_R0_CMD(ccc_cmd) | CMD_R0_CP |
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CMD_R0_DEV_INDEX(dat_idx) |
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CMD_R0_MODE(mode) |
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(rnw ? CMD_R0_RNW : 0);
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xfer->cmd_desc[1] =
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CMD_R1_DATA_LENGTH(data_len);
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}
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return 0;
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}
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static void hci_cmd_v1_prep_i3c_xfer(struct i3c_hci *hci,
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struct i3c_dev_desc *dev,
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struct hci_xfer *xfer)
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{
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struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev);
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unsigned int dat_idx = dev_data->dat_idx;
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enum hci_cmd_mode mode = get_i3c_mode(hci);
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u8 *data = xfer->data;
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unsigned int data_len = xfer->data_len;
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bool rnw = xfer->rnw;
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xfer->cmd_tid = hci_get_tid();
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if (!rnw && data_len <= 4) {
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/* we use an Immediate Data Transfer Command */
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xfer->cmd_desc[0] =
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CMD_0_ATTR_I |
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CMD_I0_TID(xfer->cmd_tid) |
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CMD_I0_DEV_INDEX(dat_idx) |
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CMD_I0_DTT(data_len) |
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CMD_I0_MODE(mode);
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fill_data_bytes(xfer, data, data_len);
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} else {
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/* we use a Regular Data Transfer Command */
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xfer->cmd_desc[0] =
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CMD_0_ATTR_R |
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CMD_R0_TID(xfer->cmd_tid) |
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CMD_R0_DEV_INDEX(dat_idx) |
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CMD_R0_MODE(mode) |
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(rnw ? CMD_R0_RNW : 0);
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xfer->cmd_desc[1] =
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CMD_R1_DATA_LENGTH(data_len);
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}
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}
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static void hci_cmd_v1_prep_i2c_xfer(struct i3c_hci *hci,
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struct i2c_dev_desc *dev,
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struct hci_xfer *xfer)
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{
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struct i3c_hci_dev_data *dev_data = i2c_dev_get_master_data(dev);
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unsigned int dat_idx = dev_data->dat_idx;
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enum hci_cmd_mode mode = get_i2c_mode(hci);
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u8 *data = xfer->data;
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unsigned int data_len = xfer->data_len;
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bool rnw = xfer->rnw;
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xfer->cmd_tid = hci_get_tid();
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if (!rnw && data_len <= 4) {
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/* we use an Immediate Data Transfer Command */
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xfer->cmd_desc[0] =
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CMD_0_ATTR_I |
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CMD_I0_TID(xfer->cmd_tid) |
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CMD_I0_DEV_INDEX(dat_idx) |
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CMD_I0_DTT(data_len) |
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CMD_I0_MODE(mode);
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fill_data_bytes(xfer, data, data_len);
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} else {
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/* we use a Regular Data Transfer Command */
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xfer->cmd_desc[0] =
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CMD_0_ATTR_R |
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CMD_R0_TID(xfer->cmd_tid) |
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CMD_R0_DEV_INDEX(dat_idx) |
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CMD_R0_MODE(mode) |
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(rnw ? CMD_R0_RNW : 0);
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xfer->cmd_desc[1] =
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CMD_R1_DATA_LENGTH(data_len);
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}
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}
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static int hci_cmd_v1_daa(struct i3c_hci *hci)
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{
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struct hci_xfer *xfer;
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int ret, dat_idx = -1;
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u8 next_addr = 0;
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u64 pid;
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unsigned int dcr, bcr;
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DECLARE_COMPLETION_ONSTACK(done);
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xfer = hci_alloc_xfer(1);
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if (!xfer)
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return -ENOMEM;
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/*
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* Simple for now: we allocate a temporary DAT entry, do a single
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* DAA, register the device which will allocate its own DAT entry
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* via the core callback, then free the temporary DAT entry.
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* Loop until there is no more devices to assign an address to.
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* Yes, there is room for improvements.
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*/
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for (;;) {
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ret = mipi_i3c_hci_dat_v1.alloc_entry(hci);
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if (ret < 0)
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break;
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dat_idx = ret;
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ret = i3c_master_get_free_addr(&hci->master, next_addr);
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if (ret < 0)
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break;
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next_addr = ret;
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DBG("next_addr = 0x%02x, DAA using DAT %d", next_addr, dat_idx);
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mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, dat_idx, next_addr);
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mipi_i3c_hci_dct_index_reset(hci);
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xfer->cmd_tid = hci_get_tid();
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xfer->cmd_desc[0] =
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CMD_0_ATTR_A |
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CMD_A0_TID(xfer->cmd_tid) |
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CMD_A0_CMD(I3C_CCC_ENTDAA) |
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CMD_A0_DEV_INDEX(dat_idx) |
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CMD_A0_DEV_COUNT(1) |
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CMD_A0_ROC | CMD_A0_TOC;
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xfer->cmd_desc[1] = 0;
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xfer->completion = &done;
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hci->io->queue_xfer(hci, xfer, 1);
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if (!wait_for_completion_timeout(&done, HZ) &&
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hci->io->dequeue_xfer(hci, xfer, 1)) {
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ret = -ETIME;
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break;
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}
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if ((RESP_STATUS(xfer->response) == RESP_ERR_ADDR_HEADER ||
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RESP_STATUS(xfer->response) == RESP_ERR_NACK) &&
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RESP_DATA_LENGTH(xfer->response) == 1) {
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ret = 0; /* no more devices to be assigned */
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break;
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}
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if (RESP_STATUS(xfer->response) != RESP_SUCCESS) {
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ret = -EIO;
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break;
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}
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i3c_hci_dct_get_val(hci, 0, &pid, &dcr, &bcr);
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DBG("assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x",
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next_addr, pid, dcr, bcr);
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mipi_i3c_hci_dat_v1.free_entry(hci, dat_idx);
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dat_idx = -1;
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/*
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* TODO: Extend the subsystem layer to allow for registering
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* new device and provide BCR/DCR/PID at the same time.
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*/
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ret = i3c_master_add_i3c_dev_locked(&hci->master, next_addr);
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if (ret)
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break;
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}
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if (dat_idx >= 0)
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mipi_i3c_hci_dat_v1.free_entry(hci, dat_idx);
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hci_free_xfer(xfer, 1);
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return ret;
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}
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const struct hci_cmd_ops mipi_i3c_hci_cmd_v1 = {
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.prep_ccc = hci_cmd_v1_prep_ccc,
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.prep_i3c_xfer = hci_cmd_v1_prep_i3c_xfer,
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.prep_i2c_xfer = hci_cmd_v1_prep_i2c_xfer,
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.perform_daa = hci_cmd_v1_daa,
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};
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