mirror_ubuntu-kernels/drivers/gpu/drm/xe/xe_pcode.h
Badal Nilawar 92d44a422d drm/xe/hwmon: Expose card reactive critical power
Expose the card reactive critical (I1) power. I1 is exposed as
power1_crit in microwatts (typically for client products) or as
curr1_crit in milliamperes (typically for server).

v2: Move PCODE_MBOX macro to pcode file (Riana)
v3: s/IS_DG2/(gt_to_xe(gt)->info.platform == XE_DG2)
v4: Fix review comments (Andi)

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://lore.kernel.org/r/20230925081842.3566834-3-badal.nilawar@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2023-12-21 11:42:08 -05:00

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853 B
C

/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
#ifndef _XE_PCODE_H_
#define _XE_PCODE_H_
#include <linux/types.h>
struct xe_gt;
int xe_pcode_probe(struct xe_gt *gt);
int xe_pcode_init(struct xe_gt *gt);
int xe_pcode_init_min_freq_table(struct xe_gt *gt, u32 min_gt_freq,
u32 max_gt_freq);
int xe_pcode_read(struct xe_gt *gt, u32 mbox, u32 *val, u32 *val1);
int xe_pcode_write_timeout(struct xe_gt *gt, u32 mbox, u32 val,
int timeout_ms);
#define xe_pcode_write(gt, mbox, val) \
xe_pcode_write_timeout(gt, mbox, val, 1)
int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_ms);
#define PCODE_MBOX(mbcmd, param1, param2)\
(FIELD_PREP(PCODE_MB_COMMAND, mbcmd)\
| FIELD_PREP(PCODE_MB_PARAM1, param1)\
| FIELD_PREP(PCODE_MB_PARAM2, param2))
#endif