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1b79fc4f2b
Intel Moorestown and Medfield are quite old Intel Atom based
32-bit platforms, which were in limited use in some Android phones,
tablets and consumer electronics more than eight years ago.
There are no bugs or problems ever reported outside from Intel
for breaking any of that platforms for years. It seems no real
users exists who run more or less fresh kernel on it. Commit
05f4434bc1 ("ASoC: Intel: remove mfld_machine") is also in align
with this theory.
Due to above and to reduce a burden of supporting outdated drivers,
remove the support for outdated platforms completely.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
140 lines
3.5 KiB
C
140 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* intel-mid.c: Intel MID platform setup code
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*
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* (C) Copyright 2008, 2012 Intel Corporation
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* Author: Jacob Pan (jacob.jun.pan@intel.com)
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* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
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*/
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#define pr_fmt(fmt) "intel_mid: " fmt
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/regulator/machine.h>
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#include <linux/scatterlist.h>
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#include <linux/sfi.h>
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#include <linux/irq.h>
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#include <linux/export.h>
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#include <linux/notifier.h>
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#include <asm/setup.h>
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#include <asm/mpspec_def.h>
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#include <asm/hw_irq.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/intel-mid.h>
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#include <asm/io.h>
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#include <asm/i8259.h>
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#include <asm/intel_scu_ipc.h>
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#include <asm/reboot.h>
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enum intel_mid_cpu_type __intel_mid_cpu_chip;
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EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
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static void intel_mid_power_off(void)
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{
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/* Shut down South Complex via PWRMU */
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intel_mid_pwr_power_off();
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/* Only for Tangier, the rest will ignore this command */
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intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1);
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};
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static void intel_mid_reboot(void)
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{
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intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
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}
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static void __init intel_mid_time_init(void)
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{
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/* Lapic only, no apbt */
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x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
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x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
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}
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static void intel_mid_arch_setup(void)
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{
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if (boot_cpu_data.x86 != 6) {
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pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
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boot_cpu_data.x86, boot_cpu_data.x86_model);
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__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
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goto out;
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}
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switch (boot_cpu_data.x86_model) {
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case 0x35:
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__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
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break;
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case 0x3C:
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case 0x4A:
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__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER;
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x86_platform.legacy.rtc = 1;
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break;
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case 0x27:
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default:
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__intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
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break;
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}
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out:
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/*
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* Intel MID platforms are using explicitly defined regulators.
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*
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* Let the regulator core know that we do not have any additional
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* regulators left. This lets it substitute unprovided regulators with
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* dummy ones:
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*/
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regulator_has_full_constraints();
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}
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/*
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* Moorestown does not have external NMI source nor port 0x61 to report
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* NMI status. The possible NMI sources are from pmu as a result of NMI
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* watchdog or lock debug. Reading io port 0x61 results in 0xff which
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* misled NMI handler.
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*/
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static unsigned char intel_mid_get_nmi_reason(void)
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{
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return 0;
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}
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/*
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* Moorestown specific x86_init function overrides and early setup
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* calls.
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*/
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void __init x86_intel_mid_early_setup(void)
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{
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x86_init.resources.probe_roms = x86_init_noop;
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x86_init.resources.reserve_resources = x86_init_noop;
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x86_init.timers.timer_init = intel_mid_time_init;
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x86_init.timers.setup_percpu_clockev = x86_init_noop;
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x86_init.irqs.pre_vector_init = x86_init_noop;
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x86_init.oem.arch_setup = intel_mid_arch_setup;
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x86_platform.get_nmi_reason = intel_mid_get_nmi_reason;
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x86_init.pci.arch_init = intel_mid_pci_init;
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x86_init.pci.fixup_irqs = x86_init_noop;
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legacy_pic = &null_legacy_pic;
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/*
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* Do nothing for now as everything needed done in
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* x86_intel_mid_early_setup() below.
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*/
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x86_init.acpi.reduced_hw_early_init = x86_init_noop;
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pm_power_off = intel_mid_power_off;
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machine_ops.emergency_restart = intel_mid_reboot;
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/* Avoid searching for BIOS MP tables */
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x86_init.mpparse.find_smp_config = x86_init_noop;
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x86_init.mpparse.get_smp_config = x86_init_uint_noop;
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set_bit(MP_BUS_ISA, mp_bus_not_pci);
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}
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