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Nothing populates them yet. Signed-off-by: Edward Cree <ecree.xilinx@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
331 lines
10 KiB
C
331 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/****************************************************************************
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* Driver for Solarflare network controllers and boards
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include "tc_counters.h"
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#include "mae_counter_format.h"
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#include "mae.h"
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#include "rx_common.h"
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/* Counter-management hashtables */
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static const struct rhashtable_params efx_tc_counter_id_ht_params = {
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.key_len = offsetof(struct efx_tc_counter_index, linkage),
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.key_offset = 0,
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.head_offset = offsetof(struct efx_tc_counter_index, linkage),
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};
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static const struct rhashtable_params efx_tc_counter_ht_params = {
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.key_len = offsetof(struct efx_tc_counter, linkage),
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.key_offset = 0,
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.head_offset = offsetof(struct efx_tc_counter, linkage),
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};
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static void efx_tc_counter_free(void *ptr, void *__unused)
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{
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struct efx_tc_counter *cnt = ptr;
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kfree(cnt);
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}
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static void efx_tc_counter_id_free(void *ptr, void *__unused)
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{
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struct efx_tc_counter_index *ctr = ptr;
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WARN_ON(refcount_read(&ctr->ref));
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kfree(ctr);
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}
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int efx_tc_init_counters(struct efx_nic *efx)
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{
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int rc;
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rc = rhashtable_init(&efx->tc->counter_id_ht, &efx_tc_counter_id_ht_params);
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if (rc < 0)
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goto fail_counter_id_ht;
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rc = rhashtable_init(&efx->tc->counter_ht, &efx_tc_counter_ht_params);
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if (rc < 0)
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goto fail_counter_ht;
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return 0;
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fail_counter_ht:
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rhashtable_destroy(&efx->tc->counter_id_ht);
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fail_counter_id_ht:
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return rc;
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}
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/* Only call this in init failure teardown.
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* Normal exit should fini instead as there may be entries in the table.
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*/
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void efx_tc_destroy_counters(struct efx_nic *efx)
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{
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rhashtable_destroy(&efx->tc->counter_ht);
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rhashtable_destroy(&efx->tc->counter_id_ht);
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}
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void efx_tc_fini_counters(struct efx_nic *efx)
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{
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rhashtable_free_and_destroy(&efx->tc->counter_id_ht, efx_tc_counter_id_free, NULL);
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rhashtable_free_and_destroy(&efx->tc->counter_ht, efx_tc_counter_free, NULL);
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}
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/* TC Channel. Counter updates are delivered on this channel's RXQ. */
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static void efx_tc_handle_no_channel(struct efx_nic *efx)
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{
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netif_warn(efx, drv, efx->net_dev,
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"MAE counters require MSI-X and 1 additional interrupt vector.\n");
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}
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static int efx_tc_probe_channel(struct efx_channel *channel)
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{
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struct efx_rx_queue *rx_queue = &channel->rx_queue;
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channel->irq_moderation_us = 0;
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rx_queue->core_index = 0;
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INIT_WORK(&rx_queue->grant_work, efx_mae_counters_grant_credits);
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return 0;
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}
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static int efx_tc_start_channel(struct efx_channel *channel)
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{
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struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
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struct efx_nic *efx = channel->efx;
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return efx_mae_start_counters(efx, rx_queue);
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}
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static void efx_tc_stop_channel(struct efx_channel *channel)
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{
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struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
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struct efx_nic *efx = channel->efx;
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int rc;
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rc = efx_mae_stop_counters(efx, rx_queue);
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if (rc)
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netif_warn(efx, drv, efx->net_dev,
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"Failed to stop MAE counters streaming, rc=%d.\n",
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rc);
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rx_queue->grant_credits = false;
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flush_work(&rx_queue->grant_work);
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}
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static void efx_tc_remove_channel(struct efx_channel *channel)
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{
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}
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static void efx_tc_get_channel_name(struct efx_channel *channel,
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char *buf, size_t len)
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{
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snprintf(buf, len, "%s-mae", channel->efx->name);
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}
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static void efx_tc_counter_update(struct efx_nic *efx,
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enum efx_tc_counter_type counter_type,
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u32 counter_idx, u64 packets, u64 bytes,
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u32 mark)
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{
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/* Software counter objects do not exist yet, for now we ignore this */
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}
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static void efx_tc_rx_version_1(struct efx_nic *efx, const u8 *data, u32 mark)
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{
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u16 n_counters, i;
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/* Header format:
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* + | 0 | 1 | 2 | 3 |
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* 0 |version | reserved |
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* 4 | seq_index | n_counters |
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*/
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n_counters = le16_to_cpu(*(const __le16 *)(data + 6));
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/* Counter update entry format:
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* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | a | b | c | d | e | f |
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* | counter_idx | packet_count | byte_count |
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*/
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for (i = 0; i < n_counters; i++) {
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const void *entry = data + 8 + 16 * i;
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u64 packet_count, byte_count;
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u32 counter_idx;
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counter_idx = le32_to_cpu(*(const __le32 *)entry);
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packet_count = le32_to_cpu(*(const __le32 *)(entry + 4)) |
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((u64)le16_to_cpu(*(const __le16 *)(entry + 8)) << 32);
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byte_count = le16_to_cpu(*(const __le16 *)(entry + 10)) |
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((u64)le32_to_cpu(*(const __le32 *)(entry + 12)) << 16);
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efx_tc_counter_update(efx, EFX_TC_COUNTER_TYPE_AR, counter_idx,
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packet_count, byte_count, mark);
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}
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}
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#define TCV2_HDR_PTR(pkt, field) \
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((void)BUILD_BUG_ON_ZERO(ERF_SC_PACKETISER_HEADER_##field##_LBN & 7), \
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(pkt) + ERF_SC_PACKETISER_HEADER_##field##_LBN / 8)
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#define TCV2_HDR_BYTE(pkt, field) \
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((void)BUILD_BUG_ON_ZERO(ERF_SC_PACKETISER_HEADER_##field##_WIDTH != 8),\
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*TCV2_HDR_PTR(pkt, field))
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#define TCV2_HDR_WORD(pkt, field) \
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((void)BUILD_BUG_ON_ZERO(ERF_SC_PACKETISER_HEADER_##field##_WIDTH != 16),\
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(void)BUILD_BUG_ON_ZERO(ERF_SC_PACKETISER_HEADER_##field##_LBN & 15), \
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*(__force const __le16 *)TCV2_HDR_PTR(pkt, field))
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#define TCV2_PKT_PTR(pkt, poff, i, field) \
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((void)BUILD_BUG_ON_ZERO(ERF_SC_PACKETISER_PAYLOAD_##field##_LBN & 7), \
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(pkt) + ERF_SC_PACKETISER_PAYLOAD_##field##_LBN/8 + poff + \
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i * ER_RX_SL_PACKETISER_PAYLOAD_WORD_SIZE)
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/* Read a little-endian 48-bit field with 16-bit alignment */
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static u64 efx_tc_read48(const __le16 *field)
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{
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u64 out = 0;
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int i;
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for (i = 0; i < 3; i++)
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out |= (u64)le16_to_cpu(field[i]) << (i * 16);
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return out;
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}
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static enum efx_tc_counter_type efx_tc_rx_version_2(struct efx_nic *efx,
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const u8 *data, u32 mark)
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{
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u8 payload_offset, header_offset, ident;
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enum efx_tc_counter_type type;
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u16 n_counters, i;
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ident = TCV2_HDR_BYTE(data, IDENTIFIER);
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switch (ident) {
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case ERF_SC_PACKETISER_HEADER_IDENTIFIER_AR:
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type = EFX_TC_COUNTER_TYPE_AR;
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break;
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case ERF_SC_PACKETISER_HEADER_IDENTIFIER_CT:
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type = EFX_TC_COUNTER_TYPE_CT;
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break;
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case ERF_SC_PACKETISER_HEADER_IDENTIFIER_OR:
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type = EFX_TC_COUNTER_TYPE_OR;
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break;
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default:
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if (net_ratelimit())
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netif_err(efx, drv, efx->net_dev,
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"ignored v2 MAE counter packet (bad identifier %u"
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"), counters may be inaccurate\n", ident);
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return EFX_TC_COUNTER_TYPE_MAX;
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}
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header_offset = TCV2_HDR_BYTE(data, HEADER_OFFSET);
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/* mae_counter_format.h implies that this offset is fixed, since it
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* carries on with SOP-based LBNs for the fields in this header
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*/
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if (header_offset != ERF_SC_PACKETISER_HEADER_HEADER_OFFSET_DEFAULT) {
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if (net_ratelimit())
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netif_err(efx, drv, efx->net_dev,
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"choked on v2 MAE counter packet (bad header_offset %u"
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"), counters may be inaccurate\n", header_offset);
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return EFX_TC_COUNTER_TYPE_MAX;
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}
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payload_offset = TCV2_HDR_BYTE(data, PAYLOAD_OFFSET);
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n_counters = le16_to_cpu(TCV2_HDR_WORD(data, COUNT));
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for (i = 0; i < n_counters; i++) {
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const void *counter_idx_p, *packet_count_p, *byte_count_p;
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u64 packet_count, byte_count;
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u32 counter_idx;
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/* 24-bit field with 32-bit alignment */
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counter_idx_p = TCV2_PKT_PTR(data, payload_offset, i, COUNTER_INDEX);
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BUILD_BUG_ON(ERF_SC_PACKETISER_PAYLOAD_COUNTER_INDEX_WIDTH != 24);
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BUILD_BUG_ON(ERF_SC_PACKETISER_PAYLOAD_COUNTER_INDEX_LBN & 31);
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counter_idx = le32_to_cpu(*(const __le32 *)counter_idx_p) & 0xffffff;
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/* 48-bit field with 16-bit alignment */
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packet_count_p = TCV2_PKT_PTR(data, payload_offset, i, PACKET_COUNT);
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BUILD_BUG_ON(ERF_SC_PACKETISER_PAYLOAD_PACKET_COUNT_WIDTH != 48);
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BUILD_BUG_ON(ERF_SC_PACKETISER_PAYLOAD_PACKET_COUNT_LBN & 15);
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packet_count = efx_tc_read48((const __le16 *)packet_count_p);
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/* 48-bit field with 16-bit alignment */
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byte_count_p = TCV2_PKT_PTR(data, payload_offset, i, BYTE_COUNT);
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BUILD_BUG_ON(ERF_SC_PACKETISER_PAYLOAD_BYTE_COUNT_WIDTH != 48);
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BUILD_BUG_ON(ERF_SC_PACKETISER_PAYLOAD_BYTE_COUNT_LBN & 15);
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byte_count = efx_tc_read48((const __le16 *)byte_count_p);
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if (type == EFX_TC_COUNTER_TYPE_CT) {
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/* CT counters are 1-bit saturating counters to update
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* the lastuse time in CT stats. A received CT counter
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* should have packet counter to 0 and only LSB bit on
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* in byte counter.
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*/
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if (packet_count || byte_count != 1)
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netdev_warn_once(efx->net_dev,
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"CT counter with inconsistent state (%llu, %llu)\n",
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packet_count, byte_count);
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/* Do not increment the driver's byte counter */
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byte_count = 0;
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}
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efx_tc_counter_update(efx, type, counter_idx, packet_count,
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byte_count, mark);
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}
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return type;
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}
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/* We always swallow the packet, whether successful or not, since it's not
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* a network packet and shouldn't ever be forwarded to the stack.
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* @mark is the generation count for counter allocations.
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*/
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static bool efx_tc_rx(struct efx_rx_queue *rx_queue, u32 mark)
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{
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struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
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struct efx_rx_buffer *rx_buf = efx_rx_buffer(rx_queue,
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channel->rx_pkt_index);
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const u8 *data = efx_rx_buf_va(rx_buf);
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struct efx_nic *efx = rx_queue->efx;
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enum efx_tc_counter_type type;
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u8 version;
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/* version is always first byte of packet */
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version = *data;
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switch (version) {
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case 1:
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type = EFX_TC_COUNTER_TYPE_AR;
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efx_tc_rx_version_1(efx, data, mark);
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break;
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case ERF_SC_PACKETISER_HEADER_VERSION_VALUE: // 2
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type = efx_tc_rx_version_2(efx, data, mark);
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break;
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default:
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if (net_ratelimit())
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netif_err(efx, drv, efx->net_dev,
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"choked on MAE counter packet (bad version %u"
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"); counters may be inaccurate\n",
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version);
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goto out;
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}
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/* Update seen_gen unconditionally, to avoid a missed wakeup if
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* we race with efx_mae_stop_counters().
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*/
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efx->tc->seen_gen[type] = mark;
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if (efx->tc->flush_counters &&
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(s32)(efx->tc->flush_gen[type] - mark) <= 0)
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wake_up(&efx->tc->flush_wq);
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out:
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efx_free_rx_buffers(rx_queue, rx_buf, 1);
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channel->rx_pkt_n_frags = 0;
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return true;
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}
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const struct efx_channel_type efx_tc_channel_type = {
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.handle_no_channel = efx_tc_handle_no_channel,
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.pre_probe = efx_tc_probe_channel,
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.start = efx_tc_start_channel,
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.stop = efx_tc_stop_channel,
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.post_remove = efx_tc_remove_channel,
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.get_name = efx_tc_get_channel_name,
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.receive_raw = efx_tc_rx,
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.keep_eventq = true,
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};
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