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According to the errata sheets for ksz9477 and ksz9567, writes to the PHY registers 0x10-0x1f (i.e. those located at addresses 0xN120 to 0xN13f) must be done as a 32 bit write to the 4-byte aligned address containing the register, hence requires a RMW in order not to change the adjacent PHY register. Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Reviewed-by: Simon Horman <simon.horman@corigine.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20230620113855.733526-4-linux@rasmusvillemoes.dk Signed-off-by: Jakub Kicinski <kuba@kernel.org> |
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| .. | ||
| Kconfig | ||
| ksz8.h | ||
| ksz8795_reg.h | ||
| ksz8795.c | ||
| ksz8863_smi.c | ||
| ksz9477_i2c.c | ||
| ksz9477_reg.h | ||
| ksz9477.c | ||
| ksz9477.h | ||
| ksz_common.c | ||
| ksz_common.h | ||
| ksz_ptp_reg.h | ||
| ksz_ptp.c | ||
| ksz_ptp.h | ||
| ksz_spi.c | ||
| lan937x_main.c | ||
| lan937x_reg.h | ||
| lan937x.h | ||
| Makefile | ||