Conor Dooley 17e4732d1d dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible ... The l2 cache on PolarFire SoC is cross between that of the fu540 and the fu740. It has the extra interrupt from the fu740 but the lower number of cache-sets. Add a specific compatible to avoid the likes of: mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long Fixes: 34fc9cc3ae ("riscv: dts: microchip: correct L2 cache interrupts") Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2022-08-31 16:57:44 +01:00
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bindings	dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible	2022-08-31 16:57:44 +01:00
changesets.rst
dynamic-resolution-notes.rst
index.rst
kernel-api.rst
of_unittest.rst	of: unittest: add program to process EXPECT messages	2022-02-28 15:20:32 -06:00
overlay-notes.rst	of: overlay: rework overlay apply and remove kfree()s	2022-04-25 10:56:11 -05:00
usage-model.rst