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1631ba1259
The Zicbom ISA-extension was ratified in november 2021 and introduces instructions for dcache invalidate, clean and flush operations. Implement cache management operations for non-coherent devices based on them. Of course not all cores will support this, so implement an alternative-based mechanism that replaces empty instructions with ones done around Zicbom instructions. As discussed in previous versions, assume the platform being coherent by default so that non-coherent devices need to get marked accordingly by firmware. Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Guo Ren <guoren@kernel.org> Link: https://lore.kernel.org/r/20220706231536.2041855-4-heiko@sntech.de Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copied from arch/arm64/include/asm/hwcap.h
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2017 SiFive
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*/
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#ifndef _ASM_RISCV_HWCAP_H
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#define _ASM_RISCV_HWCAP_H
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#include <linux/bits.h>
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#include <uapi/asm/hwcap.h>
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#ifndef __ASSEMBLY__
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#include <linux/jump_label.h>
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/*
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* This yields a mask that user programs can use to figure out what
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* instruction set this cpu supports.
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*/
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#define ELF_HWCAP (elf_hwcap)
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enum {
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CAP_HWCAP = 1,
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};
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extern unsigned long elf_hwcap;
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#define RISCV_ISA_EXT_a ('a' - 'a')
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#define RISCV_ISA_EXT_c ('c' - 'a')
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#define RISCV_ISA_EXT_d ('d' - 'a')
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#define RISCV_ISA_EXT_f ('f' - 'a')
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#define RISCV_ISA_EXT_h ('h' - 'a')
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#define RISCV_ISA_EXT_i ('i' - 'a')
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#define RISCV_ISA_EXT_m ('m' - 'a')
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#define RISCV_ISA_EXT_s ('s' - 'a')
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#define RISCV_ISA_EXT_u ('u' - 'a')
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/*
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* Increse this to higher value as kernel support more ISA extensions.
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*/
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#define RISCV_ISA_EXT_MAX 64
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#define RISCV_ISA_EXT_NAME_LEN_MAX 32
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/* The base ID for multi-letter ISA extensions */
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#define RISCV_ISA_EXT_BASE 26
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/*
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* This enum represent the logical ID for each multi-letter RISC-V ISA extension.
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* The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
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* RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
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* extensions while all the multi-letter extensions should define the next
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* available logical extension id.
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*/
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enum riscv_isa_ext_id {
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RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
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RISCV_ISA_EXT_SVPBMT,
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RISCV_ISA_EXT_ZICBOM,
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RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
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};
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/*
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* This enum represents the logical ID for each RISC-V ISA extension static
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* keys. We can use static key to optimize code path if some ISA extensions
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* are available.
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*/
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enum riscv_isa_ext_key {
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RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */
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RISCV_ISA_EXT_KEY_MAX,
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};
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struct riscv_isa_ext_data {
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/* Name of the extension displayed to userspace via /proc/cpuinfo */
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char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
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/* The logical ISA extension ID */
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unsigned int isa_ext_id;
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};
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extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX];
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static __always_inline int riscv_isa_ext2key(int num)
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{
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switch (num) {
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case RISCV_ISA_EXT_f:
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return RISCV_ISA_EXT_KEY_FPU;
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case RISCV_ISA_EXT_d:
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return RISCV_ISA_EXT_KEY_FPU;
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default:
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return -EINVAL;
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}
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}
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
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#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
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bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
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#define riscv_isa_extension_available(isa_bitmap, ext) \
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__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
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#endif
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#endif /* _ASM_RISCV_HWCAP_H */
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