Aurabindo Pillai 158858bf1a drm/amd/display: rework macros for DWB register access ... [Why] A hack was used to access DWB register due to difference in the register naming convention which was not compatible with existing SR/SRI* macros. The additional macro needed were added to dwb ip specific header file (dcnxx_dwb.h) instead of soc resource file (dcnxx_resource.c). Due to this pattern, BASE macro had to be redefined in dcnxx_dwb.h, which in turn needed us to undefine them in the resource file. [How] Add a separate macro for DWB access to the resource files that need it instead of defining them in DWB ip header file. This will enable us to reuse the BASE macro defined in the resource file. Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-11-15 13:35:15 -05:00
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amdgpu_dm	drm/amd/display: Fix invalid DPIA AUX reply causing system hang	2022-11-15 11:52:40 -05:00
dc	drm/amd/display: rework macros for DWB register access	2022-11-15 13:35:15 -05:00
dmub	drm/amd/display: Waiting for 1 frame to fix the flash issue on PSR1	2022-11-09 17:24:57 -05:00
include	drm/amd/display: Refactor LTTPR mode selection	2022-09-29 09:41:46 -04:00
modules	drm/amd/display: Set correct EOTF and Gamut flag in VRR info	2022-11-09 17:41:41 -05:00
Kconfig	drm/amd/display: add DCN support for ARM64	2022-11-04 16:05:54 -04:00
Makefile
TODO