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f2791ed731
Replace the "simple-bus" simplification by the proper bus for IXP4xx memory or device expansion. Use chip-select addressing with two address cells on all the flashes mounted on the IXP4xx devices. This includes all flash chips. Change the unit-name from @50000000 to @c4000000 as the DTS validation screams. The registers for controlling the bus are at c4000000 but the actual memory windows and ranges are at 50000000. Well it is just syntax, we can live with it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
147 lines
3.0 KiB
Plaintext
147 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: ISC
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/*
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* Device Tree file for Iomega NAS 100D
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*/
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/dts-v1/;
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#include "intel-ixp42x.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Iomega NAS 100D";
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compatible = "iom,nas-100d", "intel,ixp42x";
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#address-cells = <1>;
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#size-cells = <1>;
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memory@0 {
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/* 64 MB SDRAM */
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device_type = "memory";
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reg = <0x00000000 0x4000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
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stdout-path = "uart0:115200n8";
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};
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aliases {
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serial0 = &uart0;
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};
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leds {
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compatible = "gpio-leds";
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led-wlan {
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label = "nas100d:red:wlan";
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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/* We don't have WLAN trigger in the kernel (yet) */
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linux,default-trigger = "netdev";
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};
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led-disk {
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label = "nas100d:red:disk";
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gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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linux,default-trigger = "disk-activity";
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};
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led-power {
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label = "nas100d:red:power";
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gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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button-power {
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wakeup-source;
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linux,code = <KEY_POWER>;
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label = "power";
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gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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};
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button-reset {
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wakeup-source;
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linux,code = <KEY_ESC>;
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label = "reset";
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gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
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};
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};
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i2c {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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#address-cells = <1>;
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#size-cells = <0>;
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rtc@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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};
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gpio-poweroff {
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compatible = "gpio-poweroff";
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gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
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timeout-ms = <5000>;
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};
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soc {
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bus@c4000000 {
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/* The first 16MB region at CS0 on the expansion bus */
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/*
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* 8 MB of Flash in 0x20000 byte blocks
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* mapped in at CS0.
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*/
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reg = <0 0x00000000 0x800000>;
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x7e0000 */
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fis-index-block = <0x3f>;
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};
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};
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};
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pci@c0000000 {
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status = "ok";
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/*
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* Taken from NAS 100D PCI boardfile (nas100d-pci.c)
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* We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3.
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*/
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interrupt-map =
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/* IDSEL 1 */
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<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
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/* IDSEL 2 */
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<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
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/* IDSEL 3 */
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<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
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<0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
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<0x1800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 3 is irq 7 */
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};
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ethernet@c8009000 {
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status = "ok";
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queue-rx = <&qmgr 3>;
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queue-txready = <&qmgr 20>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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};
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};
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