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SST registers are presented to OS in multi-layer structures starting with a SST header showing version information freezing current definition. For details on SST terminology refer to Documentation/admin-guide/pm/intel-speed-select.rst under the kernel documentation SST TPMI details are published in the following document: https://github.com/intel/tpmi_power_management/blob/main/SST_TPMI_public_disclosure_FINAL.docx SST MMIO structure layout follows: SST-HEADER SST-CP Header SST-CP CONTROL SST-CP STATUS SST-CP CONFIG0 SST-CP CONFIG1 ... ... SST-PP Header SST-PP OFFSET_0 SST-PP OFFSET_1 SST_PP_0_INFO SST_PP_1_INFO SST_PP_2_INFO SST_PP_3_INFO SST-PP CONTROL SST-PP STATUS Each register bank contains information to get to next lower level information. This information is parsed and stored in the struct tpmi_per_power_domain_info for each domain. This information is used to process each SST requests. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Zhang Rui <rui.zhang@intel.com> Tested-by: Pragya Tanwar <pragya.tanwar@intel.com> Link: https://lore.kernel.org/r/20230308070642.1727167-4-srinivas.pandruvada@linux.intel.com Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
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| .. | ||
| atomisp2 | ||
| ifs | ||
| int1092 | ||
| int3472 | ||
| pmc | ||
| pmt | ||
| speed_select_if | ||
| telemetry | ||
| uncore-frequency | ||
| wmi | ||
| bxtwc_tmu.c | ||
| bytcrc_pwrsrc.c | ||
| chtdc_ti_pwrbtn.c | ||
| chtwc_int33fe.c | ||
| crystal_cove_charger.c | ||
| hid.c | ||
| int0002_vgpio.c | ||
| ishtp_eclite.c | ||
| Kconfig | ||
| Makefile | ||
| mrfld_pwrbtn.c | ||
| oaktrail.c | ||
| punit_ipc.c | ||
| rst.c | ||
| sdsi.c | ||
| smartconnect.c | ||
| tpmi.c | ||
| turbo_max_3.c | ||
| vbtn.c | ||
| vsec.c | ||
| vsec.h | ||