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088ec01fce
Add a macro to allow parsing of the rd register from an instruction. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Link: https://lore.kernel.org/r/20221223221332.4127602-11-heiko@sntech.de Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
293 lines
11 KiB
C
293 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020 SiFive
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*/
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#include <linux/bits.h>
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#define RV_INSN_FUNCT3_MASK GENMASK(14, 12)
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#define RV_INSN_FUNCT3_OPOFF 12
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#define RV_INSN_OPCODE_MASK GENMASK(6, 0)
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#define RV_INSN_OPCODE_OPOFF 0
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#define RV_INSN_FUNCT12_OPOFF 20
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#define RV_ENCODE_FUNCT3(f_) (RVG_FUNCT3_##f_ << RV_INSN_FUNCT3_OPOFF)
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#define RV_ENCODE_FUNCT12(f_) (RVG_FUNCT12_##f_ << RV_INSN_FUNCT12_OPOFF)
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/* The bit field of immediate value in I-type instruction */
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#define RV_I_IMM_SIGN_OPOFF 31
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#define RV_I_IMM_11_0_OPOFF 20
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#define RV_I_IMM_SIGN_OFF 12
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#define RV_I_IMM_11_0_OFF 0
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#define RV_I_IMM_11_0_MASK GENMASK(11, 0)
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/* The bit field of immediate value in J-type instruction */
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#define RV_J_IMM_SIGN_OPOFF 31
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#define RV_J_IMM_10_1_OPOFF 21
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#define RV_J_IMM_11_OPOFF 20
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#define RV_J_IMM_19_12_OPOFF 12
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#define RV_J_IMM_SIGN_OFF 20
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#define RV_J_IMM_10_1_OFF 1
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#define RV_J_IMM_11_OFF 11
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#define RV_J_IMM_19_12_OFF 12
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#define RV_J_IMM_10_1_MASK GENMASK(9, 0)
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#define RV_J_IMM_11_MASK GENMASK(0, 0)
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#define RV_J_IMM_19_12_MASK GENMASK(7, 0)
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/*
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* U-type IMMs contain the upper 20bits [31:20] of an immediate with
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* the rest filled in by zeros, so no shifting required. Similarly,
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* bit31 contains the signed state, so no sign extension necessary.
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*/
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#define RV_U_IMM_SIGN_OPOFF 31
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#define RV_U_IMM_31_12_OPOFF 0
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#define RV_U_IMM_31_12_MASK GENMASK(31, 12)
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/* The bit field of immediate value in B-type instruction */
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#define RV_B_IMM_SIGN_OPOFF 31
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#define RV_B_IMM_10_5_OPOFF 25
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#define RV_B_IMM_4_1_OPOFF 8
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#define RV_B_IMM_11_OPOFF 7
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#define RV_B_IMM_SIGN_OFF 12
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#define RV_B_IMM_10_5_OFF 5
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#define RV_B_IMM_4_1_OFF 1
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#define RV_B_IMM_11_OFF 11
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#define RV_B_IMM_10_5_MASK GENMASK(5, 0)
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#define RV_B_IMM_4_1_MASK GENMASK(3, 0)
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#define RV_B_IMM_11_MASK GENMASK(0, 0)
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/* The register offset in RVG instruction */
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#define RVG_RS1_OPOFF 15
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#define RVG_RS2_OPOFF 20
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#define RVG_RD_OPOFF 7
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#define RVG_RD_MASK GENMASK(4, 0)
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/* The bit field of immediate value in RVC J instruction */
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#define RVC_J_IMM_SIGN_OPOFF 12
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#define RVC_J_IMM_4_OPOFF 11
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#define RVC_J_IMM_9_8_OPOFF 9
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#define RVC_J_IMM_10_OPOFF 8
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#define RVC_J_IMM_6_OPOFF 7
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#define RVC_J_IMM_7_OPOFF 6
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#define RVC_J_IMM_3_1_OPOFF 3
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#define RVC_J_IMM_5_OPOFF 2
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#define RVC_J_IMM_SIGN_OFF 11
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#define RVC_J_IMM_4_OFF 4
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#define RVC_J_IMM_9_8_OFF 8
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#define RVC_J_IMM_10_OFF 10
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#define RVC_J_IMM_6_OFF 6
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#define RVC_J_IMM_7_OFF 7
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#define RVC_J_IMM_3_1_OFF 1
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#define RVC_J_IMM_5_OFF 5
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#define RVC_J_IMM_4_MASK GENMASK(0, 0)
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#define RVC_J_IMM_9_8_MASK GENMASK(1, 0)
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#define RVC_J_IMM_10_MASK GENMASK(0, 0)
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#define RVC_J_IMM_6_MASK GENMASK(0, 0)
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#define RVC_J_IMM_7_MASK GENMASK(0, 0)
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#define RVC_J_IMM_3_1_MASK GENMASK(2, 0)
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#define RVC_J_IMM_5_MASK GENMASK(0, 0)
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/* The bit field of immediate value in RVC B instruction */
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#define RVC_B_IMM_SIGN_OPOFF 12
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#define RVC_B_IMM_4_3_OPOFF 10
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#define RVC_B_IMM_7_6_OPOFF 5
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#define RVC_B_IMM_2_1_OPOFF 3
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#define RVC_B_IMM_5_OPOFF 2
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#define RVC_B_IMM_SIGN_OFF 8
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#define RVC_B_IMM_4_3_OFF 3
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#define RVC_B_IMM_7_6_OFF 6
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#define RVC_B_IMM_2_1_OFF 1
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#define RVC_B_IMM_5_OFF 5
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#define RVC_B_IMM_4_3_MASK GENMASK(1, 0)
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#define RVC_B_IMM_7_6_MASK GENMASK(1, 0)
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#define RVC_B_IMM_2_1_MASK GENMASK(1, 0)
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#define RVC_B_IMM_5_MASK GENMASK(0, 0)
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#define RVC_INSN_FUNCT4_MASK GENMASK(15, 12)
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#define RVC_INSN_FUNCT4_OPOFF 12
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#define RVC_INSN_FUNCT3_MASK GENMASK(15, 13)
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#define RVC_INSN_FUNCT3_OPOFF 13
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#define RVC_INSN_J_RS2_MASK GENMASK(6, 2)
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#define RVC_INSN_OPCODE_MASK GENMASK(1, 0)
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#define RVC_ENCODE_FUNCT3(f_) (RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF)
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#define RVC_ENCODE_FUNCT4(f_) (RVC_FUNCT4_##f_ << RVC_INSN_FUNCT4_OPOFF)
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/* The register offset in RVC op=C0 instruction */
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#define RVC_C0_RS1_OPOFF 7
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#define RVC_C0_RS2_OPOFF 2
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#define RVC_C0_RD_OPOFF 2
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/* The register offset in RVC op=C1 instruction */
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#define RVC_C1_RS1_OPOFF 7
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#define RVC_C1_RS2_OPOFF 2
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#define RVC_C1_RD_OPOFF 7
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/* The register offset in RVC op=C2 instruction */
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#define RVC_C2_RS1_OPOFF 7
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#define RVC_C2_RS2_OPOFF 2
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#define RVC_C2_RD_OPOFF 7
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/* parts of opcode for RVG*/
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#define RVG_OPCODE_AUIPC 0x17
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#define RVG_OPCODE_BRANCH 0x63
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#define RVG_OPCODE_JALR 0x67
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#define RVG_OPCODE_JAL 0x6f
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#define RVG_OPCODE_SYSTEM 0x73
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/* parts of opcode for RVC*/
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#define RVC_OPCODE_C0 0x0
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#define RVC_OPCODE_C1 0x1
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#define RVC_OPCODE_C2 0x2
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/* parts of funct3 code for I, M, A extension*/
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#define RVG_FUNCT3_JALR 0x0
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#define RVG_FUNCT3_BEQ 0x0
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#define RVG_FUNCT3_BNE 0x1
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#define RVG_FUNCT3_BLT 0x4
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#define RVG_FUNCT3_BGE 0x5
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#define RVG_FUNCT3_BLTU 0x6
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#define RVG_FUNCT3_BGEU 0x7
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/* parts of funct3 code for C extension*/
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#define RVC_FUNCT3_C_BEQZ 0x6
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#define RVC_FUNCT3_C_BNEZ 0x7
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#define RVC_FUNCT3_C_J 0x5
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#define RVC_FUNCT3_C_JAL 0x1
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#define RVC_FUNCT4_C_JR 0x8
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#define RVC_FUNCT4_C_JALR 0x9
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#define RVC_FUNCT4_C_EBREAK 0x9
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#define RVG_FUNCT12_EBREAK 0x1
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#define RVG_FUNCT12_SRET 0x102
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#define RVG_MATCH_AUIPC (RVG_OPCODE_AUIPC)
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#define RVG_MATCH_JALR (RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR)
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#define RVG_MATCH_JAL (RVG_OPCODE_JAL)
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#define RVG_MATCH_BEQ (RV_ENCODE_FUNCT3(BEQ) | RVG_OPCODE_BRANCH)
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#define RVG_MATCH_BNE (RV_ENCODE_FUNCT3(BNE) | RVG_OPCODE_BRANCH)
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#define RVG_MATCH_BLT (RV_ENCODE_FUNCT3(BLT) | RVG_OPCODE_BRANCH)
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#define RVG_MATCH_BGE (RV_ENCODE_FUNCT3(BGE) | RVG_OPCODE_BRANCH)
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#define RVG_MATCH_BLTU (RV_ENCODE_FUNCT3(BLTU) | RVG_OPCODE_BRANCH)
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#define RVG_MATCH_BGEU (RV_ENCODE_FUNCT3(BGEU) | RVG_OPCODE_BRANCH)
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#define RVG_MATCH_EBREAK (RV_ENCODE_FUNCT12(EBREAK) | RVG_OPCODE_SYSTEM)
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#define RVG_MATCH_SRET (RV_ENCODE_FUNCT12(SRET) | RVG_OPCODE_SYSTEM)
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#define RVC_MATCH_C_BEQZ (RVC_ENCODE_FUNCT3(C_BEQZ) | RVC_OPCODE_C1)
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#define RVC_MATCH_C_BNEZ (RVC_ENCODE_FUNCT3(C_BNEZ) | RVC_OPCODE_C1)
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#define RVC_MATCH_C_J (RVC_ENCODE_FUNCT3(C_J) | RVC_OPCODE_C1)
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#define RVC_MATCH_C_JAL (RVC_ENCODE_FUNCT3(C_JAL) | RVC_OPCODE_C1)
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#define RVC_MATCH_C_JR (RVC_ENCODE_FUNCT4(C_JR) | RVC_OPCODE_C2)
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#define RVC_MATCH_C_JALR (RVC_ENCODE_FUNCT4(C_JALR) | RVC_OPCODE_C2)
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#define RVC_MATCH_C_EBREAK (RVC_ENCODE_FUNCT4(C_EBREAK) | RVC_OPCODE_C2)
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#define RVG_MASK_AUIPC (RV_INSN_OPCODE_MASK)
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#define RVG_MASK_JALR (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
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#define RVG_MASK_JAL (RV_INSN_OPCODE_MASK)
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#define RVC_MASK_C_JALR (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)
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#define RVC_MASK_C_JR (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)
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#define RVC_MASK_C_JAL (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
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#define RVC_MASK_C_J (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
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#define RVG_MASK_BEQ (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
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#define RVG_MASK_BNE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
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#define RVG_MASK_BLT (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
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#define RVG_MASK_BGE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
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#define RVG_MASK_BLTU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
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#define RVG_MASK_BGEU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
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#define RVC_MASK_C_BEQZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
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#define RVC_MASK_C_BNEZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
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#define RVC_MASK_C_EBREAK 0xffff
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#define RVG_MASK_EBREAK 0xffffffff
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#define RVG_MASK_SRET 0xffffffff
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#define __INSN_LENGTH_MASK _UL(0x3)
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#define __INSN_LENGTH_GE_32 _UL(0x3)
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#define __INSN_OPCODE_MASK _UL(0x7F)
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#define __INSN_BRANCH_OPCODE _UL(RVG_OPCODE_BRANCH)
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#define __RISCV_INSN_FUNCS(name, mask, val) \
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static __always_inline bool riscv_insn_is_##name(u32 code) \
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{ \
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BUILD_BUG_ON(~(mask) & (val)); \
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return (code & (mask)) == (val); \
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} \
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#if __riscv_xlen == 32
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/* C.JAL is an RV32C-only instruction */
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__RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL)
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#else
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#define riscv_insn_is_c_jal(opcode) 0
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#endif
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__RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)
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__RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)
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__RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)
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__RISCV_INSN_FUNCS(c_jr, RVC_MASK_C_JR, RVC_MATCH_C_JR)
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__RISCV_INSN_FUNCS(c_jalr, RVC_MASK_C_JALR, RVC_MATCH_C_JALR)
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__RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J)
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__RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ)
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__RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE)
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__RISCV_INSN_FUNCS(blt, RVG_MASK_BLT, RVG_MATCH_BLT)
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__RISCV_INSN_FUNCS(bge, RVG_MASK_BGE, RVG_MATCH_BGE)
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__RISCV_INSN_FUNCS(bltu, RVG_MASK_BLTU, RVG_MATCH_BLTU)
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__RISCV_INSN_FUNCS(bgeu, RVG_MASK_BGEU, RVG_MATCH_BGEU)
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__RISCV_INSN_FUNCS(c_beqz, RVC_MASK_C_BEQZ, RVC_MATCH_C_BEQZ)
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__RISCV_INSN_FUNCS(c_bnez, RVC_MASK_C_BNEZ, RVC_MATCH_C_BNEZ)
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__RISCV_INSN_FUNCS(c_ebreak, RVC_MASK_C_EBREAK, RVC_MATCH_C_EBREAK)
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__RISCV_INSN_FUNCS(ebreak, RVG_MASK_EBREAK, RVG_MATCH_EBREAK)
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__RISCV_INSN_FUNCS(sret, RVG_MASK_SRET, RVG_MATCH_SRET)
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/* special case to catch _any_ branch instruction */
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static __always_inline bool riscv_insn_is_branch(u32 code)
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{
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return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;
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}
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#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
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#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
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#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
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#define RVC_X(X, s, mask) RV_X(X, s, mask)
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#define RV_EXTRACT_RD_REG(x) \
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({typeof(x) x_ = (x); \
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(RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
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#define RV_EXTRACT_UTYPE_IMM(x) \
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({typeof(x) x_ = (x); \
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(RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
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#define RV_EXTRACT_JTYPE_IMM(x) \
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({typeof(x) x_ = (x); \
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(RV_X(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
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(RV_X(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
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(RV_X(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
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(RV_IMM_SIGN(x_) << RV_J_IMM_SIGN_OFF); })
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#define RV_EXTRACT_ITYPE_IMM(x) \
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({typeof(x) x_ = (x); \
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(RV_X(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
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(RV_IMM_SIGN(x_) << RV_I_IMM_SIGN_OFF); })
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#define RV_EXTRACT_BTYPE_IMM(x) \
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({typeof(x) x_ = (x); \
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(RV_X(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
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(RV_X(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
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(RV_X(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
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(RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); })
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#define RVC_EXTRACT_JTYPE_IMM(x) \
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({typeof(x) x_ = (x); \
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(RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \
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(RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \
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(RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \
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(RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \
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(RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \
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(RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \
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(RVC_X(x_, RVC_J_IMM_10_OPOFF, RVC_J_IMM_10_MASK) << RVC_J_IMM_10_OFF) | \
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(RVC_IMM_SIGN(x_) << RVC_J_IMM_SIGN_OFF); })
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#define RVC_EXTRACT_BTYPE_IMM(x) \
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({typeof(x) x_ = (x); \
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(RVC_X(x_, RVC_B_IMM_2_1_OPOFF, RVC_B_IMM_2_1_MASK) << RVC_B_IMM_2_1_OFF) | \
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(RVC_X(x_, RVC_B_IMM_4_3_OPOFF, RVC_B_IMM_4_3_MASK) << RVC_B_IMM_4_3_OFF) | \
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(RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \
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(RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \
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(RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
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