Hansen 07fe77c3ad drm/amd/display: Fix detection of 4 lane for DPALT ... [Why] DPALT detection for B0 PHY has its own set of RDPCSPIPE registers [How] Use RDPCSPIPE registers to detect if DPALT lane is 4 lane Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Hansen <Hansen.Dsouza@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-10-06 15:49:49 -04:00
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amdgpu_dm	drm/amd/display: Re-arrange FPU code structure for dcn2x	2021-10-06 15:49:24 -04:00
dc	drm/amd/display: Fix detection of 4 lane for DPALT	2021-10-06 15:49:49 -04:00
dmub	drm/amd/display: Prevent using DMUB rptr that is out-of-bounds	2021-10-04 15:23:02 -04:00
include	drm/amd/display: add cyan_skillfish display support	2021-10-04 15:22:57 -04:00
modules	drm/amd/display: Revert adding degamma coefficients	2021-09-14 15:57:10 -04:00
Kconfig	drm/amdgpu/display: fix dependencies for DRM_AMD_DC_SI	2021-10-04 15:23:02 -04:00
Makefile
TODO