Commit Graph

9 Commits

Author SHA1 Message Date
Rohit Agarwal
aae0f5314f ARM: dts: qcom: sdx65-mtp: Enable modem
Enable modem on SDX65 MTP board.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1654080312-5408-8-git-send-email-quic_rohiagar@quicinc.com
2022-06-27 16:10:59 -05:00
Kaushal Kumar
59e73f67e1 ARM: dts: qcom: sdx65-mtp: Enable QPIC NAND support
Enable QPIC NAND devicetree node for Qualcomm SDX65-MTP board.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1651511286-18690-5-git-send-email-quic_kaushalk@quicinc.com
2022-06-27 16:08:49 -05:00
Kaushal Kumar
eae61fddd6 ARM: dts: qcom: sdx65-mtp: Enable QPIC BAM support
Enable QPIC BAM devicetree node for Qualcomm SDX65-MTP board.
While at it, sort the blsp1_uart3 node in alphabetical order
and set it's status as "okay".

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1651511286-18690-4-git-send-email-quic_kaushalk@quicinc.com
2022-06-27 16:08:49 -05:00
Rohit Agarwal
eeaec4f2b9 ARM: dts: qcom: sdx65-mtp: Enable USB3 and PHY support
Enable the support for USB3 controller, QMP PHY and HS PHY on SDX65 MTP.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1651482395-29443-5-git-send-email-quic_rohiagar@quicinc.com
2022-06-27 16:08:03 -05:00
Rohit Agarwal
a30be44449 ARM: dts: qcom: sdx65: Add reserved memory nodes
Add reserved memory nodes to the SDX65 dtsi as defined by
the memory map.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1649670615-21268-2-git-send-email-quic_rohiagar@quicinc.com
2022-04-12 22:35:04 -05:00
Rohit Agarwal
dc39466a73 ARM: dts: qcom: sdx65-mtp: Add regulator nodes
Add the regulators found on SDX65 MTP.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-7-git-send-email-quic_rohiagar@quicinc.com
2022-04-12 22:29:40 -05:00
Rohit Agarwal
1ebc5adc26 ARM: dts: qcom: sdx65-mtp: Add pmx65 pmic
SDX65-mtp features PMX65 pmic, so include the dts as well.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-4-git-send-email-quic_rohiagar@quicinc.com
2022-04-12 22:29:40 -05:00
Rohit Agarwal
26380f298b ARM: dts: qcom: sdx65-mtp: Add pmk8350b and pm8150b pmic
SDX65-mtp features PMK8350b and PM8150B pmic, so include the dts as well

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-3-git-send-email-quic_rohiagar@quicinc.com
2022-04-12 21:55:38 -05:00
Vamsi krishna Lanka
bae2f5979c ARM: dts: qcom: Add SDX65 platform and MTP board support
Add basic devicetree support for SDX65 platform and MTP board from
Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms
the Application Processor Sub System (APSS) along with standard Qualcomm
peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there
exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem
etc..

This commit adds basic devicetree support that includes GCC, RPMh clock, INTC
and Debug UART.

Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com
2021-12-14 21:04:33 -06:00