The memory range for the hwuart is at 0x41600000, not 0x41100000.
This also solves a conflict with the MMC controller node.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
The pinctrl node does not have any children, so the #address-cells and #size-cells
properties are not needed.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
PXA is single-core only, so this node will not have enumerable children.
Drop the #address-cells and #size-cells properties to squelch a dtc warning.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Add a device node for hardware graphic acceleration.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Add node for s5p-jpeg codec, which is present in S5PV210 SoC.
Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The base aspeed-g5.dtsi already defines a '/memory@80000000' node, so
'/memory' in the board files create a duplicate node. We're probably
getting lucky that the bootloader fixes up the memory node that the
kernel ends up using. Add the unit-address so it's merged with the base
node.
Found with DT json-schema checks.
Cc: Joel Stanley <joel@jms.id.au>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-aspeed@lists.ozlabs.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
There's a bug in dtc in checking for duplicate node names when there's
another section (e.g. "/ { };"). In this case, skeleton.dtsi provides
another section. Upon removal of skeleton.dtsi, the dtb fails to build
due to a duplicate node 'fixedregulator@0'. As both nodes were pretty
much the same 3.3V fixed regulator, it hasn't really mattered. Fix this
by renaming the nodes to something unique. In the process, drop the
unit-address which shouldn't be present wtihout reg property.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
- support more timers on meson8
- add the stdout-path property on several boards
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAlwATkAACgkQWTcYmtP7
xmUJ5w/+KMrv+9D9uqdRRBjMxyGfYURCsY+sA/iT1TPjBruVCl9Js6uQ77h8NZ5W
oCkEmrL2t8oSK4q8BqR7F9ayzloM5G3i7ruIzgVQE0pHWdVxvJa+zlsrnCI9/Gsv
Swy9zpXzHIcRZNiMewBYwvB/cO/qYmNxjnWi3NintE6NSv0Syl0q6MMoTlUSdyoE
MFednj/OcQyt8csBeJljVhZ6P7VLaag2WHIe7JqTa53qUU/qRGA18g8qb7UnHmUC
BWJaFzzfXG8Tr9nP1ddo3WTeHskgzWiuObnXw64ep2wMcVU+HsbPGiMyWLXzpjrM
8IEOFGTuxNeY7M9Rs7jhyFWAqP9Ls0USiiOOuHiyFENumVc3WCVXTl7toTXbW1qc
kVyE4BbdAIwd2Zbwr6gimr2Q0Gzz2oHK09+gBGrAvgZvt+Kwf7QCOMoGlokAVkMX
h+wJyqC+2PABV/Desl3ocjMQtuLRfIL6/NyFfcWqSXLMLhXPqMfNQ+k3p/ZcgH9d
9Q0zre83NeBCgNk7QejZW85XHfkyekqkPGnWJHQkOO5XHJmaaRTmUM7wiV6l6emE
3JBil39sHkPsiInYd6yvbZs4g5InOXvTDf43fHBeWRMxBBpxpGf57HYa9ib7r6MJ
asnfxjBwdYcwzWg+Gb7Ri0Jmi4xUxROrhuiMKLfbDCLmt+yIPBE=
=9yK+
-----END PGP SIGNATURE-----
Merge tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt
Amlogic 32-bit DT updates for v4.21
- support more timers on meson8
- add the stdout-path property on several boards
* tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM: dts: meson: add the clock inputs for the Meson timer
ARM: dts: meson: add the TIMER B/C/D interrupts
ARM: dts: meson: consistently disable pin bias
ARM: dts: meson8b: mxq: add the /chosen/stdout-path property
ARM: dts: meson8: minix-neo-x8: add the /chosen/stdout-path property
ARM: dts: meson6: atv1200: add the /chosen/stdout-path property
dt-bindings: timer: meson6_timer: document the clock inputs
dt-bindings: timer: meson6_timer: document all interrupts
Signed-off-by: Olof Johansson <olof@lixom.net>
These changes mostly configure pinctrl for am437x-gp-evm. There is
also non-critical fix for a comment for Clang, and we enable earlycon
for am3517-evm.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlwAQlARHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXPKSw//V+EavS1zpABU2bEHH/4b+SktvPFOf78u
o1kwMYHnpabWyRyhM3tz/vaUvoEwVWh1CA2G1jyBQl5Go8LhgyHsx6tRuI0c0oqz
atoDpexURkE/3NMyv2AewyWKzpW3kEfCJ/Udt1+gvByzb2AISpxjcv+nD1Cywv5w
hkGtRBh5bT9eloGN+2sZspKRcc2bFUo9wWBc/TJ+m5t1uodrt3xNaPXJDenE2Qa4
XNHzQPG4ektb6Pd8yXXPQLap3Bme5oXv0yp/UTus8bPWaQBVKNroYiXiyKeGTJS6
mWhpmquJmFjojLTVU7kbgOKcH0BmWHizhr/I3Lpq9aRjR/mDyMPQGt4eM3XhITv8
6x8ZAu+dLUmfSGAcVK4Tudw2LTea04u43DWTPmvx2ARXzyIC5658rEkpot8LMBhI
FMOdHT8pqbCP7PQ0YwLYzshckqhl7Mg7dIaJED10S71s7r0BA7h0lHntfh6jiPDG
SNGcgjf0glyye4IG65qArOsCVZkbUpXX7kQC+BlZ2W8xfg5k+8fPjcrA1jFP1C1L
ASpm2fdNHjLFaV3Kfp1wezbC4zmkdtCyYqJ5tE/S0TndNMRatFWIhTtF9JU9s9hK
FzmqBPcdyrsgDh01RBkEfbPpjygTV3ZxFzQAqnaciuGhxUsNyahMzjGyN/1z1UCu
qt6px/yF8FE=
=/+sU
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.21/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Device tree changes for omaps for v4.21 merge window
These changes mostly configure pinctrl for am437x-gp-evm. There is
also non-critical fix for a comment for Clang, and we enable earlycon
for am3517-evm.
* tag 'omap-for-v4.21/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am437x-gp-evm: Add sleep state for beeper pins
ARM: dts: am437x-gp-evm: Add pinmux for gpio0 wake
ARM: dts: am437x-gp-evm: Add uart0 pinctrl default and sleep states
ARM: dts: am437x-gp-evm: Add pinctrl for debugss pins
ARM: dts: am437x-gp-evm: Add pinctrl for unused_pins
ARM: dts: am437x-gp-evm: Add state for ddr3 vtt toggle pin
ARM: dts: am3517-evm: Enable earlycon stdout path
ARM: dts: omap3-gta04: Fix comment block
Signed-off-by: Olof Johansson <olof@lixom.net>
This updates the Versatile Express family DTS files to
contain the correct and detailed information required
for the PL11x DRM driver to work properly.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJb/5ZcAAoJEEEQszewGV1zXo0QAMzrWDyBqNxgPR5XwNJBzgu1
x68wAA9N3jLXvHm0KG+J5OP9830m3uCLefhH4/dZN5XV4EjMME9n1Uv+uz6/8/Uu
fGBMFR1AwIH1qbN1bhG6wcC495vsUp+k8Q8zkpTZ4iT18pv0FMLgTugpOUIIbhxP
1oUP4xi/c97190QRy1OS7MDTyXElhrxoVtrjmggE9kWgkHPP76FX9ZAQE5EMTDtU
+O6JrpWuNjpusgOaTYwgNeKzOloAcFbNcaQOGLjHQmGoFRgRuK1jP+ZpULyFaJKo
5U4D6haYKJqcVhzlMclZa2rh3gkH8M8YUGhDNDABKiTdy1R+gkn44GWKBT9+uKpl
ve0Jd6ca3DhBe/XQlCADUYGmGy6PUJY9DpWCNxCZn/BBsSOLMiom51jndsnk8Y5b
gszQnkDPIv6tKxuUIxLS7Q89Jf3TIlVwiDbVHlzvYjiAqJQ9fsRa/BrGM5FknMl6
YAg8UPAqveUt26RL2t4VEpVY9FSJtCFsmvD202dbmbkJYHpihIN5Nse+msxAn5Ln
GbCZsA5SFSUapXYDSPQmpLiu2fGS8ojVUzadAKvoG1ktIo1h1SMbvBpHjeERIKaM
Zw1ErQ5IMyAhtXq64dqIEIgesb7zYiZ+TC89huJr96CRkShfu2bLy0oaqa09GUvk
JXPF+OrQmUqmq/5P385H
=4oHX
-----END PGP SIGNATURE-----
Merge tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt
Versatile Express DTS update for DRM:
This updates the Versatile Express family DTS files to
contain the correct and detailed information required
for the PL11x DRM driver to work properly.
* tag 'vexpress-drm-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: Modernize the Vexpress PL111 integration
Signed-off-by: Olof Johansson <olof@lixom.net>
Despite Marvel keeps their base addresses secret there's a good chance
they're actually correct.
SSP1 and SSP3 bases were taken from OLPC 1.75: OpenFirmware and kernel
respectively. SSP2 and SSP4 addresses are from James Cameron who actually
has a copy of the data sheet.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Olof Johansson <olof@lixom.net>
The USB OTG PHY chip. To be used by the OTG controller.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Olof Johansson <olof@lixom.net>
I've gotten the base addresses, clocks and interrupts from an rusty and old
out-of-tree driver. I haven't actually checked against the datasheet, since
that one is reserved for the Marvell inner circle.
Tested with an accelerometer on TWSI6 on an OLPC XO 1.75 machine.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Olof Johansson <olof@lixom.net>
Marvell keeps their MMP2 datasheet secret, but there are good clues
that TWSI2 is not on 0xd4025000 on that platform, not does it use
IRQ 58. In fact, the IRQ 58 on MMP2 seems to be a signal processor:
arch/arm/mach-mmp/irqs.h:#define IRQ_MMP2_MSP 58
I'm taking a somewhat educated guess that is probably a copy & paste
error from PXA168 or PXA910 and that the real controller in fact hides
at address 0xd4031000 and uses an interrupt line multiplexed via IRQ 17.
I'm also copying some properties from TWSI1 that were missing or
incorrect.
Tested on a OLPC XO 1.75 machine, where the RTC is on TWSI2.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Olof Johansson <olof@lixom.net>
There's apparently four of them on a MMP2.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Olof Johansson <olof@lixom.net>
The timer needs the timer clock to be enabled, otherwise it stops
ticking.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Olof Johansson <olof@lixom.net>
This will be useful for boards that actually use GPIO pins.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Olof Johansson <olof@lixom.net>
gpio-pxa uses two cell to encode the interrupt source: the pin number
and the trigger type. Adjust the device node accordingly.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Olof Johansson <olof@lixom.net>
- Use SPDX license identifier for all SoCFPGA DTS files.
- Remove dma-mask property as it has been deprecated.
- Use tabs in DTS files.
- Use the specific "altr,stratix10-rst-mgr" property for the Stratix10
reset manager.
-----BEGIN PGP SIGNATURE-----
iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAlv+teoUHGRpbmd1eWVu
QGtlcm5lbC5vcmcACgkQGZQEC4GjKPS9Sg//b6N0rtVZlkVaOVtTDR+X/y3/GKyx
ZCbNaCygR5Iy17nz2XU/h9R/QEPDCWllmJyykvJ4jorwHLeebI2+CDN6aYRSZrA5
dKw7OFsWntRYAE9Z2v23fATPK0Gc94GopcE0p53YBMS03atKdf06ORDdYPTWs+bi
4TmP40NcQzTvcNDuOrnkE1Kg1QhH6hakt5u5d2zt4JK7oCkLsMH9uOF4XuoqXDfc
1RatsAaSbA5JRAB09y+uvPrFrDeA3Guzx9FruBhR4EdSgDJzVnKLZM8/7z+Zmq52
lwIcpaWBtSgcvB7BgfxgCEsfDbTIlrupWuWGubIShD6oBBdXqk8m5t2E0wqTbyuq
LJ72OBpUIo2KvMb2Q2cBDW5nyTGkiimf7DUjcBRLmPtAbpubrovt8jJGyJqzzbvn
p6Rf2AfYm43WiyeNCJGk4nnzO+gGS6T/RTvDIjMhLLRJtiftuj3JRlcJ7Ihx2deO
Cwu84mbyLQjT9VGOuLdtXAy8fDsZfpkJ9DVavWq8FPbZCdKhuk3vSyrxSVx/QPHt
uWeauXbyaL+aTOx6pH7opdl84nOwb8zVrldunmhzv0UmrrylttHGS0Dr1L2JiPip
bOBaPmHKDUFNjgL67PLQ4QCXIUe+4YSFUqRwiyF6e47TR4yVj5cDsUbHI/ttPiR0
cvfeRb6etth+ri0=
=IDQS
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_updates_for_v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS updates for v5.0
- Use SPDX license identifier for all SoCFPGA DTS files.
- Remove dma-mask property as it has been deprecated.
- Use tabs in DTS files.
- Use the specific "altr,stratix10-rst-mgr" property for the Stratix10
reset manager.
* tag 'socfpga_dts_updates_for_v5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: stratix10: use "altr,stratix10-rst-mgr" binding
ARM: dts: socfpga: use tabs for indentation
arm: dts: socfpga: remove dma-mask property
arm: dts: socfpga*.dts*: use SPDX-License-Identifier
Signed-off-by: Olof Johansson <olof@lixom.net>
regulator name and referencing all cpus in the cooling maps instead
of only cpu0.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlv2mkYQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgf2ZCACoJZ1G4trbzqhdH1DXlLac7hsk+Hu/1jTW
WrP6mXVyOJLdo3XRAoYEKI8WFx88pyXUDuXnxH4vO2SaoEDyIDYGuYxiiDZsrMiv
oX0uyx9JKpY3cSBiDsPkfaxdcyGmVP2x10gxJvcoF4mP3FlMh5Ovtoyq83djxm7B
/kw0NniMU9qKn8ilPAy+kiNADQkC3swupq0uLpt4wgvIPKkiGWEEaJjG30boc21q
qpFlB9PowM52ZIqttTjvzh/wnb0eB6sEcI9tuuUa4S8y0PHzRpiIco0pqUsuq6I4
UbAbqshORINRkJTZwhfw4HWmrKLF5s6vXGKFbx9M3TgVHKWGYHTw
=zDNA
-----END PGP SIGNATURE-----
Merge tag 'v4.21-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Powerdomain and QoS nodes for rk3066 and rk3188. A fix for a rock2
regulator name and referencing all cpus in the cooling maps instead
of only cpu0.
* tag 'v4.21-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: Add all CPUs in cooling maps
ARM: dts: rockchip: Fix rk3288-rock2 vcc_flash name
ARM: dts: rockchip: add rk3066/rk3188 power-domains
ARM: dts: rockchip: add qos nodes found on rk3066 and rk3188
dt-bindings: add power-domain header for RK3066 SoCs
dt-bindings: add power-domain header for RK3188 SoCs
Signed-off-by: Olof Johansson <olof@lixom.net>
- Reomve non-existing EEPROM device from imx51-zii-rdu1 board.
It was added by mistake.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJcAVNxAAoJEFBXWFqHsHzO0SYH/06mGVqrvAdCYYMamrcLPkom
7aVizSIcK6O+9ddxhA5pDSHMIKu0Wjn6d1acySeql6AWg0d9pECydoI7Rgfj/fDC
mw/aXlv9TJv+4R6/2MI/CEO2Xfi0c2d0nCzTAmsL3CKp92hIVqPTxc7mW5K9J8bx
W2wbj1wueCn/cLiynDV25krxq4BRbsU8g0Ke+HiuO89W9Qb87qgPyJjWeecyH/dl
/llXuiFzZqHYpmzdYacnKvKResVCCc8Ev4VgEF89M1M9tgOojQOakFfMBfTDEIHG
iooQLc6WLdYjsqDhmnUEbonZ+pHBbNPUvV0iHmR/9y0SyVZdrGgNWjVRSkKuT6I=
=OlmI
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
i.MX fixes for 4.20, round 2:
- Reomve non-existing EEPROM device from imx51-zii-rdu1 board.
It was added by mistake.
* tag 'imx-fixes-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx51-zii-rdu1: Remove EEPROM node
Signed-off-by: Olof Johansson <olof@lixom.net>
This set of fixes contains minor regression fixes for LogicPD dts files
for MMC pinctrl and interrupts. There is also one section annotation fix
that shows up with Clang, and a fix for an unitialized field for omap1.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlwANxERHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXMqpw/9G+M+1FEb8SAXgdb1B2Qp9qkAe89jO2DV
1yHtGKgS4z9yKBm/al/hYPNDQcIfX0aziBwo4pYwTxQe+FyziBmy/o/aTDc711fy
YTXt2jAka+Meu1DbGx78CE+h2QCBMEA2QZzwFvFxIppIzE985gfR56D8F9stHsHH
7omIvpGMVchlH7hZg+oFPyFU5dYoFen4BbRd2B2Yk2+N/tLRdnJhvTtmZbOCyg8/
uI+UYFEZM6jc1dztVilKJETnAknJnt54CzylgQNULISKN+omRC6p1D8JjIM1nSt0
IihcG1YCXhBRc/W7oM5tFpihJKJtu+LVNiTXzltt1sJMEDkvnGA17UhTpzhdsE83
vSP6ZPe2M9BRbrSBo+Jq21mP4a5HdQUV93UMzrtPVRrD1G56UUZUTztZJMghyUmX
H2ougoQ1/U++PVPXRtdPKviebfWLS2TuPIj9Ebdk27lnOgCMvrbxLXGA5ILhC3zZ
xqEeZfAPoM99lzXkk1mGQLPAMoVk5RwqyURfs3fMnt+qU2gsLNsZpJ3GvzGMDtkL
GXZuOLTg060X6Elbs+GsZjmga0qglW9vsa0JWiby0rmPBCmJiMGwr24WHFHf8NcH
Xz8nVMyp4+VLXDh5GUzFdjbAD1R9JB76rdNIQKTBYohveCzLUjOtSw1F7asKLI+U
jKI73eyresU=
=EaEX
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.20/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Few minor fixes for omaps for v4.20-rc cycle
This set of fixes contains minor regression fixes for LogicPD dts files
for MMC pinctrl and interrupts. There is also one section annotation fix
that shows up with Clang, and a fix for an unitialized field for omap1.
* tag 'omap-for-v4.20/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP1: ams-delta: Fix possible use of uninitialized field
ARM: dts: am3517-som: Fix WL127x Wifi interrupt
ARM: dts: logicpd-somlv: Fix interrupt on mmc3_dat1
ARM: dts: LogicPD Torpedo: Fix mmc3_dat1 interrupt
ARM: dts: am3517: Fix pinmuxing for CD on MMC1
ARM: OMAP2+: prm44xx: Fix section annotation on omap44xx_prm_enable_io_wakeup
Signed-off-by: Olof Johansson <olof@lixom.net>
firmware on these devices as issues identifying the formally correct
node.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlv2krMQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgenqB/4z/gAlUZ8xo9au7cHLXOKmg7WkhqRkWHsr
F1rib1I8wv2d6X+PkQv6QiejaJcp+Tj4unx6IGx904PADlCRj38uo+7jEgirf3h+
MGUcZM9+A1V1IvN31eaSTax9KO/XUaABxCBiDSH91YM6JZHRTh1oskjC1lt2pmfF
yygoVfX0jA6GC9+S1YpKAmMyY37ZFIyiZFak5qVPzDDIHKqRLgFDDc2gGTlsqTca
glxbHapRHXg624wUcuGgnRmhhrzNPFzrQ89/LAZX9MBAwC8p2SekhzE7VR2nAvvZ
9Asl7SU2lOjYTpWP/b8jONpPIPvDSXKnfYxQSYDD+Eud+kUk+rqU
=wPsf
-----END PGP SIGNATURE-----
Merge tag 'v4.20-rockchip-dts32fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes
Moving the veyron memory node from memory@0 back to memory, as the
firmware on these devices as issues identifying the formally correct
node.
* tag 'v4.20-rockchip-dts32fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: Remove @0 from the veyron memory node
Signed-off-by: Olof Johansson <olof@lixom.net>
Single patch to use updated coresight graph bindings thereby removing
loads of dtc warnings
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJboNezAAoJEABBurwxfuKYFB0QAKxuGglCbwo5YitzfrsEKFFK
HRCCl8VdmN9ENGsM+wK3qMED6wLeAaQGpGmIpE5Gn8DYBKKQ0S16nEcMg+9CmmOg
jPrcFqbpliDOkwwblwl/pV1vcaTE4bGs7ZF+7TrHJVxwY/GEgjJn56No0mWrxs9i
wqegu5vc0pky9lFMFlw4/5zwDycRbb8Zxgg3X6sAfoGdhLoCgusXLk4DOy3HyA8n
rz4MsUwQmTw9O1JtMxNSqFfWBJSm6nom7C0z9iS4iISKGIlId0r1z5W83Km5/seW
ChChUzWrKOMY6xYhoexkw5m4vI/RjbNcp5CvO+C6SHkyHWzwvNeHLdP9CMpVavTs
OvRUFyXbozRn4PzvK+oE+vCbKoLO+14VtBIG0UXS5F4ykEg3gMur38v91rhTdCWc
y1VsK5fHid26tJYNwTg5KbT4wOWM4bE6JCaDvibaWFum2RYLwh6WuN+tqV0PDjLM
qovVTABQcMXDTxfEG78GvQF0vb6lpN3CEzFZdjQPmUPJveYxG7g9TQVVNKEdJKjj
9w4AiNub0c3kdVHqwFrmoYj6a8BuA9w7w+MjEISX6mr5tZqxh61ygZwp4p4AyKwt
VLFuXgj+0gEAg60Km8Z2X7PcxySOoX8vjWiiNTdbtAtUsM4m6kX3RrjM/qp1HW1u
FB/pQ3kiwb4Ye0DtyJSK
=8TMG
-----END PGP SIGNATURE-----
Merge tag 'vexpress-updates-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt
ARMv7 Vexpress updates for v4.20
Single patch to use updated coresight graph bindings thereby removing
loads of dtc warnings
* tag 'vexpress-updates-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
ARM: dts: vexpress/TC2: Update entries to match latest coresight bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
This describes hardware & will allow referencing pin functions. The
first usage is UART1 which allows supporting devices using it.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
It is wireless home router based on BCM4708A0 with BCM4360 + BCM4331
wireless chipsets. The BCM4331 5GHz chip currently isn't supported only
due to missing compatible firmware.
Signed-off-by: Rene Kjellerup <rk.katana.steel@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Hwmod parses the DT hierarchically from root to search for matching
ti,hwmod property. With the introduction of L4 data, we have two nodes
with the ti,hwmod = "gmac" declaration, and the hwmod core only matches
the first one found, which is the target-module one. This node incorrectly
dropped the ti,no-idle flag, which causes number of problems, like ignoring
errata i877, and also causing an intermittent boot failure on certain dra7
boards.
Fix the issue by moving the ti,no-idle flag to the proper node.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Without this McASP FIFO would constantly underflow. EDMA
test via dmatest works though.
Let's revert the change for now until we know the root cause.
Reported-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Video Image Compositor can be used to perform a variety of image
operations. Add a device tree node for it, so that it can be exposed
as a host1x channel to userspace.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Versatile Express was submitted with the actual display
bridges unconnected (but defined in the device tree) and
mock "panels" encoded in the device tree node of the PL111
controller.
This doesn't even remotely describe the actual Versatile
Express hardware. Exploit the SiI9022 bridge by connecting
the PL111 pads to it, making it use EDID or fallback values
to drive the monitor.
The also has to use the reserved memory through the
CMA pool rather than by open coding a memory region and
remapping it explicitly in the driver. To achieve this,
a reserved-memory node must exist in the root of the
device tree, so we need to pull that out of the
motherboard .dtsi include files, and push it into each
top-level device tree instead.
We do the same manouver for all the Versatile Express
boards, taking into account the different location of the
video RAM depending on which chip select is used on
each platform.
This plays nicely with the new PL111 DRM driver and
follows the standard ways of assigning bridges and
memory pools for graphics.
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Mali DP Maintainers <malidp@foss.arm.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Tested-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Meson Timer IP block has two clock inputs:
- clk81 for using the system clock as timebase
- xtal for a timebase with 1us, 10us, 100us and 1ms resolution
The clocksource driver does not use these yet, but it's still a good
idea to add them as this describes how the hardware actually works
internally.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The timer on Meson6/Meson8/Meson8b SoCs has four internal timer events.
For each of these a separate interrupt exists.
Pass these interrupts to allow using the timers other than TIMER A.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
On Amlogic chipsets, the bias set through pinconf applies to the pad
itself, not only the GPIO function. This means that even when we change
the function of the pad from GPIO to anything else, the bias previously
set still applies.
As we have seen with the eMMC, depending on the bias type and the function,
it may trigger problems.
The underlying issue is that we inherit whatever was left by previous user
of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual
setup we will get is undefined.
There is nothing mentioned in the documentation about pad bias and pinmux
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch removes support for the APQ8064 based Arrow SD600 eval
board. This board was never sold publicly and had very limited
distribution. As such, we are removing this board and no longer
going to support it.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Nicolas Dechesne <nicolas.dechesne@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
As per upstream discussion [1], we should have an SoC-specific
compatible string for Qualcomm's SDHCI nodes. Let's add it.
[1] https://lkml.kernel.org/r/20181105203657.GA32282@bogus
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch correctly sets the gpios property for the ak8963
magnetometer's DRDY pin so that interrupts work properly.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
In two of the gen5 socfpga devicetree files, there are some lines
indented using spaces instead of tabs.
Fix this by correctly indenting them with tabs.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Follow the recent trend for the license description.
This is also in an effort to fully sync the devicetrees with U-Boot.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Our memory node will generate a warning in DTC since the unit address is
not matching the reg property. However, that node will be created by the
bootloader, so we can just remove it entirely in order to remove that
warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The MMC0 controllers have only one muxing option in the SoC. In such a
case, we can just move the muxing into the DTSI, and remove it from
the DTS.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
All our pinctrl nodes were using a node name convention with a unit-address
to differentiate the different muxing options. However, since those nodes
didn't have a reg property, they were generating warnings in DTC.
In order to accomodate for this, convert the old nodes to the syntax we've
been using for the new SoCs, including removing the letter suffix of the
node labels to the bank of those pins to make things more readable.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
One of the usage of the LRADC is to implement buttons. The bindings define
that we should have one subnode per button, with their associated voltage
as a property.
However, there was no reg property but we still used the voltage associated
to the button as the unit-address, which eventually generated warnings in
DTC.
Rename the node names to avoid those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Most of our device trees have had leading zeros for padding as part of
the nodes unit-addresses.
Remove all these useless zeros that generate warnings
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The i2c nodes were pre-populated to ease the use of overlays. However, now
that we provide default muxing options for those nodes, the one in the DTS
don't provide any content at all.
Remove them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The I2C's and MMC0 controllers have only one muxing option in the SoC. In
such a case, we can just move the muxing into the DTSI, and remove it from
the DTS.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Now that all the SoCs using the tablet reference design DTSI are using the
same pinctrl naming scheme, we can move back the pinctrl phandles to the
main DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Some GPIO pinctrl nodes cannot be easily removed, because they would also
change the pin configuration, for example to add a pull resistor or change
the current delivered by the pin.
Those nodes still have underscores and unit-addresses in their node names
in our DTs, so adjust their name to remove the warnings. Use that occasion
to also fix some poorly chosen node-names.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
All our pinctrl nodes were using a node name convention with a unit-address
to differentiate the different muxing options. However, since those nodes
didn't have a reg property, they were generating warnings in DTC.
In order to accomodate for this, convert the old nodes to the syntax we've
been using for the new SoCs, including removing the letter suffix of the
node labels to the bank of those pins to make things more readable.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Boards usually have an external pull-up on the card-detect signal, so
there's no need to add another one.
This also removes a DTC warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The pin groups are supposed to be in alphabetical order, and they aren't.
Fix this.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
One of the usage of the LRADC is to implement buttons. The bindings define
that we should have one subnode per button, with their associated voltage
as a property.
However, there was no reg property but we still used the voltage associated
to the button as the unit-address, which eventually generated warnings in
DTC.
Rename the node names to avoid those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The gpio pinctrl nodes are redundant and as such useless most of the times.
Since they will also generate warnings in DTC, we can simply remove most of
them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Some boards override the MMC pin muxing settings in order to enable the
pull-ups and change the drive strength to a value higher than the default.
While this was needed in the earlier days, this is now the default setting
for those pins, and therefore we don't need those board-specific settings
anymore.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The simple-framebuffer nodes have a unit address, but no reg property which
generates a warning when compiling it with DTC.
Change the simple-framebuffer node names so that there is no warnings on
this anymore.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Most of our device trees have had leading zeros for padding as part of
the nodes unit-addresses.
Remove all these useless zeros that generate warnings
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The #address-cells and #size-cells are only relevant for nodes that have
childs with reg properties. Otherwise, DTC will emit a warning saying that
those properties are unnecessary.
Remove them when needed.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
DTC will emit a warning on our OPPs nodes for the common DTSI between the
A23 and A33 since those nodes use the frequency as unit addresses, but
don't have a matching reg property.
Fix this by moving the frequency to the node name instead.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Our main node for all the in-SoC controllers used to have a unit name. The
unit-name, in addition to being actually false, would not match any reg
property, which generates a warning.
Remove it in order to remove those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Using skeleton.dtsi will create a memory node that will generate a warning
in DTC. However, that node will be created by the bootloader, so we can
just remove it entirely in order to remove that warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The #address-cells and #size-cells are only relevant for nodes that have
childs with reg properties. Otherwise, DTC will emit a warning saying that
those properties are unnecessary.
Remove them when needed.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Some boards override the MMC pin muxing settings in order to enable the
pull-ups and change the drive strength to a value higher than the default.
While this was needed in the earlier days, this is now the default setting
for those pins, and therefore we don't need those board-specific settings
anymore.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The I2C and MMC controllers have only one muxing option in the SoC. In such a
case, we can just move the muxing into the DTSI, and remove it from
the DTS.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Our HDMI output endpoint on the A10s DTSI has a warning under DTC: "graph
node has single child node 'endpoint', #address-cells/#size-cells are not
necessary". Fix this by removing those properties.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Some GPIO pinctrl nodes cannot be easily removed, because they would also
change the pin configuration, for example to add a pull resistor or change
the current delivered by the pin.
Those nodes still have underscores and unit-addresses in their node names
in our DTs, so adjust their name to remove the warnings. Use that occasion
to also fix some poorly chosen node-names.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The SOM204-EVB doesn't use the CTS pin, and thus was defining its own
pinctrl node for the UART3 muxing. Since we split away the TX and RX pin,
we can use the global node now, and only have the RTS pin in our local
node.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Some UART nodes on the A20 DTSI do not share the same pattern that we use
everywhere else, with the RTS and CTS pins split away from the TX and RX
pins. Make those pin groups consistent with the rest of our DT.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
All our pinctrl nodes were using a node name convention with a unit-address
to differentiate the different muxing options. However, since those nodes
didn't have a reg property, they were generating warnings in DTC.
In order to accomodate for this, convert the old nodes to the syntax we've
been using for the new SoCs, including removing the letter suffix of the
node labels to the bank of those pins to make things more readable.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Some gpio-keys definitions in our DTs were having buttons defined with a
unit-address and that would generate a DTC warning.
Change the buttons node names to remove the warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
One of the usage of the LRADC is to implement buttons. The bindings define
that we should have one subnode per button, with their associated voltage
as a property.
However, there was no reg property but we still used the voltage associated
to the button as the unit-address, which eventually generated warnings in
DTC.
Rename the node names to avoid those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Boards usually have an external pull-up on the card-detect signal, so
there's no need to add another one.
This also removes a DTC warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The gpio pinctrl nodes are redundant and as such useless most of the times.
Since they will also generate warnings in DTC, we can simply remove most of
them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The simple-framebuffer nodes have a unit address, but no reg property which
generates a warning when compiling it with DTC.
Change the simple-framebuffer node names so that there is no warnings on
this anymore.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Our oscillators clock names have a unit address, but no reg property, which
generates a warning in DTC. Change these names to remove those unit
addresses.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Our main node for all the in-SoC controllers used to have a unit name. The
unit-name, in addition to being actually false, would not match any reg
property, which generates a warning.
Remove it in order to remove those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Using skeleton.dtsi will create a memory node that will generate a warning
in DTC. However, that node will be created by the bootloader, so we can
just remove it entirely in order to remove that warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The I2C and MMC controllers have only one muxing option in the SoC. In such a
case, we can just move the muxing into the DTSI, and remove it from
the DTS.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Our I2C GPIO bus node name has a unit address, but no reg property, which
generates a warning in DTC. Change the name to remove that unit address.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Some GPIO pinctrl nodes cannot be easily removed, because they would also
change the pin configuration, for example to add a pull resistor or change
the current delivered by the pin.
Those nodes still have underscores and unit-addresses in their node names
in our DTs, so adjust their name to remove the warnings. Use that occasion
to also fix some poorly chosen node-names.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
All our pinctrl nodes were using a node name convention with a unit-address
to differentiate the different muxing options. However, since those nodes
didn't have a reg property, they were generating warnings in DTC.
In order to accomodate for this, convert the old nodes to the syntax we've
been using for the new SoCs, including removing the letter suffix of the
node labels to the bank of those pins to make things more readable.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Some boards override the MMC pin muxing settings in order to enable the
pull-ups and change the drive strength to a value higher than the default.
While this was needed in the earlier days, this is now the default setting
for those pins, and therefore we don't need those board-specific settings
anymore.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Boards usually have an external pull-up on the card-detect signal, so
there's no need to add another one.
This also removes a DTC warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The gpio pinctrl nodes are redundant and as such useless most of the times.
Since they will also generate warnings in DTC, we can simply remove most of
them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
One of the usage of the LRADC is to implement buttons. The bindings define
that we should have one subnode per button, with their associated voltage
as a property.
However, there was no reg property but we still used the voltage associated
to the button as the unit-address, which eventually generated warnings in
DTC.
Rename the node names to avoid those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Our main node for all the in-SoC controllers used to have a unit name. The
unit-name, in addition to being actually false, would not match any reg
property, which generates a warning.
Remove it in order to remove those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Our oscillators clock names have a unit address, but no reg property, which
generates a warning in DTC. Change these names to remove those unit
addresses.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The simple-framebuffer nodes have a unit address, but no reg property which
generates a warning when compiling it with DTC.
Change the simple-framebuffer node names so that there is no warnings on
this anymore.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Using skeleton.dtsi will create a memory node that will generate a warning
in DTC. However, that node will be created by the bootloader, so we can
just remove it entirely in order to remove that warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The I2C's, MMC0 and MMC1 controllers have only one muxing option in the
SoC. In such a case, we can just move the muxing into the DTSI, and remove
it from the DTS.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
One of the usage of the LRADC is to implement buttons. The bindings define
that we should have one subnode per button, with their associated voltage
as a property.
However, there was no reg property but we still used the voltage associated
to the button as the unit-address, which eventually generated warnings in
DTC.
Rename the node names to avoid those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Some GPIO pinctrl nodes cannot be easily removed, because they would also
change the pin configuration, for example to add a pull resistor or change
the current delivered by the pin.
Those nodes still have underscores and unit-addresses in their node names
in our DTs, so adjust their name to remove the warnings. Use that occasion
to also fix some poorly chosen node-names.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
There's no phandle pointing to the CMA pool, so it's label is unnecessary.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The CMA node has a unit address, but no reg property which generates a
warning in DTC. Change the node name to reflect its usage and drop the unit
address.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Harmless mistake, but it's incorrect. The DT spec provides recommendations
for the node names:
"The name of a node should be somewhat generic, reflecting the function
of the device and not its precise programming model. If appropriate, the
name should be one of the following choices:
...
interrupt-controller"
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit adds QSPI flash support to the iwg23s board specific
device tree.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add QSPI[01] support to the RZ/G1C SoC specific device tree.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch enables cmt0 support on the iWave iwg23s sbc.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add CMT[01] support to r8a77470 SoC DT.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds USB DMAC nodes.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch enables watchdog support on the iWave iwg23s sbc.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds watchdog support to the r8a77470 SoC dtsi.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
[simon: moved node to preserve sort order]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Update the R-Mobile A1 (r8a7740), Emma Mobile EV2 (emev2) and
SH-Mobile AG5 (sh72a0) DTSI to include product name.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
[simon: squashed similar patches]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The LVDS0 encoder on Koelsh and Porter, and the LVDS1 encoder on Lager,
are enabled in DT but have no device connected to their output. This
result in spurious messages being printed to the kernel log such as
rcar-du feb00000.display: no connector for encoder /soc/lvds@feb90000, skipping
Fix it by disabling the encoders.
Fixes: 15a1ff30d8 ("ARM: dts: r8a7790: Convert to new LVDS DT bindings")
Fixes: e5c3f4707f ("ARM: dts: r8a7791: Convert to new LVDS DT bindings")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add uSD card and eMMC support to the iwg23s single board
computer powered by the RZ/G1C SoC (a.k.a. r8a77470).
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Althought interface SDHI1 found on the RZ/G1C SoC (a.k.a.
r8a77470) is compatible with the R-Car Gen3 ones, its OF
compatibility is restricted to the SoC specific compatible
string to avoid confusion, as from a more generic perspective
the RZ/G1C is sharing the most similarities with the R-Car
Gen2 family of SoCs, and there is a combination of R-Car
Gen2 compatible SDHI IPs and R-Car Gen3 compatible SDHI IP
on this specific chip.
This patch adds the SoC specific part of SDHI1 support, and
since SDHI1 comes with internal DMA, its DT node looks fairly
different from SDHI0 and SDHI2.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
RZ/G1C comes with two different types of IP for the SDHI
interfaces, SDHI0 and SDHI2 share the same IP type, and
such an IP is also compatible with the one found in R-Car
Gen2. SDHI1 IP on the other hand is compatible with R-Car
Gen3 with internal DMA.
This patch completes the SDHI support of the R-Car Gen2
compatible IPs, including fixing the max-frequency
definition of SDHI2, as it turns out there is a bug in
Section 1.3.9 of the RZ/G1C Hardware User's Manual (Rev.
1.00 Oct. 2017).
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add device tree nodes for the I2C[0123] controllers. Also, add
the aliases node.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This provides a pinctrl driver for the Renesas R9A06G032 SoC
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Our HDMI output endpoint on the A10s DTSI has a warning under DTC: "graph
node has single child node 'endpoint', #address-cells/#size-cells are not
necessary". Fix this by removing those properties.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
All our pinctrl nodes were using a node name convention with a unit-address
to differentiate the different muxing options. However, since those nodes
didn't have a reg property, they were generating warnings in DTC.
In order to accomodate for this, convert the old nodes to the syntax we've
been using for the new SoCs, including removing the letter suffix of the
node labels to the bank of those pins to make things more readable.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Boards usually have an external pull-up on the card-detect signal, so
there's no need to add another one.
This also removes a DTC warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The gpio pinctrl nodes are redundant and as such useless most of the times.
Since they will also generate warnings in DTC, we can simply remove most of
them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
One of the usage of the LRADC is to implement buttons. The bindings define
that we should have one subnode per button, with their associated voltage
as a property.
However, there was no reg property but we still used the voltage associated
to the button as the unit-address, which eventually generated warnings in
DTC.
Rename the node names to avoid those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The interrupt-parent property is set in sun5i.dtsi, so there's no need to
repeat it.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Our main node for all the in-SoC controllers used to have a unit name. The
unit-name, in addition to being actually false, would not match any reg
property, which generates a warning.
Remove it in order to remove those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Using skeleton.dtsi will create a memory node that will generate a warning
in DTC. However, that node will be created by the bootloader, so we can
just remove it entirely in order to remove that warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Our oscillators clock names have a unit address, but no reg property, which
generates a warning in DTC. Change these names to remove those unit
addresses.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
The simple-framebuffer nodes have a unit address, but no reg property which
generates a warning when compiling it with DTC.
Change the simple-framebuffer node names so that there is no warnings on
this anymore.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Our HDMI output endpoint on the A10 DTSI has a warning under DTC: "graph
node has single child node 'endpoint', #address-cells/#size-cells are not
necessary". Fix this by removing those properties.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Fix the 'unnecessary #address-cells/#size-cells without "ranges" or child
"reg" property' DTC warning for the gpio-keys DT node on A10 boards.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
firmware and VCHI driver to coordinate on using the correct cache line
size for the platform.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEE/JuuFDWp9/ZkuCBXtdYpNtH8nugFAlv9sgoACgkQtdYpNtH8
nuiXWhAArqokJBWAt2j3PzOD43i2WG1cJoPvrerUdk962fvzX3HlIOgptvWAWQ1f
drbfU+5TC8W5f6WVJaA4Xp2hHI778AyI2ij8TB4s5HJRUL+t6Znx53tkUuISswVp
/duV8wKZbdyg6iQv3ylv0wAvvVOh2927m6+CoU4Gf0IDr2Y4d/2riD8AbCB42pv5
LNOafJaYNJhPt2pkGgZ/8xvmBMXbJwP4F+GkyoqSW+02L/mua9JcZWoss+BNTIzb
6Qw46Rhp/bWzVjZaDJw1BzX8XLAL39xSJytUkTdQe9rVR/Nj8BiCNNEvwfi6Sbrx
mZl6mEYzv9coDffeoe1lK1qElcBIc98RzmGaEMduX4XKEnSkG7sPjkNqA5ghG8i4
QOH+sQo9WZAcZrD1oe1tp6Oc8RsSABvpKpuhGr2n5nyYqZ8wZwyM2nn9wcfpVWZU
MqcCag3wvf4LFVaSy/qFaV5f43/fp+Dw75Hx1UwkBP10snjWvZ6ytyRNXoniRIqS
boqGZ4kwhPxCRwFJY/di8P356WNrMQzaCuyEB0c4xfBYHzE9MUMuYn8uWUiaYuyh
Wc4/PFQzb2jO5ZIt/PuSHNFoEyQndcF6gUE9v2yyyseu/dvJqqDNSl2VyjdVbGL/
aMTfFCNcwM8wEUyFHRbI0x69FA1KRmI4Ic18agIS2OsMYoJ8NV0=
=BEZr
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAlv90pcACgkQh9CWnEQH
BwRoyQ//Wy0AjmVf3inDdvtCI4oOnUG/I1bTXQJLachpHmUId4jYIs1TsOrs4CeF
jMLj7QskySXYfPyglL2LQD03VydArKv26tQup3UHI7RgTphma5r/4q+/jX3KO0Ak
FgW0OfN6JU4PQz1yC4qOHYdvxv+36FiZFjACFS4PDLiXkdvUtipBnDYxsZi9F0Oj
Ut4q5lFumZBuc9JUGcW47N1F43ezV+D2HcyaeaQmPTxlvN7Ax3CcvWEDPEreICvr
hCGBguVB5c2qmDzyKg66TPP3kZ7vfSR2Q8oLezLVYzXPfJ+XMorIEgfaxCJbz+a8
ef6tjJiILdXARSdGenrgK+oUElVpQtBszjSwe7+ptZyKwKr3+p61J89pLQuLHSXT
u9bilEqbaNuN8iS939XCvkdl8F/T2/jNBKB0JCUDaXE7wwpHucIuIxeeCL1Dhs5J
IeYriOHyLYPsuuvr8vXe3C14Ej5fs6OXJdtYkGEYUH6VWoH4Yxa3MaqjyX6BE6oO
gwUCaJM2jkpSyEXWxu2tQ015tKlw0A0wMFKseIoe+jPGcnihC9XWfRaeOny1TgTa
J5mQL9pQntL++LCMYiXgZZU/Ff5dHBQU/yMJWfG8glS74RqJfDyrt1IBNb/199yC
6+ONHv0mtGH3ttKO8vxJUP2dlhirjvuDvDxsidgLxvnDhMmsRpQ=
=zY4r
-----END PGP SIGNATURE-----
Merge tag 'tags/bcm2835-dt-next-2018-11-27' into devicetree/next
This pull request adds a compatible string to the DT necessary for the
firmware and VCHI driver to coordinate on using the correct cache line
size for the platform.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The H3 and H5 features the same CSI controller that was initially found on
the A31.
Add a DT node for it.
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
cpu0-supply in cpu0 is deprecated, instead each cpu-core is supposed to
list its supply separately. With the added cpu core phandles, update
existing rk3188 boards accordingly.
Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
The fact that OPPs specified only on cpu0 work is Linux specific and
normally cpu frequencies should be specified for each cpu core.
To facilitate this without needing to duplicate the frequency table
each time, convert to opp-v2 before adding references to all cores.
Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
The Rockchip i2s always just requires a sound-dail-cells value of 0,
so add them to the core soc dtsi for convenience.
Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
The lradc's analog reference voltage is set to 3.0 volt in the
hardware. This is more or less set in copper for at least lradc0. Set the
property in the dts to ensure the lradc is referenced properly.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Pass the 'dmas' property to the UART ports so that DMA can
be supported.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
It is not correct to assign the 24MHz clock oscillator to the GPIO
ports.
Fix it by assigning the proper GPIO clocks instead.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
According to the Rockchip vendor tree the PMU interrupt number is
76, so fix it accordingly.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since firmware does not initialize any of the generic timer CPU
registers pass the 'arm,cpu-registers-not-fw-configured' property as
suggested in Documentation/devicetree/bindings/timer/arm,arch_timer.txt.
This also aligns with other Rockchip SoC dtsi files.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Like it is done on cpu nodes of other Rockchip SoCs, pass the
'clock-latency' property to the CPU node, so that cpufreq driver
can take the latency into account when switching frequencies.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the pin settings for the emmc pins so they can be used across multiple
boards.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
DWC2 hardware module integrated in Samsung SoCs requires some quirks to
operate properly, so use Samsung SoC specific compatible to notify driver
to apply respective fixes.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The T3/R40/V40 using the same sdk and config file in allwinner
sdk, it seem they are the same SOC just with different name, so
compatible with R40.
The t3-cqa3t-bv3 based on Allwinner T3 SoC, it has various connectors,
leds, buttons, and sell on:
https://item.taobao.com/item.htm?spm=2013.1.w4023-4203040713.25.62704cce7UCgLS&id=557154455330
It features:
- X-Powers AXP221s PMIC connected to i2c0
- 1/2 GB DDR3 DRAM
- 8 GB eMMC
- 2x USB 2.0 hosts
- 1x USB 2.0 OTG
- 2 LVDS connectors
- 24 bit RGB LCD connector
- HDMI output
- DVP camera interface (support 500w cmos camera)
- GPIO connectors
- 5 TTL uarts and 2 RS232 uarts
- 1 RS485 connector
- support i2c capacitive tp and usb infrared tp
- boot control, reset and user buttons
- 3.5mm headphone and 3.5mm mic jack
- 100M RJ45
- micro SD card slot
- DC power jack
- RCT power slot
- 1 CVBS TVIN
- 1 CVBS TVOUT
- 2 customer leds
- 1 buzzer
- 1 minipcie
- I2C output
- SPI output
- PCM output
- wifi and bt connector reserved.
Board info can find here:
https://github.com/Axl-zhang/Allwinner-V40-T3-R40-manual
Signed-off-by: Hao Zhang <hao5781286@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The pwm-backlight driver initializes BLON (the enable gpio) to
output-high if the gpio is input on probe. Initializing the gpio
to output-low before the driver probes prevents this action by
the pwm-backlight driver and gets rid of a nasty blink of full
backlight with an uninitialized panel.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two
different clocks for the peripherals in the SoC. The Static Memory
controller is connected to the divided master clock.
Unfortunately, the device tree does not correctly show this and uses the
master clock directly. This clock is then used by the code for the NAND
controller to calculate the timings for the controller, and we end up with
slow NAND Flash access.
Fix the device tree, and the performance of Flash access is improved.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Add sleep state for beeper pins. Without this there was a power
increase during the suspend and standby states on V3_3D domain.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add pinctrl settings so that gpio0 wake from suspend will be supported
using buttons SW4 and SW7. Also, add pinctrl configuration for 0x954,
spi0_d0, which is an unused pin brought out to a header on the board
that in it's default state also connects to the gpio used for wakeup,
gpio0_3, which affects the state of the pin and prevents a working
wakeup unless we set the mux to a different state.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently uart0 uses pinctrl config set by bootloader so
create default state that can be restored after a suspend
event.
Also, modify uart0 pinctrl to include RTS and CTS pins as by
default these are not in a mode for optimal power savings.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The pins used by debugss are not configued by default, place pulldowns
on the pins for maximum power savings during sleep.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
There are several pins on this EVM that are not in use but they can
still draw power if misconfigured. Create a pinctrl entry for these pins
and configure each one for optimal power savings.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add pinctrl data for ddr_vtt_toggle pin so that it is configured
for proper state during DeepSleep0. The pin should enter DS0 off mode
and hold the line low so VTT regulator is kept off while suspended.
It is also important for the PULLUP to be set on this pin so that
on removal of isolation, the VTT line is pulled high as a requirement
for bringing the DDR3 out of self-refresh.
This toggling is dependent on the IO isolation controlled by the
wkup_m3. Without placing the IOs into isolation the DS0 states set for
the pin will not be latched into effect during suspend.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As long as the kernel cmdline has "earlycon" in it, this allows
seeing debug messages earlier and does not require DEBUG_LL to
be enabled.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The EEPROM under I2C2 was put by mistake in the dts.
Remove it as it is not really present on the real hardware.
Fixes: ceef0396f3 ("ARM: dts: imx: add ZII RDU1 board")
Reported-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Coreboot version on veyron ChromeOS devices seems to ignore
memory@0 nodes when updating the available memory and instead
inserts another memory node without the address.
This leads to 4GB systems only ever be using 2GB as the memory@0
node takes precedence. So remove the @0 for veyron devices.
Fixes: 0b639b815f ("ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards")
Cc: stable@vger.kernel.org
Reported-by: Heikki Lindholm <holin@iki.fi>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
There are two common DTSI files for Exynos5422 Odroid XU3 family of
boards. One is shared between all of them (XU3, XU3-Lite, XU4 and HC1)
and the second skips HC1. Document this in the files.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This allows a board to specify a custom thermal zone configuration
involving the SoC internal sensor, CPU and GPU nodes without having
to change those nodes.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Use the correct compatible for the new protocol used by the firmware
on the touch controller, the GPIO wakeup isn't used in that case.
Also eGalax touch needs axis swapping, just as with the RMI4 touch.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch corrects indentation problems in the gpmigrp and i2c1grp nodes.
Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The wireless variants of the ConnecCore 6UL SOM include a Qualcomm
QCA6564 wireless chip with dual WiFi and Bluetooth.
Both the ConnectCore 6UL SBC Express and Pro boards fit a wireless SOM.
The Wifi is connected through the SDIO interface on usdhc1 and the
Bluetooth is connected via uart1.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the status property disable the PCIe, the property will be enable
by bootloader.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Leave b{4,6}50v3 GPIO expander pca953x pins P05,P10,P11 unconfigured as
they are now used to implement an additional watchdog mechanism in user
space. P10,P11 pins remain unused (and therefore hogged) on b850v3.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Support for this board is currently very limited. To debug any potential
issues on this board the "earlycon" kernel parameter can be used (without
any arguments). However, this requires the board to define a
/chosen/stdout-path property in it's .dts.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Support for this board is currently very limited. To debug any potential
issues on this board the "earlycon" kernel parameter can be used (without
any arguments). However, this requires the board to define a
/chosen/stdout-path property in it's .dts.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Support for Meson6 SoCs is currently very limited. It's often unclear
why such a device does not boot. To debug this the "earlycon" kernel
parameter can be used (without any arguments). However, this requires
the board to define a /chosen/stdout-path property in it's .dts.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
There is no functional change from this, but it is confusing to find two
copies of vcc_sys and no vcc_flash when looking in
/sys/class/regulator/*/name.
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This new property allows the number of sensors to be configured from DT
instead of being hardcoded in platform data. Use it.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
We've earlier added support to split the register address space into TM
and SROT regions. Split up the regmap address space into two for msm8974
that has a similar register layout.
Since tsens-common.c/init_common() currently only registers one address
space, the order is important (TM before SROT). This is OK since the
code doesn't really use the SROT functionality yet.
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Since commit d7c5f68635 ("ARM: dts: sun8i: a83t: bananapi-m3: Add
AXP813 regulator nodes") my BPIM3 no longer works at gigabit speed.
With the default setting, dldo3 is regulated at 2.9v which seems
sufficient for the PHY but the aforementioned commit drops it to 2.5V
which is insufficient. Note that this behaviour is random for all BPIM3.
Some work with 2.5V, but some don't.
Finnaly, someone from Bananapi confirmed that this regulator must be set
to 3.3V.
Fixes: d7c5f68635 ("ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813
regulator nodes")
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
[wens@csie.org: Reworked commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The i.MX25 contains two EPIT (Enhanced Periodic Interrupt Timer)
function blocks. Add their ipg and per clocks to the device tree.
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Acked-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add SD card write-protect pin configuration to be sure that it will be
properly pulled down to indicate write access.
Suggested-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Set the eMMC max-frequency to 200MHz for optimal performance on Odroid
XU3/XU4 family of boards.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Set the SD max-frequency to 200MHz for optimal performance on Odroid
XU3/XU4/HC1 family of boards.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
From Odroid XU3/XU4/HC1 schematics the LDO13 regulator for SD2, can be
set on 1.8V or 2.8V so the minimal value should be fixed to 1.8V. This
is necessary to support UHS-I tuning (otherwise card won't be detected
during boot).
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Add support for UHS-I bus speed tuning for SDR50, DDR50 and SDR104 to
Odroid XU3/XU4/HC1 family boards.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Add missing clocks to SoC build-in RTC device to make it fully
operational on Exynos5250-based Arndale board.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The bindings for s2mps11/s5m8767 clocks driver require a compatible for
clocks node. Parent MFD sec-core driver will also use it when
instantiating children.
The compatible is not needed for proper working because device will be
anyway created by parent MFD device. Add it for correctness.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The bindings for s2mps11/s5m8767 clocks driver require a compatible for
clocks node. Parent MFD sec-core driver will also use it when
instantiating children.
The compatible is not needed for proper working because device will be
anyway created by parent MFD device. Add it for correctness.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Similar to commit 8f42cb7f64 ("ARM: dts: omap4: Add l4 interconnect
hierarchy and ti-sysc data"), let's add proper interconnect hierarchy
for l4 interconnect instances with the related ti-sysc interconnect
module data as in Documentation/devicetree/bindings/bus/ti-sysc.txt.
Using ti-sysc driver binding allows us to start dropping legacy platform
data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of
ti-sysc dts data.
This data is generated based on platform data from a booted system
and the interconnect acces protection registers for ranges. To avoid
regressions, we initially validate the device tree provided data
against the existing platform data on boot.
Cc: devicetree@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
At the same time the AM3517 EVM was gaining WiFi support,
separate patches were introduced to move the interrupt
from HIGH to RISING. Because they overlapped, this was not
done to the AM3517-EVM. This patch fixes Kernel 4.19+
Fixes: 6bf5e3410f ("ARM: dts: am3517-som: Add WL127x Wifi")
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The interrupt on mmc3_dat1 is wrong which prevents this from
appearing in /proc/interrupts.
Fixes: ab8dd3aed0 ("ARM: DTS: Add minimal Support for Logic PD
DM3730 SOM-LV") #Kernel 4.9+
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
When the Torpedo was first introduced back at Kernel 4.2,
the interrupt extended flag has been set incorrectly.
It was subsequently moved, so this patch corrects Kernel
4.18+
Fixes: a388673052 ("ARM: dts: Move move WiFi bindings to
logicpd-torpedo-37xx-devkit") # v4.18+
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The MMC1 is active low, not active high. For some reason,
this worked with different combination of U-Boot and kernels,
but it's supposed to be active low and is currently broken.
Fixes: cfaa856a25 ("ARM: dts: am3517: Add pinmuxing, CD and
WP for MMC1") #kernel 4.18+
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The size field in a Device Tree "reg" property is encoded in bytes, not
words.
Fixes: 614fa22119 ("ARM: dts: bcm2835: Add VCHIQ node to the Raspberry Pi boards. (v3)")
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
To allow VCHIQ to determine the correct cache line size, use the new
"brcm,bcm2836-vchiq" compatible string on BCM2836 and BCM2837.
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
All boards replicate the aliases node, move the aliases node to
bcm-nsp.dtsi and add all the serial and ethernet ports such that a boot
program like u-boot can populate MAC addresses accordingly.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This matches licensing used by most of BCM5301X files and is preferred as:
1) GPL 2.0+ makes it clearly compatible with Linux kernel
2) MIT is also permissive but preferred over ISC
This file has been developed by me & once modified by Rob dropping a
single leading zero in an UART address.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The Broadcom BCM963138DVT board has an eSATA port which is fully
functional, turn on the AHCI controller and the companion SATA PHY.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This matches licensing used by most of BCM5301X files and is preferred as:
1) GPL 2.0+ makes it clearly compatible with Linux kernel
2) MIT is also permissive but preferred over ISC
This file was fully developed by me.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This matches licensing used by other BCM5301X files and is preferred as:
1) GPL 2.0+ makes it clearly compatible with Linux kernel
2) MIT is also permissive but preferred over ISC
This file has been developed by me & once modified by Vivek.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Vivek Unune <npcomplete13@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This matches licensing used by other BCM5301X files and is preferred as:
1) GPL 2.0+ makes it clearly compatible with Linux kernel
2) MIT is also permissive but preferred over ISC
Both files were fully developed by me. Commits touching them were signed
by Florian and Hauke due to submitting process only.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The Mapleboard MP130 is a single board computer based on the Allwinner
H3 SoC, with all schematics freely available. The Lite version includes
1GB main memory and 8GB eMMC.
https://www.mapleboard.org/en (still mostly in Chinese even when English
is selected)
This DTS is based upon the DTS shipped with the board which uses
mapleboard,mp130- prefixes instead of the allwinner,sun8i variants.
v2: Fold in review comments from Maxime Ripard
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
QoS nodes keep information about priorites etc on the interconnect
and loose state when the power-domain gets disabled. Therefore the
power-domain driver stores the settings of available qos nodes and
restores them when the power-domain gets enabled again.
So add the qos nodes found on the Cortex-A9 socs from Rockchip, so
that they can then be connected to the power-domains.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Orange Pi Plus board lacks voltage scaling capabilities in its
current form. This results in random freezes during boot when cpufreq is
enabled, probably due to wrong voltages.
This patch (more or less copy/paste from 06139c) does the following
things on this board:
- enable r_i2c
- add sy8106a to the r_i2c bus
- have the sy8106a regulate VDD of cpu
Since the Orange Pi Plus has the same PMU setup as the Orange Pi PC, I
simply took min/max/fixed/ramp from the latter DTS. In that file the
origin of the values are described by the following comment:
"The datasheet uses 1.1V as the minimum value of VDD-CPUX,
however both the Armbian DVFS table and the official one
have operating points with voltage under 1.1V, and both
DVFS table are known to work properly at the lowest
operating point.
Use 1.0V as the minimum voltage instead."
I have tested this on patch two Orange Pi Plus boards, by running a
kernel with this patch and do intermettent runs of cpuburn while
monitoring voltage, frequency and temperature. The board runs stable
across its operatiing points while showing a reasonable (< 40C)
temperature. My Orange Pi PC, when put to the same test, yields similar
stable results.
Signed-off-by: Jorik Jonker <jorik@kippendief.biz>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The actual hardware has 4 data lines. Use them.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Drop reg property from fixed regulator and remove the unncessary bus
node.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This would help us to get early boot logs by passing "earlycon" to
kernel bootargs.
Further, by adding this we don't have to depend on complex earlyprintk
configs for early boot logs.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The DCP block on 6ull has no major differences other than requiring
explicit clock enabling.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit adds DTS support for BK4 device from Liebherr. It
uses vf610 SoC from NXP.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add Pincfgs for UART4 to enable Communication with the onboard SAM3X
Signed-off-by: Markus Kueffner <kueffner.markus@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for the ZII SCU 4 board, which has lots of switches and
SFF ports.
Based on the work from Andrew Lunn.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Bindings for "fixed-regulator" only explicitly support "gpio" property,
not "gpios". Fix by correcting the property name.
The enet PHYs on imx6sx-sdb needs to be explicitly reset after a power
cycle, this can be handled by the phy-reset-gpios property. Sadly this
is not handled on suspend: the fec driver turns phy-supply off but
doesn't assert phy-reset-gpios again on resume.
Since additional phy-level work is required to support powering off the
phy in suspend fix the problem by just marking the regulator as
"boot-on" "always-on" so that it's never turned off. This behavior is
equivalent to older releases.
Keep the phy-reset-gpios property on fec anyway because it is a correct
description of board design.
This issue was exposed by commit efdfeb079c ("regulator: fixed:
Convert to use GPIO descriptor only") which causes the "gpios" property
to also be parsed. Before that commit the "gpios" property had no
effect, PHY reset was only handled in the the bootloader.
This fixes linux-next boot failures previously reported here:
https://lore.kernel.org/patchwork/patch/982437/#1177900https://lore.kernel.org/patchwork/patch/994091/#1178304
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
A quoted label reference doesn't expand to the node path and is taken as
a literal string. Dropping the quotes can fix this unless the baudrate
string is appended in which case we have to use the alias.
At least on VF610, the problem was masked by setting the console in
bootargs. Use the alias syntax with baudrate parameter so we can drop
setting the console in bootargs.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fix the type of compatible string "fs,imx6sll-i2c" which should be
"fsl,imx6sll-i2c".
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Remove unused parameter from HASH1 dmas property on stm32mp157c SoC.
Fixes: 1e726a40e0 ("ARM: dts: stm32: Add HASH support on stm32mp157c")
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
[Olof: Bug doesn't cause any harm, so shouldn't need stable backport]
Signed-off-by: Olof Johansson <olof@lixom.net>
There are close to 800 indivudal changesets in this branch again, which
feels like a lot. There are particularly many changes for the NVIDIA
Tegra platform this time, in fact more than it has seen in the two years
since the v4.9 merge window. Aside from this, it's been fairly normal,
with lots of changes going into Renesas R-CAR, NXP i.MX, Allwinner Sunxi,
Samsung Exynos, and TI OMAP.
Most of the changes are for adding new features into existing boards,
for brevity I'm only mentioning completely new machines and SoCs here.
For the first time I think we have (slightly) more new 64-bit hardware
than 32-bit:
Two boards get added for TI OMAP: Moxa UC-2101 is an industrial
computer, see https://www.moxa.com/product/UC-2100.htm; GTA04A5
is a minor variation of the motherboards of the GTA04 phone, see
https://shop.goldelico.com/wiki.php?page=GTA04A5
Clearfog is a nice little board for quad-core
Marvell Armada 8040 network processor, see
https://www.solid-run.com/marvell-armada-family/clearfog-gt-8k/
Two additional server boards come with the Aspeed baseboard management
controllers: Stardragon4800 is an arm64 reference platform made by HXT
(based on Qualcomm's server chips), and TiogaPass is an Open Compute
mainboard with x86 CPUs. Both use the ARM11 based AST2500 chips in
the BMC.
NXP i.MX usually sees a lot of new boards each release. This time there
we only add one minor variant: ConnectCore 6UL SBC Pro uses the same
SoM design as the ConnectCore 6UL SBC Express added later. However,
there is a new chip, the i.MX6ULZ, which is an even smaller variant
of the i.MX6ULL, with features removed. There is also support for the
reference board design, the i.MX6ULZ 14x14 EVK.
A new Raspberry Pi variant gets added, this one is the CM3 compute module
based on bcm2837, it was launched in early 2017 but only now added to
the kernel, both as 32-bit and as 64-bit files, as we tend to do for
Raspberry Pi.
On the Allwinner side, everything is again about cheap development
boards, usually of the "Fruit Pi" variety. The new ones this time
are:
Orange Pi Zero Plus2: http://www.orangepi.org/OrangePiZeroPlus2/
Orange Pi One Plus: http://www.orangepi.org/OrangePiOneplus/
Pine64 LTS: https://www.pine64.org/?product=pine-a64-lts
Banana Pi M2+ H5: http://www.banana-pi.org/m2plus.html
The last one of these is now a 64-bit version of the earlier Banana
Pi M2+ H3, with the same board layout.
Similarly, for Rockchips, get get another variant of the 32-bit
Asus Tinker board, the model 'S' based on rk3288, and three now
boards based on the popular RK3399 chip:
ROC-RK3399-PC: https://libre.computer/products/boards/roc-rk3399-pc/
Rock960: https://www.96boards.org/product/rock960/
RockPro64: https://www.pine64.org/?page_id=61454
These are all quite powerful boards with lots of RAM and I/O, and
the RK3399 is the same chip used in several Chromebooks. Finally,
we get support for the PX30 (aka rk3326) chip, which is based on the
low-end 64-bit Cortex-A35 CPU core. So far, only the evaluation board
is supported.
One more Banana Pi is added with a Mediatek chip: Banana Pi R64 is based
on the MT7622 WiFi router platform, and the first product I've seen with
a 64-bit Mediatek chip in that market: http://www.banana-pi.org/r64.html
For HiSilicon, we gain support for the Hi3670 SoC and HiKey 370
development board, which are similar to the Hi3660 and Hikey 360
respectively, but add support for an NPU.
Amlogic gets initial support for the Meson-G12A chip (S905D2),
another quad-core Cortex-A53 SoC, and its evaluation platform.
On the 32-bit side, we gain support for an actual end-user product,
the Endless Computers Endless Mini based on Meson8b (S805), see
https://endlessos.com/computers/
Qualcomm adds support for their MSM8998 SoC and evaluation platform. This
chip is commonly known as the Snapdragon 835, and is used in high-end
phones as well as low-end laptops.
For Renesas, a very bare support for the r8a774a1 (RZ/G2M) is added,
but no boards for this one. However, we do add boards for the previously
added r8a77965 (R-Car M3-N): the M3NULCB Kingfisher and the M3NULCB
Starter Kit Pro.
While we have lots of DT changes for NVIDIA to update the existing files,
the only board that gets added is the Toradex Colibri T20 on Colibri
Evaluation Board for the old Tegra2.
Synaptics add support for their AS370 SoC, which is part of the (formerly
Marvell) Berlin line of set-top-box chips used e.g. in the various Google
Chromecast. Only the .dtsi gets added at this point, no actual machines.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJb1224AAoJEGCrR//JCVIn9uYP/jLMoGkVQRS5L9sRjOci1l5b
EHl8veJ+uNJaTStp5XAZk90MoBcSdXtnISSEiR7a3qKJw1mYfgAWyPtQCttRFUCo
rDp4GJpJ96TBg1tyt5Lop3V9eIYbCh9epf2foKTTdpRiX022AFk1031jvnh2Teuy
fKA2VNeoyyOZqxh0ysJq7G8kWt8PTQTKXDebYPWEbsu0AFmqQ84lz7oGNdPk0GPm
krtQIO6rh+sJR/8wWGYfnTYAIOk6jNrPhiyjEcyu+x2525rwKxJNKVY8P9PuNhrl
hzqld1dPtb3gfdcxWxZUznHmVUGkVEIa1QNC6csSmLzuxqJJE0/J5u2P8lIfrhVI
c5C8r3eaTxFM0s5uKhNhhewlJ6uiDhUQy13AG0JXteujP23BGObYstnV10pJrH75
xq7uSUiU04v95MocPjodJ2I7dIlAoFCd6ELnsmD/mz743gY9AZ6DHaOBMMwIzK3H
EQifF5E/4PWOjBx7fonumBm0LebPjWGmv4CNyCK5Q93ylK7U/kFDdjiNjNhyks5E
CVQBFhA7sshKJQRDOiaofMxOfKJHeKGU2PR7yGRpT3YWQD/apIL/elG4qUNjLX46
2Dwdgq8nDdbY2SzPwwy7ncTtyDRYcsFCtScT5slu1I1UxIhwEYJurzCKDM4jJNZb
Cg2D7a+AlZ8N5Vsr1ldV
=yaED
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree updates from Arnd Bergmann:
"There are close to 800 indivudal changesets in this branch again,
which feels like a lot. There are particularly many changes for the
NVIDIA Tegra platform this time, in fact more than it has seen in the
two years since the v4.9 merge window. Aside from this, it's been
fairly normal, with lots of changes going into Renesas R-CAR, NXP
i.MX, Allwinner Sunxi, Samsung Exynos, and TI OMAP.
Most of the changes are for adding new features into existing boards,
for brevity I'm only mentioning completely new machines and SoCs here.
For the first time I think we have (slightly) more new 64-bit hardware
than 32-bit:
Two boards get added for TI OMAP: Moxa UC-2101 is an industrial
computer, see https://www.moxa.com/product/UC-2100.htm; GTA04A5 is a
minor variation of the motherboards of the GTA04 phone, see
https://shop.goldelico.com/wiki.php?page=GTA04A5
Clearfog is a nice little board for quad-core Marvell Armada 8040
network processor, see
https://www.solid-run.com/marvell-armada-family/clearfog-gt-8k/
Two additional server boards come with the Aspeed baseboard management
controllers: Stardragon4800 is an arm64 reference platform made by HXT
(based on Qualcomm's server chips), and TiogaPass is an Open Compute
mainboard with x86 CPUs. Both use the ARM11 based AST2500 chips in the
BMC.
NXP i.MX usually sees a lot of new boards each release. This time
there we only add one minor variant: ConnectCore 6UL SBC Pro uses the
same SoM design as the ConnectCore 6UL SBC Express added later.
However, there is a new chip, the i.MX6ULZ, which is an even smaller
variant of the i.MX6ULL, with features removed. There is also support
for the reference board design, the i.MX6ULZ 14x14 EVK.
A new Raspberry Pi variant gets added, this one is the CM3 compute
module based on bcm2837, it was launched in early 2017 but only now
added to the kernel, both as 32-bit and as 64-bit files, as we tend to
do for Raspberry Pi.
On the Allwinner side, everything is again about cheap development
boards, usually of the "Fruit Pi" variety. The new ones this time are:
- Orange Pi Zero Plus2: http://www.orangepi.org/OrangePiZeroPlus2/
- Orange Pi One Plus: http://www.orangepi.org/OrangePiOneplus/
- Pine64 LTS: https://www.pine64.org/?product=pine-a64-lts
- Banana Pi M2+ H5: http://www.banana-pi.org/m2plus.html
The last one of these is now a 64-bit version of the earlier Banana Pi
M2+ H3, with the same board layout.
Similarly, for Rockchips, get get another variant of the 32-bit Asus
Tinker board, the model 'S' based on rk3288, and three now boards
based on the popular RK3399 chip:
- ROC-RK3399-PC: https://libre.computer/products/boards/roc-rk3399-pc/
- Rock960: https://www.96boards.org/product/rock960/
- RockPro64: https://www.pine64.org/?page_id=61454
These are all quite powerful boards with lots of RAM and I/O, and the
RK3399 is the same chip used in several Chromebooks. Finally, we get
support for the PX30 (aka rk3326) chip, which is based on the low-end
64-bit Cortex-A35 CPU core. So far, only the evaluation board is
supported.
One more Banana Pi is added with a Mediatek chip: Banana Pi R64 is
based on the MT7622 WiFi router platform, and the first product I've
seen with a 64-bit Mediatek chip in that market:
http://www.banana-pi.org/r64.html
For HiSilicon, we gain support for the Hi3670 SoC and HiKey 370
development board, which are similar to the Hi3660 and Hikey 360
respectively, but add support for an NPU.
Amlogic gets initial support for the Meson-G12A chip (S905D2), another
quad-core Cortex-A53 SoC, and its evaluation platform. On the 32-bit
side, we gain support for an actual end-user product, the Endless
Computers Endless Mini based on Meson8b (S805), see
https://endlessos.com/computers/
Qualcomm adds support for their MSM8998 SoC and evaluation platform.
This chip is commonly known as the Snapdragon 835, and is used in
high-end phones as well as low-end laptops.
For Renesas, a very bare support for the r8a774a1 (RZ/G2M) is added,
but no boards for this one. However, we do add boards for the
previously added r8a77965 (R-Car M3-N): the M3NULCB Kingfisher and the
M3NULCB Starter Kit Pro.
While we have lots of DT changes for NVIDIA to update the existing
files, the only board that gets added is the Toradex Colibri T20 on
Colibri Evaluation Board for the old Tegra2.
Synaptics add support for their AS370 SoC, which is part of the
(formerly Marvell) Berlin line of set-top-box chips used e.g. in the
various Google Chromecast. Only the .dtsi gets added at this point, no
actual machines"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (721 commits)
ARM: dts: socfgpa: remove ethernet aliases from dtsi
arm64: dts: stratix10: add ethernet aliases
dt-bindings: mediatek: Add bindig for MT7623 IOMMU and SMI
dt-bindings: mediatek: Add JPEG Decoder binding for MT7623
dt-bindings: iommu: mediatek: Add binding for MT7623
dt-bindings: clock: mediatek: add support for MT7623
ARM: dts: mvebu: armada-385-db-88f6820-amc: auto-detect nand ECC properites
ARM: dts: da850-lego-ev3: slow down A/DC as much as possible
ARM: dts: da850-evm: Enable tca6416 on baseboard
arm64: dts: uniphier: Add USB2 PHY nodes
arm64: dts: uniphier: Add USB3 controller nodes
ARM: dts: uniphier: Add USB2 PHY nodes
ARM: dts: uniphier: Add USB3 controller nodes
arm64: dts: meson-axg: s400: disable emmc
arm64: dts: meson-axg: s400: add missing emmc pwrseq
arm64: dts: clearfog-gt-8k: add PCIe slot description
ARM: dts: at91: sama5d4_xplained: even nand memory partitions
ARM: dts: at91: sama5d3_xplained: even nand memory partitions
ARM: dts: at91: at91sam9x5cm: even nand memory partitions
ARM: dts: at91: sama5d2_ptc_ek: fix bootloader env offsets
...
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJb12wyAAoJEAhfPr2O5OEVQG4P/3QlXjec6qlhbo6UPs54E2sC
bVdZfp3mobo8NmLRt791Yh9cc0rN45Tlf2BT8XEmCyI6+NB++obU/j0LW5XT7sp7
oE8IgeRraVFWH/Xl9lTgP15Cs6v43eyvP12xgRWBmr+TYugLHDVTheGBvU/COb3d
yaykUULezuOMLA3HsPbz5EJOmU5rZ/Wa1w1sAiNJY/cRohfVb3kO4593enwUTMSx
yHJ+AVjl/Dn3RV4yLwoybpxPH6XIb3KoLg/6Fx8bOlKy1sg0mcWpzQ1CvMUNpXTF
kdwTw3ri1bfYnjChZewuKoJU8Wcw0Gt7pkqAhULN1ieo84MNA3bNor56pdRPaOZW
KxzlXZRS6xgYW8bzZ51N0Ku6fwSt3AWRE7TeKcrHF84Yb8vOtPS15sp3qc+9o9rb
EDV/lJLcz4bbi3W28di5WMFaN7LHxCHnRV7GvrcNQm6Im62CBFZHiI7jKjMv3tXp
Taes0utMPGfWuY6fv4LmuBzFG4nGB6/H4RiVvL1cLkjnx/FJtWGH+1uOcKDraKeI
ENBrK0VYrNH7nCDGNehiamStcVK+27tS+xsuqoZkGz6RA8vAxYBXTIZULXA98BPA
f6NC32ZNJaruxh4qh5tUy+LKPGzXs0sWa9kfgKmFfaOndFLMjGTXHpAT5AYJMbNe
iqKi/4aXD4aKAWTA7PPg
=Cc6D
-----END PGP SIGNATURE-----
Merge tag 'media/v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab:
- new dvb frontend driver: lnbh29
- new sensor drivers: imx319 and imx 355
- some old soc_camera driver renames to avoid conflict with new
drivers
- new i.MX Pixel Pipeline (PXP) mem-to-mem platform driver
- a new V4L2 frontend for the FWHT codec
- several other improvements, bug fixes, code cleanups, etc
* tag 'media/v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (289 commits)
media: rename soc_camera I2C drivers
media: cec: forgot to cancel delayed work
media: vivid: Support 480p for webcam capture
media: v4l2-tpg: fix kernel oops when enabling HFLIP and OSD
media: vivid: Add 16-bit bayer to format list
media: v4l2-tpg-core: Add 16-bit bayer
media: pvrusb2: replace `printk` with `pr_*`
media: venus: vdec: fix decoded data size
media: cx231xx: fix potential sign-extension overflow on large shift
media: dt-bindings: media: rcar_vin: add device tree support for r8a7744
media: isif: fix a NULL pointer dereference bug
media: exynos4-is: make const array config_ids static
media: cx23885: make const array addr_list static
media: ivtv: make const array addr_list static
media: bttv-input: make const array addr_list static
media: cx18: Don't check for address of video_dev
media: dw9807-vcm: Fix probe error handling
media: dw9714: Remove useless error message
media: dw9714: Fix error handling in probe function
media: cec: name for RC passthrough device does not need 'RC for'
...
-----BEGIN PGP SIGNATURE-----
iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAlvPV7IUHGJoZWxnYWFz
QGdvb2dsZS5jb20ACgkQWYigwDrT+vyaUg//WnCaRIu2oKOp8c/bplZJDW5eT10d
oYAN9qeyptU9RYrg4KBNbZL9UKGFTk3AoN5AUjrk8njxc/dY2ra/79esOvZyyYQy
qLXBvrXKg3yZnlNlnyBneGSnUVwv/kl2hZS+kmYby2YOa8AH/mhU0FIFvsnfRK2I
XvwABFm2ZYvXCqh3e5HXaHhOsR88NQ9In0AXVC7zHGqv1r/bMVn2YzPZHL/zzMrF
mS79tdBTH+shSvchH9zvfgIs+UEKvvjEJsG2liwMkcQaV41i5dZjSKTdJ3EaD/Y2
BreLxXRnRYGUkBqfcon16Yx+P6VCefDRLa+RhwYO3dxFF2N4ZpblbkIdBATwKLjL
npiGc6R8yFjTmZU0/7olMyMCm7igIBmDvWPcsKEE8R4PezwoQv6YKHBMwEaflIbl
Rv4IUqjJzmQPaA0KkRoAVgAKHxldaNqno/6G1FR2gwz+fr68p5WSYFlQ3axhvTjc
bBMJpB/fbp9WmpGJieTt6iMOI6V1pnCVjibM5ZON59WCFfytHGGpbYW05gtZEod4
d/3yRuU53JRSj3jQAQuF1B6qYhyxvv5YEtAQqIFeHaPZ67nL6agw09hE+TlXjWbE
rTQRShflQ+ydnzIfKicFgy6/53D5hq7iH2l7HwJVXbXRQ104T5DB/XHUUTr+UWQn
/Nkhov32/n6GjxQ=
=58I4
-----END PGP SIGNATURE-----
Merge tag 'pci-v4.20-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
- Fix ASPM link_state teardown on removal (Lukas Wunner)
- Fix misleading _OSC ASPM message (Sinan Kaya)
- Make _OSC optional for PCI (Sinan Kaya)
- Don't initialize ASPM link state when ACPI_FADT_NO_ASPM is set
(Patrick Talbert)
- Remove x86 and arm64 node-local allocation for host bridge structures
(Punit Agrawal)
- Pay attention to device-specific _PXM node values (Jonathan Cameron)
- Support new Immediate Readiness bit (Felipe Balbi)
- Differentiate between pciehp surprise and safe removal (Lukas Wunner)
- Remove unnecessary pciehp includes (Lukas Wunner)
- Drop pciehp hotplug_slot_ops wrappers (Lukas Wunner)
- Tolerate PCIe Slot Presence Detect being hardwired to zero to
workaround broken hardware, e.g., the Wilocity switch/wireless device
(Lukas Wunner)
- Unify pciehp controller & slot structs (Lukas Wunner)
- Constify hotplug_slot_ops (Lukas Wunner)
- Drop hotplug_slot_info (Lukas Wunner)
- Embed hotplug_slot struct into users instead of allocating it
separately (Lukas Wunner)
- Initialize PCIe port service drivers directly instead of relying on
initcall ordering (Keith Busch)
- Restore PCI config state after a slot reset (Keith Busch)
- Save/restore DPC config state along with other PCI config state
(Keith Busch)
- Reference count devices during AER handling to avoid race issue with
concurrent hot removal (Keith Busch)
- If an Upstream Port reports ERR_FATAL, don't try to read the Port's
config space because it is probably unreachable (Keith Busch)
- During error handling, use slot-specific reset instead of secondary
bus reset to avoid link up/down issues on hotplug ports (Keith Busch)
- Restore previous AER/DPC handling that does not remove and
re-enumerate devices on ERR_FATAL (Keith Busch)
- Notify all drivers that may be affected by error recovery resets
(Keith Busch)
- Always generate error recovery uevents, even if a driver doesn't have
error callbacks (Keith Busch)
- Make PCIe link active reporting detection generic (Keith Busch)
- Support D3cold in PCIe hierarchies during system sleep and runtime,
including hotplug and Thunderbolt ports (Mika Westerberg)
- Handle hpmemsize/hpiosize kernel parameters uniformly, whether slots
are empty or occupied (Jon Derrick)
- Remove duplicated include from pci/pcie/err.c and unused variable
from cpqphp (YueHaibing)
- Remove driver pci_cleanup_aer_uncorrect_error_status() calls (Oza
Pawandeep)
- Uninline PCI bus accessors for better ftracing (Keith Busch)
- Remove unused AER Root Port .error_resume method (Keith Busch)
- Use kfifo in AER instead of a local version (Keith Busch)
- Use threaded IRQ in AER bottom half (Keith Busch)
- Use managed resources in AER core (Keith Busch)
- Reuse pcie_port_find_device() for AER injection (Keith Busch)
- Abstract AER interrupt handling to disconnect error injection (Keith
Busch)
- Refactor AER injection callbacks to simplify future improvments
(Keith Busch)
- Remove unused Netronome NFP32xx Device IDs (Jakub Kicinski)
- Use bitmap_zalloc() for dma_alias_mask (Andy Shevchenko)
- Add switch fall-through annotations (Gustavo A. R. Silva)
- Remove unused Switchtec quirk variable (Joshua Abraham)
- Fix pci.c kernel-doc warning (Randy Dunlap)
- Remove trivial PCI wrappers for DMA APIs (Christoph Hellwig)
- Add Intel GPU device IDs to spurious interrupt quirk (Bin Meng)
- Run Switchtec DMA aliasing quirk only on NTB endpoints to avoid
useless dmesg errors (Logan Gunthorpe)
- Update Switchtec NTB documentation (Wesley Yung)
- Remove redundant "default n" from Kconfig (Bartlomiej Zolnierkiewicz)
- Avoid panic when drivers enable MSI/MSI-X twice (Tonghao Zhang)
- Add PCI support for peer-to-peer DMA (Logan Gunthorpe)
- Add sysfs group for PCI peer-to-peer memory statistics (Logan
Gunthorpe)
- Add PCI peer-to-peer DMA scatterlist mapping interface (Logan
Gunthorpe)
- Add PCI configfs/sysfs helpers for use by peer-to-peer users (Logan
Gunthorpe)
- Add PCI peer-to-peer DMA driver writer's documentation (Logan
Gunthorpe)
- Add block layer flag to indicate driver support for PCI peer-to-peer
DMA (Logan Gunthorpe)
- Map Infiniband scatterlists for peer-to-peer DMA if they contain P2P
memory (Logan Gunthorpe)
- Register nvme-pci CMB buffer as PCI peer-to-peer memory (Logan
Gunthorpe)
- Add nvme-pci support for PCI peer-to-peer memory in requests (Logan
Gunthorpe)
- Use PCI peer-to-peer memory in nvme (Stephen Bates, Steve Wise,
Christoph Hellwig, Logan Gunthorpe)
- Cache VF config space size to optimize enumeration of many VFs
(KarimAllah Ahmed)
- Remove unnecessary <linux/pci-ats.h> include (Bjorn Helgaas)
- Fix VMD AERSID quirk Device ID matching (Jon Derrick)
- Fix Cadence PHY handling during probe (Alan Douglas)
- Signal Cadence Endpoint interrupts via AXI region 0 instead of last
region (Alan Douglas)
- Write Cadence Endpoint MSI interrupts with 32 bits of data (Alan
Douglas)
- Remove redundant controller tests for "device_type == pci" (Rob
Herring)
- Document R-Car E3 (R8A77990) bindings (Tho Vu)
- Add device tree support for R-Car r8a7744 (Biju Das)
- Drop unused mvebu PCIe capability code (Thomas Petazzoni)
- Add shared PCI bridge emulation code (Thomas Petazzoni)
- Convert mvebu to use shared PCI bridge emulation (Thomas Petazzoni)
- Add aardvark Root Port emulation (Thomas Petazzoni)
- Support 100MHz/200MHz refclocks for i.MX6 (Lucas Stach)
- Add initial power management for i.MX7 (Leonard Crestez)
- Add PME_Turn_Off support for i.MX7 (Leonard Crestez)
- Fix qcom runtime power management error handling (Bjorn Andersson)
- Update TI dra7xx unaligned access errata workaround for host mode as
well as endpoint mode (Vignesh R)
- Fix kirin section mismatch warning (Nathan Chancellor)
- Remove iproc PAXC slot check to allow VF support (Jitendra Bhivare)
- Quirk Keystone K2G to limit MRRS to 256 (Kishon Vijay Abraham I)
- Update Keystone to use MRRS quirk for host bridge instead of open
coding (Kishon Vijay Abraham I)
- Refactor Keystone link establishment (Kishon Vijay Abraham I)
- Simplify and speed up Keystone link training (Kishon Vijay Abraham I)
- Remove unused Keystone host_init argument (Kishon Vijay Abraham I)
- Merge Keystone driver files into one (Kishon Vijay Abraham I)
- Remove redundant Keystone platform_set_drvdata() (Kishon Vijay
Abraham I)
- Rename Keystone functions for uniformity (Kishon Vijay Abraham I)
- Add Keystone device control module DT binding (Kishon Vijay Abraham
I)
- Use SYSCON API to get Keystone control module device IDs (Kishon
Vijay Abraham I)
- Clean up Keystone PHY handling (Kishon Vijay Abraham I)
- Use runtime PM APIs to enable Keystone clock (Kishon Vijay Abraham I)
- Clean up Keystone config space access checks (Kishon Vijay Abraham I)
- Get Keystone outbound window count from DT (Kishon Vijay Abraham I)
- Clean up Keystone outbound window configuration (Kishon Vijay Abraham
I)
- Clean up Keystone DBI setup (Kishon Vijay Abraham I)
- Clean up Keystone ks_pcie_link_up() (Kishon Vijay Abraham I)
- Fix Keystone IRQ status checking (Kishon Vijay Abraham I)
- Add debug messages for all Keystone errors (Kishon Vijay Abraham I)
- Clean up Keystone includes and macros (Kishon Vijay Abraham I)
- Fix Mediatek unchecked return value from devm_pci_remap_iospace()
(Gustavo A. R. Silva)
- Fix Mediatek endpoint/port matching logic (Honghui Zhang)
- Change Mediatek Root Port Class Code to PCI_CLASS_BRIDGE_PCI (Honghui
Zhang)
- Remove redundant Mediatek PM domain check (Honghui Zhang)
- Convert Mediatek to pci_host_probe() (Honghui Zhang)
- Fix Mediatek MSI enablement (Honghui Zhang)
- Add Mediatek system PM support for MT2712 and MT7622 (Honghui Zhang)
- Add Mediatek loadable module support (Honghui Zhang)
- Detach VMD resources after stopping root bus to prevent orphan
resources (Jon Derrick)
- Convert pcitest build process to that used by other tools (iio, perf,
etc) (Gustavo Pimentel)
* tag 'pci-v4.20-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (140 commits)
PCI/AER: Refactor error injection fallbacks
PCI/AER: Abstract AER interrupt handling
PCI/AER: Reuse existing pcie_port_find_device() interface
PCI/AER: Use managed resource allocations
PCI: pcie: Remove redundant 'default n' from Kconfig
PCI: aardvark: Implement emulated root PCI bridge config space
PCI: mvebu: Convert to PCI emulated bridge config space
PCI: mvebu: Drop unused PCI express capability code
PCI: Introduce PCI bridge emulated config space common logic
PCI: vmd: Detach resources after stopping root bus
nvmet: Optionally use PCI P2P memory
nvmet: Introduce helper functions to allocate and free request SGLs
nvme-pci: Add support for P2P memory in requests
nvme-pci: Use PCI p2pmem subsystem to manage the CMB
IB/core: Ensure we map P2P memory correctly in rdma_rw_ctx_[init|destroy]()
block: Add PCI P2P flag for request queue
PCI/P2PDMA: Add P2P DMA driver writer's documentation
docs-rst: Add a new directory for PCI documentation
PCI/P2PDMA: Introduce configfs/sysfs enable attribute helpers
PCI/P2PDMA: Add PCI p2pmem DMA mappings to adjust the bus offset
...
With l4 interconnect hierarchy and ti-sysc interconnect target module
data in place, we can simply move all the related child devices to
their proper location and enable probing using ti-sysc.
In general the first child device address range starts at range 0
from the ti-sysc interconnect target so the move involves adjusting
the child device reg properties for that.
In case of any regressions, problem devices can be reverted to probe
with legacy platform data as needed by moving them back and removing
the related interconnect target module node.
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Similar to commit 8f42cb7f64 ("ARM: dts: omap4: Add l4 interconnect
hierarchy and ti-sysc data"), let's add proper interconnect hierarchy
for l4 interconnect instances with the related ti-sysc interconnect
module data as in Documentation/devicetree/bindings/bus/ti-sysc.txt.
Using ti-sysc driver binding allows us to start dropping legacy platform
data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of
ti-sysc dts data.
This data is generated based on platform data from a booted system
and the interconnect acces protection registers for ranges. To avoid
regressions, we initially validate the device tree provided data
against the existing platform data on boot.
Note that we cannot yet include this file from the SoC dtsi file until
the child devices are moved to their proper locations in the
interconnect hierarchy in the following patch. Otherwise we would have
the each module probed twice.
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With l4 interconnect hierarchy and ti-sysc interconnect target module
data in place, we can simply move all the related child devices to
their proper location and enable probing using ti-sysc.
In general the first child device address range starts at range 0
from the ti-sysc interconnect target so the move involves adjusting
the child device reg properties for that.
In case of any regressions, problem devices can be reverted to probe
with legacy platform data as needed by moving them back and removing
the related interconnect target module node.
Note that we are not yet moving dss or wkup_m3, those will be moved
later after some related driver changes.
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Similar to commit 8f42cb7f64 ("ARM: dts: omap4: Add l4 interconnect
hierarchy and ti-sysc data"), let's add proper interconnect hierarchy
for l4 interconnect instances with the related ti-sysc interconnect
module data as in Documentation/devicetree/bindings/bus/ti-sysc.txt.
Using ti-sysc driver binding allows us to start dropping legacy platform
data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of
ti-sysc dts data.
This data is generated based on platform data from a booted system
and the interconnect acces protection registers for ranges. To avoid
regressions, we initially validate the device tree provided data
against the existing platform data on boot.
Note that we cannot yet include this file from the SoC dtsi file until
the child devices are moved to their proper locations in the
interconnect hierarchy in the following patch. Otherwise we would have
the each module probed twice.
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With l4 interconnect hierarchy and ti-sysc interconnect target module
data in place, we can simply move all the related child devices to
their proper location and enable probing using ti-sysc.
In general the first child device address range starts at range 0
from the ti-sysc interconnect target so the move involves adjusting
the child device reg properties for that.
In case of any regressions, problem devices can be reverted to probe
with legacy platform data as needed by moving them back and removing
the related interconnect target module node.
Note that we are not yet moving dss or wkup_m3, those will be moved
later after some related driver changes.
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Similar to commit 8f42cb7f64 ("ARM: dts: omap4: Add l4 interconnect
hierarchy and ti-sysc data"), let's add proper interconnect hierarchy
for l4 interconnect instances with the related ti-sysc interconnect
module data as in Documentation/devicetree/bindings/bus/ti-sysc.txt.
Using ti-sysc driver binding allows us to start dropping legacy platform
data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of
ti-sysc dts data.
This data is generated based on platform data from a booted system
and the interconnect acces protection registers for ranges. To avoid
regressions, we initially validate the device tree provided data
against the existing platform data on boot.
Note that we cannot yet include this file from the SoC dtsi file until
the child devices are moved to their proper locations in the
interconnect hierarchy in the following patch. Otherwise we would have
the each module probed twice.
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Convert DRA7xx to use the new clockdomain based layout. Previously the
clkctrl split was based on CM isntance boundaries. The new layout
helps with introducing the interconnect driver instances.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Convert AM43xx to use the new clockdomain based layout. Previously the
clkctrl split was based on CM isntance boundaries. The new layout
helps with introducing the interconnect driver instances.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Convert AM33xx to use the new clockdomain based layout. Previously the
clkctrl split was based on CM instance boundaries. The new layout
helps with introducing the interconnect driver instances.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Two last minute bugfixes, both for NXP platforms:
* The Layerscape 'qbman' infrastructure suffers from probe ordering
bugs in some configurations, a two-patch series adds a hotfix for
this. 4.20 will have a longer set of patches to rework it.
* The old imx53-qsb board regressed in 4.19 after the addition
of cpufreq support, adding a set of explicit operating points
fixes this.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJbwLz1AAoJEGCrR//JCVInfygP/2U3Uqt3Tr2QRROx4wIl0gGh
+sE5gfjBSrXPXq8SoLrJOOgxHYQwbAoWO93rYcmgjhn5a14YZuJzK9cgKiHaHOIc
fbkqjGrJ8Bbmy6gRCKrEVCvF8W6qV4pAwh/VT+HFaKDJK6pblvJEOysAAzFEbAP+
3fOxJcjKh5KaDrvWS/Y/wVBd5BUfpIpPWksWBaRONIfaO24gGs5Bp+OfVS/u2Ccz
iml59Pgg3KsaBr5u6PQSgZDfJ1CX4mMdJS0yLlqCdh+LdHduCWomH15OLIxiCEty
8hrDeSleMRW7MzIhbnxvGgkKGE3wa5yPr5ABMB6DR6wcWuI0V1K5TDr0GP4x53yK
li4+rFGVgenIkGqtFEogYerfbH7jLp3noC/7SYKPsT4wkSSoXegFgOw+tV9DPmVf
6CZbNP98HCNlPyu/pxizHv9PHPKOVmzO7k32Afens35/7/2oPrbeNnXbBRBaKbFF
2oUUNyHER6DOuELsXcMZGLeJpp5lwRa7+0/6pKOFvqkirbJji7N1o7EBNMG2ZL82
OiDXK4SKip9TWDfZ7ueKV8TznYnGlWmiGc1az1wrsOctB8Sk2tqxl7UADFOYM/5L
KBwDw9SVttRWfbKTBhEiaFIyHLY+X6JPSbEqbXU7HL/MNW9JlGVwZzFHtaq/AaYL
yPNvMgg7GFfGpEk8pQFV
=WY74
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Arnd writes:
"ARM: SoC fixes for 4.19
Two last minute bugfixes, both for NXP platforms:
* The Layerscape 'qbman' infrastructure suffers from probe ordering
bugs in some configurations, a two-patch series adds a hotfix for
this. 4.20 will have a longer set of patches to rework it.
* The old imx53-qsb board regressed in 4.19 after the addition
of cpufreq support, adding a set of explicit operating points
fixes this."
* tag 'armsoc-fixes-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
soc: fsl: qman_portals: defer probe after qman's probe
soc: fsl: qbman: add APIs to retrieve the probing status
ARM: dts: imx53-qsb: disable 1.2GHz OPP
Not all boards use two ethernet devices and/or use them in different
order. As almost all in-tree boards already define their own ethernet
aliases, remove them from the dtsi and add the aliases to the two boards,
that are missing their own definition.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
[dinguyen@kernel.org: rebased to latest dts changes]
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Auto-detect nand ECC on the armada-385 based board db-88f6820-amc
instead of hard coded them in the device tree.
-----BEGIN PGP SIGNATURE-----
iFwEABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCW7Y3KgAKCRALBhiOFHI7
1UBvAJiH2KUDbW343DFDnrUsePLsvZQRAJ9WcERzrI5pWPm+m1ix0Gj7Kp1L8g==
=FOy5
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-4.20-2' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt for 4.20 (part 2)
Auto-detect nand ECC on the armada-385 based board db-88f6820-amc
instead of hard coded them in the device tree.
* tag 'mvebu-dt-4.20-2' of git://git.infradead.org/linux-mvebu:
ARM: dts: mvebu: armada-385-db-88f6820-amc: auto-detect nand ECC properites
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This is required for the imx pci driver to send the PME_Turn_Off TLP.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
As the v4l2-fwnode now allows drivers to set defaults, and eventually
override them by specifying properties in DTS, use defaults for the CEU
driver.
Also remove endpoint properties from the gr-peach-audiocamerashield as
they match the defaults now specified in the driver code
(h/vsync-active and bus-width) or are not relevant to the interface
as they cannot be configured (pclk-sample).
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
- Fix crash of qman_portal by deferring its probe if qman is not probed
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEhb3UXAyxp6UQ0v6khtxQDvusFVQFAluypMcACgkQhtxQDvus
FVQvKA/+Kc4IDHyidEgcbdNwjZNkp4eHXKSwtCdMstrEquQ7tOqmxCaEnC9izTBy
wW6XF91ez4DJkQDgxrN1fJN512yTN0v6D7Jq+VclrrGfcT2f1xnNRf33r6957csc
9hOp7S1hkeHZfCRtMZrjwIRgzWtlfH+XcRne/USE/enQ0GmTKThhv2rngH2hnAxP
cqW+ult+jyL+m5i+hpzIZUjSMio4w8Z+K/QEwhlfy63nh2oYc8Zpvql5EYq1oFgd
c0JWA1/DM/dbBiWRZVfjvjw1ZDnkJpYIJDmJYfNz3k4IJJlUYPWM4RrSRn1+yYl9
wg/zZ3a0NlCskn32KlIwE0m1zLLVEjFam+3a7EiIFh98gBGQ5eeIpZ8UAqyc6zLi
4etMYtt6+kUt7x2nsZ1GQrQXembt4TUBf70HMBLz85TaCg6z98PRsYyGRq1vKnj4
sAk8aiCHOsnlqHpKt403U8wUABRAr8m+xGI2D8MSTdzbQnDftf8eqKrLS2qtnlSi
4R3jkBiaszV8O6FdRC8+3VmtaOx/PCGh8Odo3GitDLQBdB1AkFdmIxJBJDcST/Cp
CWAmxJsPIS4PUGJupeIALsJF8rFHiwn5uVxsNRKxpL1xpDD6mwxLSn+LOHQT8fD3
PGhhngQD8ky9nKqL+gckpu/QfjiBrJNeUD6pvhRJc1cI+7ue/nM=
=qVf2
-----END PGP SIGNATURE-----
Merge tag 'soc-fsl-fix-v4.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into fixes
NXP/FSL SoC driver fixes for v4.19 round 2
- Fix crash of qman_portal by deferring its probe if qman is not probed
* tag 'soc-fsl-fix-v4.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: qman_portals: defer probe after qman's probe
soc: fsl: qbman: add APIs to retrieve the probing status
soc: fsl: qe: Fix copy/paste bug in ucc_get_tdm_sync_shift()
soc: fsl: qbman: qman: avoid allocating from non existing gen_pool
ARM: dts: BCM63xx: Fix incorrect interrupt specifiers
MAINTAINERS: update the Annapurna Labs maintainer email
ARM: dts: sun8i: drop A64 HDMI PHY fallback compatible from R40 DT
ARM: dts: at91: sama5d2_ptc_ek: fix nand pinctrl
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This board has a Micron MT29F8G08ABACAWP chip which requires a ECC
strength of 8/512. Rather than hard coding any particular strength the
the nand controller auto-detect the ECC strength based on the ONFI data.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
- i.MX53 QSB board stops working when cpufreq driver is enabled,
because the default OPP table has the maximum CPU frequency at
1.2GHz, while the board is only capable of running 1GHz. Fix up
the OPP table for the board to get it work with cpufreq driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJbtCuVAAoJEFBXWFqHsHzOHDEH/RXzkCIZCmvVhdXIQDa/PC7b
GupBi+UJE2iQMS3Z3RNYnZQ2yK8zq7AZNIjZtR7/8dm6ALFjXMGvfj19Cs0wThdt
VQ3g7FyS76lwvb2sVl6yGZTOcZfn7nIwFC9NNfY1FSt87QXKBPG0UmnMpCxR7m+1
V1d0T3y0WejpRigtzGJZJwibkOFoKy8HbAn09BBzyE+eRnNcXSp6NunIr+82AGgo
yA3rtcoDXD997wXMUUgnFzh0VjqH5wrrbMtplWOFpDtKEFxwiHGOjWsIm6S2xi/8
SKkk13M+GBHtPR0ygTtRngV1TF0z0kTdArhS/GGGTzWbpZ5sri5khyCfNP+i0LA=
=xyJS
-----END PGP SIGNATURE-----
Merge tag 'imx-fixes-4.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
i.MX fixes for 4.19, round 2:
- i.MX53 QSB board stops working when cpufreq driver is enabled,
because the default OPP table has the maximum CPU frequency at
1.2GHz, while the board is only capable of running 1GHz. Fix up
the OPP table for the board to get it work with cpufreq driver.
* tag 'imx-fixes-4.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx53-qsb: disable 1.2GHz OPP
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
----------------------------
- A non-critical fix to reduce errors on A/DC on Lego Mindstorms EV3
- Support for GPIO expander on DA850 EVM
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJbtiwqAAoJEGFBu2jqvgRNmF0QAJNow69RDeV/WHJgFhxN79pK
Qo5bjwgVEhz1fbFDaIoOxYcIjWfJ0zlum1F8PHGh/GN68vrGqrxF01yHqoVTVfpL
GQ6B4r0D7Dz6AjQem01wqaqiPQ2IaNaZzFB+ExYR3nePiZu2s9qj5uXfPDaib7rS
8unBRbWJEJP7Ip0z90XY9nOxYCT5OALAJdCs1bGfxaqlZJN3vucghmeuBXXNmSNx
4W1j3pb/2ogxL0N+T3OsKPhA6FF6/3VYGLYOuy7I0SWtxNEiV5oBsWSEMBoBCR42
mtS84rjzUpbKvGepdt//kmtUYMv8xw5d78gnfbrJqFN5DpDk33SqknVe3ffun5o9
TLhhgl1sGZzINhI3ZK648Z7VHL2dzeI13Qz6BA13w1gsv1cxBHdnMjkxq2wDhjRK
h0ZKjdoqJavij04Bng/hjMMjR5or21UwuxrGVxqGkx4iFrkkbrk+ahaNi5Do7+bd
dEZnzPTOB/pG3nnF42vLO/QSoKBoAsjK0ZDMnoV65/GjmMVWQryW7QtdVCqfmPAk
XRAZV6lU2UCFWdmA934acF2tqeUkpT7irecuoWiAA0lfhvFqhpGScVwy888/OYzz
QQzs8EN75q6OfyAc2ETNMplAdc6KRmf6wuAn7DAOBZDN2eREsqgNgTMPXcDFUOe2
bRRC7qjLeFDYb7mSXttw
=NVmP
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v4.20/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt
DaVinci DT updates for v4.20
----------------------------
- A non-critical fix to reduce errors on A/DC on Lego Mindstorms EV3
- Support for GPIO expander on DA850 EVM
* tag 'davinci-for-v4.20/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: dts: da850-lego-ev3: slow down A/DC as much as possible
ARM: dts: da850-evm: Enable tca6416 on baseboard
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
dtc warning, gpio setting for the sdmmc regulator on radxarock and a
new board the "S" variant of the rk3288-based Tinker board, that sports
an added emmc.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAluyKz0QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgSxkB/9hXQysAvkRD0oCsBhRpRse/XkE99IyqoFD
QixXrUVdO21P5h/x0seJoqVE/dFrl2iQUBhgL9jyRHEZGPoTbZw0KoSe50KwGQp4
WkMqj9MukWdM11HDmonaQR+CcyoOkZHhWjGHuSIUSJKWi8wugVzL/X9IzHd7VdqB
TZ6DDnFqbxOsCMDw4jcPIRMO/wkePR7g3sL3u+Wn/9owsfho4pvP+kX/b8DOwS1N
mI30Ga+0O19XtGx3psc+xh7PSjKbw5UzVFz7EtHgeQHl0YjYUGh+RRf4nJmg17+T
YfxzVuvFLol6cKITI+iU5CGaJdazR1cThekCEyxFMHXlLIlxogLq
=MloN
-----END PGP SIGNATURE-----
Merge tag 'v4.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Nodes for the newly support rk3188 display controller, a fix for a new
dtc warning, gpio setting for the sdmmc regulator on radxarock and a
new board the "S" variant of the rk3288-based Tinker board, that sports
an added emmc.
* tag 'v4.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add rk3288-based Tinker board S
ARM: dts: rockchip: move shared tinker-board nodes to a common dtsi
ARM: dts: rockchip: explicitly set vcc_sd0 pin to gpio on rk3188-radxarock
ARM: dts: rockchip: Fix erroneous SPI bus dtc warnings on rk3036
ARM: dts: rockchip: add rk3188 lcd controller nodes
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Due to the electrical design of the A/DC circuits on LEGO MINDSTORMS EV3,
if we are reading analog values as fast as possible (i.e. using DMA to
service the SPI) the A/DC chip will read incorrect values - as much as
0.1V off when the SPI is running at 10MHz. (This has to do with the
capacitor charge time when channels are muxed in the A/DC.)
This patch slows down the SPI as much as possible (if CPU is at 456MHz,
SPI runs at 1/2 of that, so 228MHz and has a max prescalar of 256, so
we could get ~891kHz, but we're just rounding it to 1MHz). We also use
the max allowable value for WDELAY to slow things down even more.
These changes reduce the error of the analog values to about 5mV, which
is tolerable.
Commits a3762b13a5 ("spi: spi-davinci: Add support for SPI_CS_WORD")
and e2540da86e ("iio: adc: ti-ads7950: use SPI_CS_WORD to reduce
CPU usage") introduce changes that allow DMA transfers to be used, so
this slow down is needed now.
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
There is a GPIO expander on both the UI board as well as the
baseboard. This patch enables the second tca6416 and identifies
it as being on the baseboard using _bb as the suffix.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
There's a patch for previously merged dts changes to remove the last
remaining use of legacy phy_id property.
For dra7, we have a non-urgent PCIe dts fix, enable a PCIe errata for
unaligned access.
For omap5, we enable omap5 USB OTG mode for DWC3 controller.
And we add support for am335x based Moxa UC-2100 series of industrial
computers.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAluzhIwRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXNbIRAA3hJaUoW6ous4f/FuNmB+mmruWpH6UqII
bSmxA6RZhv4POuaJTuGLV0/j6JUtmuIAQ77PQmzJxk/M+4Sjv6DLU9uyFLKTQPtG
cOJpDPh6ngGezse5H8rW8IinRhALUktEl5fV79Rp6GycyXX/be0H6SP5EU3iz6l9
XE6eHJRxgCWydtHPkSB8m9/RCQMgCmMVr1Ea/Ph+HM5QQuzR2vqafqih8rpstvBj
JpBbefedi+7PppDczbVFySQ5Ip3LYh4aU67L9p/X1p+JGdk9aVUANjeP/pUVKXu1
V9PlRhMaPNARpdFpmy+X7uhQbho5Cs1zC/HlH7Q+p7M7kbt6GxBHQRVZlspb9xol
qcCNk72hY5Dv5ih0H2t3NMTHNYY4Wh2WCig5F74eFXBm5Heo9Mj2sAnRSAXfC0oc
CM9ZTWSKk0rvkudXsIHKrmhiIHIlOAWbKNQ3OB+q4t01pyIEpU0Qc4a/hR2NAU2S
AN5V7wWeS3uJp1CaeN7YPL/FP9r0g6vQ3LUQkR8N+O8LKLNfiaACBCFj9vsqg2Kh
V2V034FqwOHRCChxrmLDfee9FS5gVfe0HjAH5nX1UchkHFRD+6ljW3TCYijgCH1i
zsU1vyRWIH68bb3w2zMPFd60Yd+xvXNt0BetLyhwG4fDDk5rNyHhELfHC3p8XHSC
wrX3FJmo83E=
=EQcw
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.20/dt-signed-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
More devicetree changes for omap variants
There's a patch for previously merged dts changes to remove the last
remaining use of legacy phy_id property.
For dra7, we have a non-urgent PCIe dts fix, enable a PCIe errata for
unaligned access.
For omap5, we enable omap5 USB OTG mode for DWC3 controller.
And we add support for am335x based Moxa UC-2100 series of industrial
computers.
* tag 'omap-for-v4.20/dt-signed-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x: Replace remaining legacy phy_id with phy-handle
ARM: dts: am335x: add support for Moxa UC-2101 open platform
ARM: dts: am335x: add common file for UC-2100 series
ARM: dts: omap5: enable OTG role for DWC3 controller
ARM: dts: dra7: Enable workaround for errata i870 in PCIe host mode
ARM: dts: dra7: Fix up unaligned access setting for PCIe EP
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add USB3 controller nodes including usb-core, resets, regulator, ss-phy
and hs-phy. This supports for Pro4, PXs2 and the boards.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
sama5d4_xplained, ssam9x5cm, sama5d2_ptc_ek and sama5d3_xplained nand
flashes have a common memory map. Even the nand memory partitions to
match our NAND flash map available at:
http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
sama5d3_xplained, sam9x5cm, sama5d2_ptc_ek and sama5d4_xplained nand
flashes have a common memory map. Even the nand memory partitions to
match our nand flash map available at:
http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
sam9x5cm, sama5d2_ptc_ek, sama5d3_xplained and sama5d4_xplained nand
flashes have a common memory map. Even the nand memory partitions to
match our nand flash map available at:
http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.png
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
at91sam9x5cm comes with a 2Gb NAND flash. Fix the rootfs size to
match this limit.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
sama5d4_xplained comes with a 4Gb NAND flash. Increase the rootfs
size to match this limit.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Add SD controller nodes for LD4, Pro4, sLD8, Pro5, and PXs2.
This is also used as an eMMC controller for LD4, Pro4, and sLD8.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This branch contains a series of improvments for omap3-gta04 phone,
and a series of clean-up for am335x to remove the deprecated phy_id
property.
The rest is to configure am57xx-idk boards for leds, load trigger,
and smps, am3517-evm audio configuration, beaglebone hdmi cec support,
coresight binding update, and fixes for i2c and spi warnings.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlutJwIRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXMMyw/+Oj8WK2Dej372d0m2I2401fLYD4L5B99U
H/It6JAAmumv2y/6IZEiPAC+TtBpTgbmMlQzyciaKRyWCjqpfg1DDb1mSNf+3RSq
VFsCkOx5cymGL2yKn8DzyIYGRejwkbfDVH6UbQTHv84mLtgX/8liqAdeSMOShx22
r7G1ismE4UwwNlVKVSd94Y/fJArDlanbRJqTXl+PVqPPDpC/MoMOu8KpPJ0hJyWi
pRYxJHSGTGttLxYv9w5i5S3N4C2b/A3vFfMo35EqHXr/t08Lfcqh1vhaMtcXRdQO
TrOMF4rvWZA4H8uVP+8sqQfwtcDrCnCBoh1VeFJrAHBdtfEJU2rqq2BoVvQXJYCi
WWu/iaa13C8xktS46NvBE4UODAxo52ciyQEzckDbQSjdUm7G82sfciSVRlWfrtjM
rBOyaNMWDTWEE7H99O75QlEA4E4J8xcgpmkHplZ3CuNEmtJx/OeknXD7F91g6FJt
13TmUj1/Wu72ZZLlkeazLLdVG1lj6M4WKdv3L3oDbaJkLAiRSQj/oIAi/R1gFbcW
i+SejX4NPqjA1f1i3tiKzmBY70ur0jPnR9iNNyMs+9VzqbRUQJQd/DOQG7TA9BYk
qE0jWBjnuWjo3+EAvel9LrIrJvrApXaJPvFC6eLaAjLbqkJ81lqwGQIivHrgHih5
vIWlcV1hWoA=
=bCXk
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.20/dt-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Devicetree changes for omap variants
This branch contains a series of improvments for omap3-gta04 phone,
and a series of clean-up for am335x to remove the deprecated phy_id
property.
The rest is to configure am57xx-idk boards for leds, load trigger,
and smps, am3517-evm audio configuration, beaglebone hdmi cec support,
coresight binding update, and fixes for i2c and spi warnings.
* tag 'omap-for-v4.20/dt-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (70 commits)
ARM: dts: add omap3-gta04a5one to Makefile
ARM: dts: omap3-gta04: add pulldown/up settings for twl4030 gpio
ARM: dts: am335x-boneblack: add cec support
ARM: dts: am3517-evm: Add support for UI board and Audio
ARM: dts: gta04: add serial console wakeup irq
ARM: dts: am57xx-idk-common: Hook smps12 regulator as cpu vdd-supply
ARM: dts: omap: Update coresight bindings for hardware ports
ARM: dts: ti: Fix SPI and I2C bus warnings
ARM: dts: dra62x-j5eco-evm: get rid of phy_id property
ARM: dts: dm8148-t410: get rid of phy_id property
ARM: dts: dm8148-evm: get rid of phy_id property
ARM: dts: am57xx-cl-som-am57x: get rid of phy_id property
ARM: dts: am57xx-idk-common: get rid of phy_id property
ARM: dts: dra7-evm: get rid of phy_id property
ARM: dts: dra71-evm: get rid of phy_id property
ARM: dts: dra72-evm-revc: get rid of phy_id property
ARM: dts: dra72-evm: get rid of phy_id property
ARM: dts: dra76-evm: get rid of phy_id property
ARM: dts: am437x-cm-t43: get rid of phy_id property
ARM: dts: am437x-gp-evm: get rid of phy_id property
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- updates the armada-xp-98dx3236 SoC and related boards to use the new
style dts bindings for nand
- add db-88f6820-amc board: plugin card for some of Marvell's switch
development kits
- fix SPI and I2C bus warnings coming with the new checks in dtc
- add new compatible string "marvell,prestera" to the armada-xp-98dx*
- fix sdhci supply property name on the clearfog (the '-supply' suffix
was missing)
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCW7HlPQAKCRALBhiOFHI7
1WD8AKCdfJ2vxjsHeFJ5YEOA7JtdjJaaXwCffYZJ9IS0XblfyH9bsh9P/cy7nXI=
=CsQf
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-4.20-1' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt for 4.20 (part 1)
- updates the armada-xp-98dx3236 SoC and related boards to use the new
style dts bindings for nand
- add db-88f6820-amc board: plugin card for some of Marvell's switch
development kits
- fix SPI and I2C bus warnings coming with the new checks in dtc
- add new compatible string "marvell,prestera" to the armada-xp-98dx*
- fix sdhci supply property name on the clearfog (the '-supply' suffix
was missing)
* tag 'mvebu-dt-4.20-1' of git://git.infradead.org/linux-mvebu:
ARM: dts: clearfog: fix sdhci supply property name
ARM: dts: mvebu: add "marvell,prestera" to PP nodes
ARM: dts: marvell: Fix SPI and I2C bus warnings
ARM: dts: mvebu: Add device tree for db-88f6820-amc board
ARM: dts: mvebu: db-xc3-24g4: use new style nand binding
ARM: dts: mvebu: db-dxbc2: use new style nand binding
ARM: dts: mvebu: 98dx3236: Rename nand controller node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- New board support: Engicam's i.Core MX6 CPU module v1.5; ConnectCore
6UL Single Board Computer (SBC) Pro; i.MX6 ULZ based EVK board.
- Add Add SFF interface support for vf610-zii board.
- Disable unneeded devices like VPU and internal watchdog for imx51-zii
boards.
- Add 'no-sdio' and 'no-sd' property for vf610-zii-cfu1 board.
- Improve i.MX6 SLL GPIO support by adding gpio-ranges property and
clocks information.
- Update iomux header for i.MX7 Solo and i.MX6 ULL.
- Enable GPIO buttons as wakeup source for imx7d-sdb and imx6sx-sdb.
- Add GPIO keys and egalax touch screen support for imx6qdl-sabreauto.
- Switch to use SPDX-License-Identifier for more boards - vf610-twr,
imx7s-warp, Engicam boards.
- Add device tree bindings of 'fsl,pmic-stby-poweroff' property and add
the support for i.MX6 RIoTboard.
- DTC has new checks for SPI buses which will be landed on 4.20.
A patch from Rob to fix those 100+ warnings on i.MX boards. (Thanks!)
- Switch i.MX7 device tree to use updated coresight binding for
hardware ports.
- Misc small or random update and cleanup.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJbsb9RAAoJEFBXWFqHsHzObO8H/Al83K27UxL8XjKMOUsMooWX
BG5FfS9mDKOe8bN0BwZnUmrjuOOkNWooMxyahBXP9e0CWZnK/4G3OvTS83PNpA34
zE+Nm1oJia9zoUsWoCpBrvLrBJpjJqVajQiXzddUDgYLhbNXPXkiwBBEZqrwAJBK
CsgwRCj4qJA1WCetvwjYVVwtcVTCCnYcpx73YQMLK1sSbi0oVqtSMynSF3spzDVC
iduF+ur88lkjo0IK1PaWMOi8+G6E5bOV//4JJky5hNcTuMsmAAywmUEALoIYQjLr
EitPoTNi2FDnFDpGPqvsf51Cez6e+3iCAk0F5V6D+6nIvNDF9mGRdyqSnDhIyBY=
=B0Zy
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
i.MX device tree update for 4.20:
- New board support: Engicam's i.Core MX6 CPU module v1.5; ConnectCore
6UL Single Board Computer (SBC) Pro; i.MX6 ULZ based EVK board.
- Add Add SFF interface support for vf610-zii board.
- Disable unneeded devices like VPU and internal watchdog for imx51-zii
boards.
- Add 'no-sdio' and 'no-sd' property for vf610-zii-cfu1 board.
- Improve i.MX6 SLL GPIO support by adding gpio-ranges property and
clocks information.
- Update iomux header for i.MX7 Solo and i.MX6 ULL.
- Enable GPIO buttons as wakeup source for imx7d-sdb and imx6sx-sdb.
- Add GPIO keys and egalax touch screen support for imx6qdl-sabreauto.
- Switch to use SPDX-License-Identifier for more boards - vf610-twr,
imx7s-warp, Engicam boards.
- Add device tree bindings of 'fsl,pmic-stby-poweroff' property and add
the support for i.MX6 RIoTboard.
- DTC has new checks for SPI buses which will be landed on 4.20.
A patch from Rob to fix those 100+ warnings on i.MX boards. (Thanks!)
- Switch i.MX7 device tree to use updated coresight binding for
hardware ports.
- Misc small or random update and cleanup.
* tag 'imx-dt-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (50 commits)
ARM: dts: imx: add i.mx6ulz and i.mx6ulz 14x14 evk support
dt-bindings: arm: add compatible for i.MX6ULZ 14x14 EVK board
ARM: dts: imx53-ppd: Remove 'num-chipselects' property
ARM: dts: vf610-twr: Switch to SPDX identifier
ARM: dts: vf: Switch to SPDX identifier
ARM: dts: imx6qdl-zii-rdu2: Disable the internal RTC
ARM: dts: imx51-zii-rdu1: Fix the rtc compatible string
ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
ARM: dts: imx: Fix SPI bus warnings
ARM: dts: imx7: Update coresight binding for hardware ports
ARM: dts: vf610-zii-cfu1: Pass the 'no-sd' property
ARM: dts: vf610-zii-cfu1: Pass the 'no-sdio' property
ARM: dts: imx51-zii-scu2-mezz: Disable the internal watchdog
ARM: dts: imx51-zii-scu2-mezz: Disable VPU
ARM: dts: imx51-zii-scu3-esb: Disable VPU
ARM: dts: imx51: Add label for VPU node
ARM: dts: imx6ull: update vdd_soc voltage for 900MHz operating point
ARM: dts: imx6ul: Add DTS for ConnectCore 6UL SBC Pro
ARM: dts: imx6: RIoTboard provide standby on power off option
dt-bindings: imx6q-clock: add new fsl,pmic-stby-poweroff property
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Fix IRQ constants usage on MSM8974
* Add led, gpio-button, sdcc, and pcie nodes for IPQ8064
* Move/cleanup common nodes for IPQ8064
* Add i2c sensor nodes for MSM8974 Hammerhead
* Fixes for SAW, kpss, opp, pci range, and space/tab on IPQ4019
* Update coresight bindings
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJbsROJAAoJEFKiBbHx2RXVgeoQAME0KidGF3FQsr/IjUD423bz
lUQIXwpuHFz9D/MHqfyvZTfX9unqCV5fn8hPH86Q3ozUqZTRR9fVruVwKRgi4nkp
T6fZsyB4KZrvENyHrcs9Pn1j3yKSGKTu8OcZOvOzTDotFAhy+YE9emzY+8WNFnDU
CfGpghwMj3DsuTEhk/C+N/MWMMrKITNMzxVK7f7LALr9LCzrxNITu5+hZmD8bJDT
P31/XnVoh3FXpue6AkYFRa8KT5VlFy4kOCMh/Uouhk2ONlPptASV1rnuZSYyfAHg
NhtBYQMMyi/6dsoj3JDMz2p3HmIjZPPxbWoM98jqGPcDDOeEsvR1DCQGVM0C85x+
DWM3TBo5J0EocPzBfr4MHKcbZkOxm7xyWDKPnZfWLFu5KxgcytYbQXQPTJH1zheL
khZA0ghoZ6enH+k17knPgHNxgEfFe2sZJg6FW88kMwNZyEZ3OPoIndXqjdwshc4a
jEhMdiTrlM8X7IEqBS0akErVYi0uDxcD3K7IqavEjWn3GwTcw3TDNdp1ViIC7ldS
Q6n9cK4V+aQ2h2gFMgKMijqbZ87Dhi2u9D1ltwxhaXDlMFTufDo+8sFD0tM9g0O6
0XlYKxBogXavL9f/23gUm2pyBjITVpRpeRlbyQh0KU24IFz9Y2BWYqBwnqBLK1D+
XwWKeLlV9b7ZJP5NvtIp
=74RU
-----END PGP SIGNATURE-----
Merge tag 'qcom-dts-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt
Qualcomm Device Tree Changes for v4.20
* Fix IRQ constants usage on MSM8974
* Add led, gpio-button, sdcc, and pcie nodes for IPQ8064
* Move/cleanup common nodes for IPQ8064
* Add i2c sensor nodes for MSM8974 Hammerhead
* Fixes for SAW, kpss, opp, pci range, and space/tab on IPQ4019
* Update coresight bindings
* tag 'qcom-dts-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
ARM: dts: qcom: Update coresight bindings for hardware ports
ARM: dts: qcom-msm8974: change invalid flag IRQ NONE to valid value
ARM: dts: qcom: ipq4019: fix space vs tab indenting inside qcom-ipq4019.dtsi
ARM: dts: qcom: ipq4019: fix PCI range
ARM: dts: qcom: ipq4019: fix cpu0's qcom,saw2 reg value
ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq support
ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanism
ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for ALS / proximity
ARM: dts: qcom: msm8974-hammerhead: add device tree bindings for mpu6515
ARM: dts: qcom: Add led and gpio-button nodes to ipq8064 boards
ARM: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi
ARM: dts: qcom: Add sdcc nodes for ipq8064
ARM: dts: qcom: Add pcie nodes for ipq8064
ARM: dts: qcom-msm8974: change invalid flag IRQ NONE to valid value
ARM: dts: qcom-msm8974: use named constant for interrupt flag NONE
ARM: dts: qcom-msm8974: use named constant for interrupt flag LEVEL HIGH
ARM: dts: qcom-msm8974: use named constant for interrupt flag EDGE RISING
ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_SPI
ARM: dts: qcom-msm8974: use named constant for interrupt type GIC_PPI
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Our usual bunch of DT patches for the Allwinner arm32 SoCs.
The most notable changes are:
- Support for the video decoding / encoding engine on the
A10s/A13/A20/A33
- IR support for the A83t
- SATA support for the R40
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE0VqZU19dR2zEVaqr0rTAlCFNr3QFAluvkSIACgkQ0rTAlCFN
r3Snkw/9FtNLppZKqT2l5NdU7eRE2nUGNvBBh1Dgw2lIlWyzpffjsdMBzZRGahTT
wK/uZwvrLmdtb2WKWCnEJ4k2Vrp3nPGGNlOdonsf9I5CqR/Cl88Z6HPIdEI1FwMC
bNgrC8LENP+zsDPjMZkgOJ/JBlOmPco9l42mC8c2kfLtSiKdiQWNZ88oPgCoiRbJ
VCWnxnxU7pQkX10yj/aIu1bhcFgxLYa1M2C0rj4AkxIdWChVaDZxiDCncuSIqcHt
7a4NchkBXOZeqYY2Dz3ppdxFnQWOhvR0qQJjHzVcGdKNDKurNv0Ud6Mq2v4+Doo9
gJUKGy0PcbvMwm3spOK/CdcW+c3IfO2bJaOz36mE3S3d6a78Ku7UeIc2GnlL9zfx
EYsowLaERm3213ZsbXWB07vfOxoJtk7cmCRIdnuk2S9sFaTZzB65/x+0lNCdxAbL
6Pc4/ZBYVp596T2fGjjnPho6bx9SQ2+ybz9/epEHVRTBYja2zIfJ/Pw4D8ofxDBR
bDZznX3EmE4L1m1w6FaDQzDsoQNv6pS/fiTfsXD35OnzNY0KplbFfcOCZQpF31Mi
7s6iADszYEcefXOwmuIekG5Zw2qcCt4sNkWu/U0hjPXf3TVMnaImPce5K6PBXJHt
zu9DabmboEHicazYPlvJflWD9gkbM5lHdNGAmqWVm/eQ7IDH0Z8=
=vyaf
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner DT changes for 4.20
Our usual bunch of DT patches for the Allwinner arm32 SoCs.
The most notable changes are:
- Support for the video decoding / encoding engine on the
A10s/A13/A20/A33
- IR support for the A83t
- SATA support for the R40
* tag 'sunxi-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sun9i: Fix I2C bus warnings
ARM: dts: sunxi: Fix I2C bus warnings
ARM: dts: sun8i-a33: Add Video Engine and reserved memory nodes
ARM: dts: sun7i-a20: Add Video Engine and reserved memory nodes
ARM: dts: sun5i: Add Video Engine and reserved memory nodes
ARM: dts: sun8i: sun8i-r40-bananapi-m2-ultra: enable AHCI
ARM: dts: sun8i: r40: add sata node
ARM: dts: sunxi: Don't use cd-inverted in sun8i-r40-bananapi-m2-ultra
ARM: dts: sun8i: a83t: bananapi-m3: Enable IR controller
ARM: dts: sun8i: a83t: Add support for the cir interface
ARM: dts: sun8i: a83t: Add the cir pin for the A83T
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This is our usual H3/H5 pull request
The most notable changes are:
- the video decoding / encoding unit is finally enabled on the H3
- Mali support for the H5
- New boards: BananaPi M2+ v1.2, Orange Pi Zero Plus 2 H3 support
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE0VqZU19dR2zEVaqr0rTAlCFNr3QFAluvhigACgkQ0rTAlCFN
r3SHzA/+IsYaAQgvy8NE7Ok1rhy/OU7eLPjd2JVqBgJ6SwCkcM4eW7Zol6SoMawG
Wt9Bh+1JFvyzi4GiftwL/rPzOh2rxjuuDZMmLo5sZBztTLoFmKv9XIYgjnv8kVJY
WXQ5Z3BOKA0H6lyIw6jinS6uotTGiWhtvihOpoAeus8pHJ/AWo3lbntb0tdPob7b
fA95Dsm5ddqhPonrkqq1WEJ+Yepetoa7m2U2dJLOUHPaX8AmIm4GgQNoA6MEVYRJ
0sZ/FDhe+5yvDRKbebVRrlqITGgwEYuTPYO1zQEQleQo6SPEvJuUOo+CW5R3Pgqc
sKk5UxohaAvxbATt5gYhqTl4GwSKkMrNdJroVTc3bf8CekwxgpnNoV2nszGQSrjH
yU2Nwy0d2ok4ZacxoFBjosbGWYh2UuqAlv7lX/UPr79GbeJpA9IUDXQxBGJoodTH
0Wy3rUSgAUU/nRfsaDZtkLqIB8/keiSZzWV97aCnIUGHWk00MfnB8nzhkU1YEel0
8Lbqh+9NY4+P3Ps4UxsnOIL0LQZt2Twf738GF/boa4RftYQOUJJQmvNO8TpFL0OK
VKe10hX0trfsNOv2Ws7oTsGrLZXqLsB8r6jjsSX84NR2Dft2CYj8s7u2lpnmFTxd
ciBjzeyFb4TbYW2iYOsYLRaei0w8GSNMdHShNU04fO/zh1dP8lU=
=AJmQ
-----END PGP SIGNATURE-----
Merge tag 'sunxi-h3-h5-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner H3 and H5 DT additions for 4.20
This is our usual H3/H5 pull request
The most notable changes are:
- the video decoding / encoding unit is finally enabled on the H3
- Mali support for the H5
- New boards: BananaPi M2+ v1.2, Orange Pi Zero Plus 2 H3 support
* tag 'sunxi-h3-h5-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees
ARM: dts: sun8i-h3: Add Video Engine and reserved memory nodes
arm64: dts: allwinner: h5: Add device tree for Bananapi M2 Plus H5
ARM: dts: sun8i: h3: Split out non-SoC-specific parts of Bananapi M2 Plus
ARM: dts: sun8i: h3: bpi-m2-plus: Fix address for external RGMII Ethernet PHY
ARM: dts: sun8i: h3-h5: ir register size should be the whole memory block
arm64: dts: allwinner: h5: Add device node for Mali-450 GPU
ARM: dts: sun8i: Add initial Orangepi Zero Plus 2 H3 support
nvmem: sunxi-sid: add support for H5's SID controller
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
A handful of fixes that have been coming in the last couple of weeks:
- Freescale fixes for on-chip accellerators
- A DT fix for stm32 to avoid fallback to non-DMA SPI mode
- Fixes for badly specified interrupts on BCM63xx SoCs
- Allwinner A64 HDMI was incorrectly specified as fully compatble with R40
- Drive strength fix for SAMA5D2 NAND pins on one board
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAluxIecPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3KswP/iJT6PRSv2OiZq5UyUPhAOx9dW+9uQP5qCYO
43hRkEhUQEbHAibjd4jKq7r2jNfOEeoZARyhE89tQc+RxwU7oOxH5Aohbmk1o4TQ
bQ8AQHoofdNerwr8LKWAWvXe6Ff74d6NIJEQZ1ampndt7pul6LDJbLGg503tDPKZ
fomG/W50id7xA8xexEfZZRXZu9HSRqNk6/wZYycUhsreZZ30nSQwJTJvLiSiTTAh
qWleTc0dD3BazQBEf8VJwLSu3UfigXF+dP7p/joElgULhk00fHYrhWdAa8d0F3ib
tS0foD/alLVslnjIDh8baEkErfqDvtZlpRCinNob1R56yzmkSxjBqCb6kSt4jCN8
o+rlNnmnJPRH/qj0wdjd9phw5AWyZw1V1lSRvZGPacG6i7ZYb02Sj13u05k8826m
hIpnryhrwuO8lKrDUCV4GT/oDpKS7ujskJZFWEUgjXHZA/XDodNXN5Rkuw8LeJmh
HJx1Ef5v/RLbdoIl3Ybs1zDdbg9rmxdaqfDs3Ukka9doZGB1wtZh+GbF1v6u6GZi
zmrcu3jzhDVek7Lw1ZWUCUBCxmYLbcg2txd6ZtkCV09M/fuSnQuxF/mLqiq03YAL
ASy7ejKc5tf8DPnHKlZ7KIR4eMXEhxUFOpKblAQktHvREel2zC5xjOQjQvCTm1hD
w5rDtaPt
=+/9J
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Olof writes:
"ARM: SoC fixes
A handful of fixes that have been coming in the last couple of weeks:
- Freescale fixes for on-chip accellerators
- A DT fix for stm32 to avoid fallback to non-DMA SPI mode
- Fixes for badly specified interrupts on BCM63xx SoCs
- Allwinner A64 HDMI was incorrectly specified as fully compatble with R40
- Drive strength fix for SAMA5D2 NAND pins on one board"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: stm32: update SPI6 dmas property on stm32mp157c
soc: fsl: qe: Fix copy/paste bug in ucc_get_tdm_sync_shift()
soc: fsl: qbman: qman: avoid allocating from non existing gen_pool
ARM: dts: BCM63xx: Fix incorrect interrupt specifiers
MAINTAINERS: update the Annapurna Labs maintainer email
ARM: dts: sun8i: drop A64 HDMI PHY fallback compatible from R40 DT
ARM: dts: at91: sama5d2_ptc_ek: fix nand pinctrl
Add SD card write-protect pin configuration to be sure that it will be
properly pulled down to indicate write access.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Switch to the new hardware port bindings for coresight
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The 'num-chipselects' property is not a valid property according
to Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt, so
let's remove it.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Bananapi released an updated revision of the H3/H5 based Bananapi M2+.
Version 1.2 enables voltage control for the CPU's regulator by using
a GPIO line to toggle a MOSFET that can change the effective resistance
value in the regulator's feedback network.
This patch adds a common .dtsi file for this new revision, which
includes the original common sunxi-bananapi-m2-plus.dtsi file, and
adds the GPIO-controlled regulator and a cpu-supply reference. H3
and H5 variant dts files are added as well.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This adds nodes for the Video Engine and the associated reserved memory
for the H3. Up to 96 MiB of memory are dedicated to the CMA pool.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Three more variants of the Bananapi M2 Plus have been introduced. One
with the H5 instead of the H3, another with the H2+ instead, and the
last with the H3 but with WiFi and eMMC removed.
All these variants use the same board. This patch splits out the
non-SoC-specific parts of the device tree, so that they can be shared
among all the variants. The original Bananapi M2 Plus has been renamed
to Bananapi M2 Plus H3.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The external RTL8211E RGMII Ethernet PHY is configured via external
resistors to use the address 0x1. The 0x0 address is a broadcast address
for this family of PHYs, and should not be used explicitly.
Fixes: 8c7ba536e7 ("ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i")
Fixes: 4904337fe3 ("ARM: dts: sunxi: Restore EMAC changes (boards)")
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embed3d@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Orangepi Zero Plus 2 is an open-source single-board computer, available in two
Allwinner SOC variants, H3 and H5. We add support for H3 variant here, as the
H5 is already supported by sun50i-h5-orangepi-zero-plus2.dts.
H3 Orangepi Zero Plus 2 has:
- Quad-core Cortex-A7
- 512MB DDR3
- microSD slot and 8GB eMMC
- Debug TTL UART
- HDMI
- Wifi + BT
- OTG + power supply
Signed-off-by: Diego Rondini <diego.rondini@kynetics.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Looks like we still have two instances of phy_handle that did not
get update by Grygorii's series. Let's replace these too with
standard phy-handle.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Neeraj Dantu <dantuguf14105@gmail.com>
Reported-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for Moxa UC-2101 open platform
The UC-2101 computing platform is designed for industrial embedded
data acquisition and processing applications.
The features of UC-2101 are:
* eMMC
* SPI flash
* 1x LAN
* 1x RS-232/422/485 ports, software-selectable
* EEPROM
* TPM 2.0
* Watchdog
* RTC
* User gpio-keys
* User LEDs
* User button
Signed-off-by: Wes Huang (黃淵河) <wes.huang@moxa.com>
Signed-off-by: Fero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com>
Signed-off-by: SZ Lin (林上智) <sz.lin@moxa.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The UC-2100 series consists many boards with different peripheral
devices and wireless modules, hence we fetch common items and
create a common dtsi file to increase reusability. All boards in
UC-2100 series will include this common dtsi file.
Signed-off-by: Wes Huang (黃淵河) <wes.huang@moxa.com>
Signed-off-by: Fero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com>
Signed-off-by: SZ Lin (林上智) <sz.lin@moxa.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Since SMPS10 and OTG cable detection extcon are described here, and
work to enable OTG power when an OTG cable is plugged in, we can
define OTG mode in the controller (which is disabled by default in
omap5.dtsi).
Tested on OMAP5EVM and Pyra.
Suggested-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add ti,syscon-unaligned-access property to PCIe RC nodes to set
appropriate bits in CTRL_CORE_SMA_SW_7 register to enable workaround for
errata i870.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
incorrectly documented in the TRM. In fact, the bit positions are
swapped. Update the DT bindings for PCIe EP to reflect the same.
Fixes: d23f3839fe ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
Cc: stable@vger.kernel.org
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
* RZ/G1M (r8a7743) based iWave G20D-Q7 board and camera daughter board
- Move PCIe node out of common dtsi to allow reuse of the common dtsi
on the iWave RZ/G1N board
* RZ/G1C (r8a77470) SoC: Add I2C4, SDHI2 and SMP support
* R-Car Gen1 based boards and R-Car Gen2 SoCs:
- Enhance top-of-file comments to include SoC name
* RZ/N1D (r9a06g032) SoC:
- Correct UART0 description and add all other UARTs
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlut51oACgkQ189kaWo3
T77BKg//fhxvkarcATUM+l5hImWpPqAs2J6/+ymR2tsmY6ei8mWlKKdqHP5TCQUe
nYev93hjOP+MUmMv5Wlgz3Ql6BPyci0nzNGGp53EgADB8ku8olFDXPxykhi3InXc
MYndvUK/hTMdxP20B0Z+ALbfCWccBO7CnT2La+hHS2IkMGHwiOmYj+rXYneX29yA
vUgDY7tzg4qHHUjzWpaCtZxo7P3sD1HPFF5dxel6k8ua2gmYIhZ2NEUQTCBofMSl
186C6KN6x8YnAR3goWf4a1JgzPBlX5U8NZXBOiPgxl8kbxJniXLWtGFs323BK8Sz
09ilSM4w//HWxDK8n9LxIxzMyrMiXblQA4JPdp1q913f6xePryEEYbV2/tPI0XMM
iCnZNfkjqUE5ykADcQmNiWrZTbwxFvpT2L8YW1xspQK8yOEgy9yN/Y12Y7yWQ7jy
dbEVIcxsEm4ccTOed8v5u5SILxujMLhpwUgSvUBIVIPrxAbiO/b/AckykloXX4ej
TbNHig0TnurnDx0XBMDYcOrVnIEtNycEOiU/Dxp+uk5TxjXnTdcEMh7oCNemjm0r
ybU56U0XrMNzjVcEwLR44wCp8TPOqL4lvEXuOAgrN0biyaUWInq5NrSlHKJT667R
7zNtd/TVONUKVZm/xF7p6JGRSlazb9lDkVl9iCO8MBCvPZhGd9Q=
=xv5S
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt2-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Second Round of Renesas ARM Based SoC DT Updates for v4.20
* RZ/G1M (r8a7743) based iWave G20D-Q7 board and camera daughter board
- Move PCIe node out of common dtsi to allow reuse of the common dtsi
on the iWave RZ/G1N board
* RZ/G1C (r8a77470) SoC: Add I2C4, SDHI2 and SMP support
* R-Car Gen1 based boards and R-Car Gen2 SoCs:
- Enhance top-of-file comments to include SoC name
* RZ/N1D (r9a06g032) SoC:
- Correct UART0 description and add all other UARTs
* tag 'renesas-arm-dt2-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: iwg20d-q7-common: Move pciec node out of common dtsi
ARM: dts: r8a77470: Add I2C4 support
ARM: dts: r8a77470: Add SDHI2 support
ARM: dts: r8a77470: Add SMP support
ARM: dts: R-Car Gen1 board comment update
ARM: dts: Include R-Car Gen2 product name in DTSI files
ARM: dts: r9a06g032: Correct UART and add all other UARTs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- fix clock controller register sizes
- new board: Endless Mini (EC-100) by Endless Mobile
- add voltage regulators
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAlurT/EACgkQWTcYmtP7
xmXSGA/+PW0Z0oflNIoqwdqy5MIJ53pQjLvNzL7lzWa/l8pYFRyBC5TIatJrOUOL
QwtSnhiCH2nylzlXUwEgWhLq2Zrn/Z9NDNe3lf73alzugAnEwQ9Jzbl3TdQs4Zzu
n8hU/p8BKKkNRXdkjdu+DCd71x6lzt40oVCbQuFqLzFkE/a12GrY98OWmnAG4LWA
muP//fuIKTHd2eosRmVs2vmK3uHOq/JZUaIZJCpNC3SlIM00P5EGzLhQ+2ZoVXfm
FvSFXiSbq6E9lybrTT+exZOdR3S5tcLR+dxzMhcTksz/Ng7euQONfgTew9+UE0ko
ikZwf9KgqWih/eVX7Ut6nwOdhXHMgkw2kIf79qE93Hqt+17eCqcQY9GD5Hqk4Q6S
gDmihGZeUQKg9h0MIrqSBANryx/2TwYpVZORHDeEvT7PENgeDwN7X245fyaz+YkS
xOMPpleQXSgE9iZC+LpRcTOxjo5OuxUzaRBqRp7TTwJnZVr5+KILO58/noSFZl/P
EkzIPIpqQFaEo+mrdypkZ5LOYpfvGMUMWqyhgnFjMqmDCg2yLUEkiWbb/FX1Gb5w
DzLQ7+1ODmsnjoxuOKOTNHX/OPKmSK9ZscZJyZIXxRw8ZP6qPIyIk8AxSWojaqhB
obSMTof8gO5FH5G+wjOzZrDA/0bgtLf0Rsoo5CoieKTsY8OX5o0=
=U6kf
-----END PGP SIGNATURE-----
Merge tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt
ARM: dts: Amlogic updates for v4.20
- fix clock controller register sizes
- new board: Endless Mini (EC-100) by Endless Mobile
- add voltage regulators
* tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM: dts: meson8b: odroidc1: add stdout-path property
ARM: dts: meson8b: odroidc1: enable the SAR ADC
ARM: dts: meson8b: odroidc1: add the fixed voltage regulators
ARM: dts: meson8b: odroidc1: add the CPU voltage regulator
ARM: dts: meson8b: Add support for the Endless Mini (EC-100)
ARM: dts: meson8b: add the RMII pins
ARM: dts: meson8b: add the I2C_A, PWM_C and UART_B pins
dt-bindings: arm: amlogic: Add the Endless Mobile Endless Mini (EC-100)
dt-bindings: add vendor prefix for "Endless Mobile, Inc."
ARM: dts: meson8b: fix the clock controller register size
ARM: dts: meson8: fix the clock controller register size
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the
name enables dtc SPI bus checks.
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
PCIe is not populated by default on iWave RZ/G1N board. RZ/G1N board
is almost identical to RZ/G1M. In order to reuse the common dtsi for
both the boards, it is required to move pcie node from common dtsi
to board specific dts.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add SoC specific device tree definitions for the SDHI2 interface.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
