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93 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Conor Dooley
|
aeb71e42ca
|
dt-bindings: riscv: deprecate riscv,isa
intro ===== When the RISC-V dt-bindings were accepted upstream in Linux, the base ISA etc had yet to be ratified. By the ratification of the base ISA, incompatible changes had snuck into the specifications - for example the Zicsr and Zifencei extensions were spun out of the base ISA. Fast forward to today, and the reason for this patch. Currently the riscv,isa dt property permits only a specific subset of the ISA string - in particular it excludes version numbering. With the current constraints, it is not possible to discern whether "rv64i" means that the hart supports the fence.i instruction, for example. Future systems may choose to implement their own instruction fencing, perhaps using a vendor extension, or they may not implement the optional counter extensions. Software needs a way to determine this. versioning schemes ================== "Use the extension versions that are described in the ISA manual" you may say, and it's not like this has not been considered. Firstly, software that parses the riscv,isa property at runtime will need to contain a lookup table of some sort that maps arbitrary versions to versions it understands. There is not a consistent application of version number applied to extensions, with a higgledy-piggledy collection of tags, "bare" and versioned documents awaiting the reader on the "recently ratified extensions" page: https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions As an aside, and this is reflected in the patch too, since many extensions have yet to appear in a release of the ISA specs, they are defined by commits in their respective "working draft" repositories. Secondly, there is an issue of backwards compatibility, whereby allowing numbers in the ISA string, some parsers may be broken. This would require an additional property to be created to even use the versions in this manner. ~boolean properties~ string array property ========================================== If a new property is needed, the whole approach may as well be looked at from the bottom up. A string with limited character choices etc is hardly the best approach for communicating extension information to software. Switching to using properties that are defined on a per extension basis, allows us to define explicit meanings for the DT representation of each extension - rather than the current situation where different operating systems or other bits of software may impart different meanings to characters in the string. Clearly the best source of meanings is the specifications themselves, this just provides us the ability to choose at what point in time the meaning is set. If an extension changes incompatibility in the future, a new property will be required. Off-list, some of the RVI folks have committed to shoring up the wording in either the ISA specifications, the riscv-isa-manual or so that in the future, modifications to and additions or removals of features will require a new extension. Codifying that assertion somewhere would make it quite unlikely that compatibility would be broken, but we have the tools required to deal with it, if & when it crops up. It is in our collective interest, as consumers of extension meanings, to define a scheme that enforces compatibility. The use of individual elements, rather than a single string, will also permit validation that the properties have a meaning, as well as potentially reject mutually exclusive combinations, or enforce dependencies between extensions. That would not have be possible with the current dt-schema infrastructure for arbitrary strings, as we would need to add a riscv,isa parser to dt-validate! That's not implemented in this patch, but rather left as future work (for the brave, or the foolish). parser simplicity ================= Many systems that parse DT at runtime already implement an function that can check for the presence of a string in an array of string, as it is similar to the process for parsing a list of compatible strings, so a bunch of new, custom, DT parsing should not be needed. Getting rid of "riscv,isa" parsing would be a nice simplification, but unfortunately for backwards compatibility with old dtbs, existing parsers may not be removable - which may greatly simplify dt parsing code. In Linux, for example, checking for whether a hart supports an extension becomes as simple as: of_property_match_string(node, "riscv,isa-extensions", "zicbom") vendor extensions ================= Compared to riscv,isa, this proposed scheme promotes vendor extensions, oft touted as the strength of RISC-V, to first-class citizens. At present, extensions are defined as meaning what the RISC-V ISA specifications say they do. There is no realistic way of using that interface to provide cross-platform definitions for what vendor extensions mean. Vendor extensions may also have even less consistency than RVI do in terms of versioning, or no care about backwards compatibility. The new property allows us to assign explicit meanings on a per vendor extension basis, backed up by a description of their meanings. fin === Create a new file to store the extension meanings and a new riscv,isa-base property to replace the aspect of riscv,isa that is not represented by the new property - the base ISA implemented by a hart. As a starting point, add properties for extensions currently used in Linux. Finally, mark riscv,isa as deprecated, as removing support for it in existing programs would be an ABI break. CC: Palmer Dabbelt <palmer@dabbelt.com> CC: Paul Walmsley <paul.walmsley@sifive.com> CC: Rob Herring <robh+dt@kernel.org> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: Alistair Francis <alistair.francis@wdc.com> CC: Andrew Jones <ajones@ventanamicro.com> CC: Anup Patel <apatel@ventanamicro.com> CC: Atish Patra <atishp@atishpatra.org> CC: Jessica Clarke <jrtc27@jrtc27.com> CC: Rick Chen <rick@andestech.com> CC: Leo <ycliang@andestech.com> CC: Oleksii <oleksii.kurochko@gmail.com> CC: linux-riscv@lists.infradead.org CC: qemu-riscv@nongnu.org CC: u-boot@lists.denx.de CC: devicetree@vger.kernel.org CC: linux-kernel@vger.kernel.org Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230702-eats-scorebook-c951f170d29f@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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Linus Torvalds
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533925cb76 |
RISC-V Patches for the 6.5 Merge Window, Part 1
* Support for ACPI. * Various cleanups to the ISA string parsing, including making them case-insensitive * Support for the vector extension. * Support for independent irq/softirq stacks. * Our CPU DT binding now has "unevaluatedProperties: false" -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmSe70ATHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiWNPD/0ZfSdQ0A/gMVOzAD4zFKPEqQ6ffW2V Zy6Jo7UDNqKsiai7QA4XB1uyYIv/y1yUKJ0oeBVcA9Nzyq+TW9QDcApDBTabxAUI agY19YKw6VVZ+p7I9sMsf6EbdJdkNfSAzcQACPxb4ScEoaf9X+oAK5qgXuRuWluh qQuVkkJlgWc/t1cuUkrRdJmHQYvjP3zL7z4o344q2IVpXJkNNu0GeP+HbF8BYKcA +I/TTA5JY3kCIaxkpF2rU6pE6T5T9xrPmRYZ7bZoPUPnbL+M8As/jx3ym52Y4WGp kf8pgkxixOjU64kVJOH66CA8GaOiaAH/ptjQb0ZmCaGrHhr7aOT9HrkX4rU1lS8T stPphfM4gGPcCoPgRqSl+mEhBzjII8maOBLtbricAoQi6efRq8fzoOGaif/QpCbc 6n0LGS4nQPGVyD3rAPfHxxfrlGJR+SsgyDvjZoDhqauFglims14GnK+eBeO8zrui Aj/uuAS63VIYprJWC1NOBJlU2WKZiOGhCANpZ6W6SH21PYn2WjsVILqaGh+WN8ZO KOHxZNaN8fQag0Yg7oNAUb7l6S0DHYtJIksFnFW2Rf2+VT58RAMYRQbpbhr7Tqr+ jLgIR8PkFrBERHE49IqLGhAxGDnNzAUysMRw9pIk7WIre2Jt4wPqUdl+ee+5ErIX jiYfSFZw9q28UA== =Fpq8 -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.5-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for ACPI - Various cleanups to the ISA string parsing, including making them case-insensitive - Support for the vector extension - Support for independent irq/softirq stacks - Our CPU DT binding now has "unevaluatedProperties: false" * tag 'riscv-for-linus-6.5-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (78 commits) riscv: hibernate: remove WARN_ON in save_processor_state dt-bindings: riscv: cpus: switch to unevaluatedProperties: false dt-bindings: riscv: cpus: add a ref the common cpu schema riscv: stack: Add config of thread stack size riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACK riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACK RISC-V: always report presence of extensions formerly part of the base ISA dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support RISC-V: remove decrement/increment dance in ISA string parser RISC-V: rework comments in ISA string parser RISC-V: validate riscv,isa at boot, not during ISA string parsing RISC-V: split early & late of_node to hartid mapping RISC-V: simplify register width check in ISA string parsing perf: RISC-V: Limit the number of counters returned from SBI riscv: replace deprecated scall with ecall riscv: uprobes: Restore thread.bad_cause riscv: mm: try VMA lock-based page fault handling first riscv: mm: Pre-allocate PGD entries for vmalloc/modules area RISC-V: hwprobe: Expose Zba, Zbb, and Zbs RISC-V: Track ISA extensions per hart ... |
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Linus Torvalds
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6c1561fb90 |
ARM: SoC devicetree updates for 6.5
The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for each
SoC vendor, following the same scheme that is used on arm64, mips and
riscv. This has been discussed for many years, but so far we never did
this as there was a plan to move the files out of the kernel entirely,
which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along
with their device drivers.
* The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the time.
* Amlogic C3 is a Cortex-A35 based smart IP camera chip
* Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
* Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
* Qualcomm SDX75 is the latest generation modem chip that is used
as a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
* Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie
C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those included
there are 39 new board files, but only five more 32-bit this time, probably
a new low:
* Marantec Maveo board based on dhcor imx6ull module
* Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
* Epson Moverio BT-200 AR glasses based on TI OMAP4
* PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
* ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than
we had in the recent releases:
* Three boards based on NXP i.MX8: Emtop SoM & Baseboard,
NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice
gw7905-2x device.
* NVIDIA IGX Orin and Jetson Orin Nano boards, both based on
tegra234
* Qualcomm gains support for 6 reference boards on various members
of their IPQ networking SoC series, as well as the Sony Xperia M4
Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board
on top of the various reference platforms for their new chips.
* Rockchips support for several newer boards: Indiedroid Nova (rk3588),
Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C
Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S
(rk3568)
* TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin
family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
* continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
* support for devicetree overlays on at91, bcm283x
* significant additions to existing SoC support on mediatek, qualcomm,
ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1
As usual, a lot more detail is available in the individual merge
commits.
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Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC devicetree updates from Arnd Bergmann:
"The biggest change this time is for the 32-bit devicetree files, which
are all moved to a new location, using separate subdirectories for
each SoC vendor, following the same scheme that is used on arm64, mips
and riscv. This has been discussed for many years, but so far we never
did this as there was a plan to move the files out of the kernel
entirely, which has never happened.
The impact of this will be that all external patches no longer apply,
and anything depending on the location of the dtb files in the build
directory will have to change. The installed files after 'make
dtbs_install' keep the current location.
There are six added SoCs here that are largely variants of previously
added chips. Two other chips are added in a separate branch along with
their device drivers.
- The Samsung Exynos 4212 makes its return after the Samsung Galaxy
Express phone is addded at last. The SoC support was originally
added in 2012 but removed again in 2017 as it was unused at the
time.
- Amlogic C3 is a Cortex-A35 based smart IP camera chip
- Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of
the still common MSM8916 (Snapdragon 410) phone chip that has been
supported for a long time.
- Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end
laptop chips, used in the Lenovo Flex 5G, which is added along with
the reference board.
- Qualcomm SDX75 is the latest generation modem chip that is used as
a peripherial in phones but can also run a standalone Linux. Unlike
the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55.
- Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the
Xuantie C910 core, a step up from all previously added rv64 chips.
All of the above come with reference board implementations, those
included there are 39 new board files, but only five more 32-bit this
time, probably a new low:
- Marantec Maveo board based on dhcor imx6ull module
- Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip
- Epson Moverio BT-200 AR glasses based on TI OMAP4
- PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM
- ICnova ADB4006 board based on Allwinner A20
On the 64-bit side, there are also fewer addded machines than we had
in the recent releases:
- Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM
EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device.
- NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234
- Qualcomm gains support for 6 reference boards on various members of
their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua
phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top
of the various reference platforms for their new chips.
- Rockchips support for several newer boards: Indiedroid Nova
(rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM
NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn
Fastrhino R66S/R68S (rk3568)
- TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex
Verdin family with AM62 COM, carrier and dev boards
Other changes to existing boards contain the usual minor improvements
along with
- continued updates to clean up dts files based on dtc warnings and
binding checks, in particular cache properties and node names
- support for devicetree overlays on at91, bcm283x
- significant additions to existing SoC support on mediatek,
qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST
STM32MP1
As usual, a lot more detail is available in the individual merge
commits"
* tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits)
ARM: mvebu: fix unit address on armada-390-db flash
ARM: dts: Move .dts files to vendor sub-directories
kbuild: Support flat DTBs install
ARM: dts: Add .dts files missing from the build
ARM: dts: allwinner: Use quoted #include
ARM: dts: lan966x: kontron-d10: add PHY interrupts
ARM: dts: lan966x: kontron-d10: fix SPI CS
ARM: dts: lan966x: kontron-d10: fix board reset
ARM: dts: at91: Enable device-tree overlay support for AT91 boards
arm: dts: Enable device-tree overlay support for AT91 boards
arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller
ARM: dts: at91: use generic name for shutdown controller
ARM: dts: BCM5301X: Add cells sizes to PCIe nodes
dt-bindings: firmware: brcm,kona-smc: convert to YAML
riscv: dts: sort makefile entries by directory
riscv: defconfig: enable T-HEAD SoC
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: Add the T-HEAD SoC family Kconfig option
...
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Palmer Dabbelt
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488833ccdc
|
Merge patch series "dt-bindings: riscv: cpus: switch to unevaluatedProperties: false"
Conor Dooley <conor@kernel.org> says: From: Conor Dooley <conor.dooley@microchip.com> Do the various bits needed to drop the additionalProperties: true that we currently have in riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes. * b4-shazam-merge: dt-bindings: riscv: cpus: switch to unevaluatedProperties: false dt-bindings: riscv: cpus: add a ref the common cpu schema Link: https://lore.kernel.org/r/20230615-creamer-emu-ade0fa0bdb68@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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Palmer Dabbelt
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42b89447b6
|
Merge patch series "ISA string parser cleanups"
Conor Dooley <conor@kernel.org> says: From: Conor Dooley <conor.dooley@microchip.com> Here are some bits that were discussed with Drew on the "should we allow caps" threads that I have now created patches for: - splitting of riscv_of_processor_hartid() into two distinct functions, one for use purely during early boot, prior to the establishment of the possible-cpus mask & another to fit the other current use-cases - that then allows us to then completely skip some validation of the hartid in the parser - the biggest diff in the series is a rework of the comments in the parser, as I have mostly found the existing (sparse) ones to not be all that helpful whenever I have to go back and look at it - from writing the comments, I found a conditional doing a bit of a dance that I found counter-intuitive, so I've had a go at making that match what I would expect a little better - `i` implies 4 other extensions, so add them as extensions and set them for the craic. Sure why not like... * b4-shazam-merge: RISC-V: always report presence of extensions formerly part of the base ISA dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support RISC-V: remove decrement/increment dance in ISA string parser RISC-V: rework comments in ISA string parser RISC-V: validate riscv,isa at boot, not during ISA string parsing RISC-V: split early & late of_node to hartid mapping RISC-V: simplify register width check in ISA string parsing Link: https://lore.kernel.org/r/20230607-audacity-overhaul-82bb867a825f@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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Conor Dooley
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1ffe6ddc5c
|
dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
To permit validation of cpu nodes, swap "additionalProperties: true" out for "unevaluatedProperties: false". Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230615-viper-stoic-1ff8efd7d51d@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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Conor Dooley
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3c1b4758a9
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dt-bindings: riscv: cpus: add a ref the common cpu schema
To permit validation of RISC-V cpu nodes, "additionalProperties: true" needs to be swapped for "unevaluatedProperties: false". To facilitate this in a way that passes dt_binding_check, a reference to the cpu schema is required. Disallow the generic cache-op-block-size property that that drags in, since the RISC-V CBO extensions do not require a common size, and have individual properties. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230615-dubiously-parasail-79d34cefedce@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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Conor Dooley
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1e5cae98e4
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dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support
Similar to commit
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Krzysztof Kozlowski
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f20233852a
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dt-bindings: riscv: cpus: drop unneeded quotes
Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230609140706.64623-1-krzysztof.kozlowski@linaro.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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Jisheng Zhang
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89b0186ab5 |
dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
Several SoMs and boards are available that feature the T-HEAD TH1520 SoC. Document the compatible strings. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
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Damien Le Moal
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f7efdf5e4d |
dt-bindings: Change Damien Le Moal's contact email
Change my email address to dlemoal@kernel.org. Signed-off-by: Damien Le Moal <dlemoal@kernel.org> Link: https://lore.kernel.org/r/20230514222614.115299-1-dlemoal@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> |
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Conor Dooley
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9e320d7ca4
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dt-bindings: riscv: drop invalid comment about riscv,isa lower-case reasoning
"Ease of parsing" may have been the initial argument for keeping this string in lower-case, but parsers may have been written that expect lower-case only. For example, the one in released kernels currently does not behave correctly for multi-letter extensions that begin with a capital letter. Allowing upper-case here brings about no benefit but would break compatibility between new devicetrees and older kernels. Drop the comment to avoid confusing people. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Yangyu Chen <cyy@cyyself.name> Link: https://lore.kernel.org/r/tencent_3B8290DDC66D3E624132ED39C7465CDC9807@qq.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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Conor Dooley
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41ebfc91f7
|
dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support
The dt-binding was defined before the extraction of csr access and fence.i into their own extensions, and thus the presence of the I base extension implies Zicsr and Zifencei. There's no harm in adding them obviously, but for backwards compatibility with DTs that existed prior to that extraction, software is unable to differentiate between "i" and "i_zicsr_zifencei" without any further information. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230427-fence-blurred-c92fb69d4137@wendy Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
||
|
Linus Torvalds
|
89d77f71f4 |
RISC-V Patches for the 6.4 Merge Window, Part 1
* Support for runtime detection of the Svnapot extension. * Support for Zicboz when clearing pages. * We've moved to GENERIC_ENTRY. * Support for !MMU on rv32 systems. * The linear region is now mapped via huge pages. * Support for building relocatable kernels. * Support for the hwprobe interface. * Various fixes and cleanups throughout the tree. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmRL5rcTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYibpcD/0RnmO+N2OJxsJXf0KtHv4LlChAFaMZ mfcsU8lv8r3Rz1USJGyVoE57885R+iUw1664ic6Gj9Ll9/A+BDVyqlNeo1BZ7nnv 6hZawSh8XGMyCJoatjaCSMW6VKObsSpHXLoA0mxtj06w1XhtpUnzjv4SZQqBYxC2 7+/cfy6l3uGdSKQ0R402sF8PE+l3HthhO+Cw9NYHQZisAHEQrfFpXRnrovhs+vX0 aVxoWo8bmIhhNke2jh6dnGhfFfAs+UClbaKgZfe8af6feboo+Tal3+OibiEy1K1j hDQ3w/G5jAdwSqnNPdXzpk4srskUOhP9is8AG79vCasMxybQIBfZcc7/kLmmQX+2 xt1EoDVD/lSO1p+CWRautLXEsInWbpBYaSJie7WcR4SHe8S7/nomTDlwkJHx5cma mkSYHJKNwCbamDTI3gXg8nrScbxsRnJQsQUolFDwAeRz7AYVwtqVh8VxAWqAdU3q xUNKrUpCAzNC3d5GL7pmRfZrqjpQhuFXkHFSy85vaCPuckBu926OzxpKBmX4Kea1 qLYWfxv78bcwuY47FWJKcd97Ib63iBYDgarJxvrHrwDaHV2xjBOmdapNPUc2PswT a938enbYYnJHIbuSmbeNBPF4iF6nKUXshyfZu7tCZl6MzsXloUckGdm++j97Bpvr g6G3ZP6STSQBmw== =oxQd -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for runtime detection of the Svnapot extension - Support for Zicboz when clearing pages - We've moved to GENERIC_ENTRY - Support for !MMU on rv32 systems - The linear region is now mapped via huge pages - Support for building relocatable kernels - Support for the hwprobe interface - Various fixes and cleanups throughout the tree * tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (57 commits) RISC-V: hwprobe: Explicity check for -1 in vdso init RISC-V: hwprobe: There can only be one first riscv: Allow to downgrade paging mode from the command line dt-bindings: riscv: add sv57 mmu-type RISC-V: hwprobe: Remove __init on probe_vendor_features() riscv: Use --emit-relocs in order to move .rela.dyn in init riscv: Check relocations at compile time powerpc: Move script to check relocations at compile time in scripts/ riscv: Introduce CONFIG_RELOCATABLE riscv: Move .rela.dyn outside of init to avoid empty relocations riscv: Prepare EFI header for relocatable kernels riscv: Unconditionnally select KASAN_VMALLOC if KASAN riscv: Fix ptdump when KASAN is enabled riscv: Fix EFI stub usage of KASAN instrumented strcmp function riscv: Move DTB_EARLY_BASE_VA to the kernel address space riscv: Rework kasan population functions riscv: Split early and final KASAN population functions riscv: Use PUD/P4D/PGD pages for the linear mapping riscv: Move the linear mapping creation in its own function riscv: Get rid of riscv_pfn_base variable ... |
||
|
Linus Torvalds
|
d42b1c4757 |
Devicetree updates for v6.4, part 1:
Bindings:
- Convert Qcom IOMMU, Amlogic timer, Freescale sec-v4.0, Toshiba
TC358764 display bridge, Parade PS8622 display bridge, and Xilinx
FPGA bindings to DT schema format
- Add qdu1000 and sa8775p SoC support to Qcom PDC interrupt controller
- Add MediaTek MT8365 UART and SYSIRQ bindings
- Add Arm Cortex-A78C and X1C core compatibles
- Add vendor prefix for Novatek
- Remove bindings for stih415, sti416, stid127 platforms
- Drop uneeded quotes in schema files. This is preparation for yamllint
checking quoting for us.
- Add missing (unevaluated|additional)Properties constraints on child
node schemas
- Clean-up schema comments formatting
- Fix I2C and SPI node bus names in schema examples
- Clean-up some display compatibles schema syntax
- Fix incorrect references to lvds.yaml
- Gather all cache controller bindings in a common directory
DT core:
- Convert unittest to new void .remove platform device hook
- kerneldoc fixes for DT address of_pci_range_to_resource/
of_address_to_resource functions
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Merge tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"Bindings:
- Convert Qcom IOMMU, Amlogic timer, Freescale sec-v4.0, Toshiba
TC358764 display bridge, Parade PS8622 display bridge, and Xilinx
FPGA bindings to DT schema format
- Add qdu1000 and sa8775p SoC support to Qcom PDC interrupt
controller
- Add MediaTek MT8365 UART and SYSIRQ bindings
- Add Arm Cortex-A78C and X1C core compatibles
- Add vendor prefix for Novatek
- Remove bindings for stih415, sti416, stid127 platforms
- Drop uneeded quotes in schema files. This is preparation for
yamllint checking quoting for us.
- Add missing (unevaluated|additional)Properties constraints on child
node schemas
- Clean-up schema comments formatting
- Fix I2C and SPI node bus names in schema examples
- Clean-up some display compatibles schema syntax
- Fix incorrect references to lvds.yaml
- Gather all cache controller bindings in a common directory
DT core:
- Convert unittest to new void .remove platform device hook
- kerneldoc fixes for DT address of_pci_range_to_resource/
of_address_to_resource functions"
* tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits)
dt-bindings: rng: Drop unneeded quotes
dt-bindings: arm/soc: mediatek: Drop unneeded quotes
dt-bindings: soc: qcom: Drop unneeded quotes
dt-bindings: i2c: samsung: Fix 'deprecated' value
dt-bindings: display: Fix lvds.yaml references
dt-bindings: display: simplify compatibles syntax
dt-bindings: display: mediatek: simplify compatibles syntax
dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references
dt-bindings: timer: Drop unneeded quotes
dt-bindings: interrupt-controller: qcom,pdc: document qcom,qdu1000-pdc
dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
dt-bindings: reset: remove stih415/stih416 reset
dt-bindings: net: dwmac: sti: remove stih415/sti416/stid127
dt-bindings: irqchip: sti: remove stih415/stih416 and stid127
dt-bindings: iommu: Convert QCOM IOMMU to YAML
dt-bindings: irqchip: ti,sci-inta: Add optional power-domains property
dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas
of: address: Reshuffle to remove forward declarations
of: address: Fix documented return value of of_pci_range_to_resource()
of: address: Document return value of of_address_to_resource()
...
|
||
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Conor Dooley
|
d4dda690b4
|
dt-bindings: riscv: add sv57 mmu-type
Dumping the dtb from new versions of QEMU warns that sv57 is an undocumented mmu-type. The kernel has supported sv57 for about a year, so bring it into the fold. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230424-rival-habitual-478567c516f0@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
||
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Arnd Bergmann
|
8f09b5ec41 |
- added D1 crypto node
- enabled DVFS on OrangePi PC2 board - added GPIO line names on Nezha D1 board - added suniv USB nodes and enabled on licheepi-nano - new suniv boards: PopStick v1.1 and Lctech Pi - added Allwinner T113-s DTSI - added MangoPi MQ-R T113-s board variant - swapped DMA names for A23, A31, A33, D1, H3, H5, V3s -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSPRixG1tysKC2PKM10Ba7+DO8kkwUCZDFhwAAKCRB0Ba7+DO8k k4J/AP0UdafVPx8HFMiXUBABSdrSVvwDWDhXcqeMiWQXZ6UWogEA7gUTOZ+ZFr2u /GDOiM0CscDyQlbHWEYx5tkAhfBUnQU= =Sv3O -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmQ5dGQACgkQYKtH/8kJ UicCgA//fqzpR1CLYH4xCF6jIiVtTEPAEU615BA+AJAWg9mACWALutARbTmvOfJo jUpCyNsVV6vCH1kGLBj36FgkVOTid691Q7lEo4lrR8Mg9hV3S+rBlbgbMD6LRX54 qSmvDVxKh3AFcDvbfxBYMKRBo+kq4samrbin0W+7E6C7Q9hqEzDGMgMRTrAGyRiF H3w6Anjbm8jdUddMGHTNveGVJZG8VDKAdOeDVzvQMACg83S4CgQWSyH/AQhq0OtG kpCMS+d3/0ElO6to0yXt5BlrsfqqmFk2lc9ovDfVUU3Z+uNOfc+V83w2mqt8+jeF Y2+kptB0LeEWwqDxFJeAHPIztPlhfZeqszsbzfAPoxhbqg1FyHGqtdsuAj/I82TD dnDVoipEWJHOf3Go3TDgz9fetsRidett0ZfAxQy2Z1/5NTRDNfFY2hSJbf1haEvO 4BOm8ZpVDHPY/wMbinu+4kiFmzu6eVMUITkdNjYAzx5W5TkPK7comTNhDe3k97dD gWyToAsAjbs6jxsRYI4M9DP7y0YR8hFuOIOMt1dibXn/S2VkteboBhID8hxl1fuY yf0p7PWkyk5ev9r6+vZScmlwDqfNXingd9Bdmr5xaRl4kIKCVO6oDJpoQT/O2dY8 kY3YIklnbJgiDsgNFJNSYqWMI+xFO8aQQDZFmDf5Wh2/3qWnvWc= =Dm8i -----END PGP SIGNATURE----- Merge tag 'sunxi-dt-for-6.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - added D1 crypto node - enabled DVFS on OrangePi PC2 board - added GPIO line names on Nezha D1 board - added suniv USB nodes and enabled on licheepi-nano - new suniv boards: PopStick v1.1 and Lctech Pi - added Allwinner T113-s DTSI - added MangoPi MQ-R T113-s board variant - swapped DMA names for A23, A31, A33, D1, H3, H5, V3s * tag 'sunxi-dt-for-6.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sunxi: h3/h5: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sun8i: v3s: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sun8i: a23/a33: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sun6i: a31: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sunxi: add MangoPi MQ-R-T113 board dt-bindings: arm: sunxi: document MangoPi MQ-R board names ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi dts: add riscv include prefix link ARM: dts: suniv: Add Lctech Pi F1C200s devicetree ARM: dts: suniv: add device tree for PopStick v1.1 dt-binding: arm: sunxi: add two board compatible strings dt-bindings: vendor-prefixes: add Source Parts and Lctech names ARM: dts: suniv: licheepi-nano: enable USB ARM: dts: suniv: add USB-related device nodes riscv: dts: nezha-d1: add gpio-line-names arm64: dts: allwinner: h5: OrangePi PC2: add OPP table to enable DVFS riscv: dts: allwinner: d1: Add crypto engine node Link: https://lore.kernel.org/r/20230408125156.GA17050@jernej-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Hal Feng
|
8868caa2a0 |
dt-bindings: riscv: Add SiFive S7 compatible
Add a new compatible string in cpu.yaml for SiFive S7 CPU core which is used on SiFive U74-MC core complex etc. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Conor Dooley
|
dc8ea9204b |
dt-bindings: move cache controller bindings to a cache directory
There's a bunch of bindings for (mostly l2) cache controllers scattered to the four winds, move them to a common directory. I renamed the freescale l2cache.txt file, as while that might make sense when the parent dir is fsl, it's confusing after the move. The two Marvell bindings have had a "marvell," prefix added to match their compatibles. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230330173255.109731-1-conor@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> |
||
|
Andre Przywara
|
c908060de3 |
dt-bindings: arm: sunxi: document MangoPi MQ-R board names
The MangoPi MQ-R board is a small development board, using Allwinner SoCs with co-packaged DRAM. There are versions with a RISC-V core and ones with two Arm Cortex-A7 cores. Add the board/SoC compatible string pair to the list of known boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230320005249.13403-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> |
||
|
Andrew Jones
|
ea20f117ab
|
dt-bindings: riscv: Document cboz-block-size
The Zicboz operation (cbo.zero) operates on a block-size defined for the cpu-core. While we already have the riscv,cbom-block-size property, it only provides the block size for Zicbom operations. Even though it's likely Zicboz and Zicbom will use the same size, that's not required by the specification. Create another property specifically for Zicboz. Cc: Rob Herring <robh@kernel.org> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230224162631.405473-4-ajones@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
||
|
Linus Torvalds
|
11c7052998 |
ARM: SoC drivers for 6.3
As usual, there are lots of minor driver changes across SoC platforms
from NXP, Amlogic, AMD Zynq, Mediatek, Qualcomm, Apple and Samsung.
These usually add support for additional chip variations in existing
drivers, but also add features or bugfixes.
The SCMI firmware subsystem gains a unified raw userspace interface
through debugfs, which can be used for validation purposes.
Newly added drivers include:
- New power management drivers for StarFive JH7110, Allwinner D1 and
Renesas RZ/V2M
- A driver for Qualcomm battery and power supply status
- A SoC device driver for identifying Nuvoton WPCM450 chips
- A regulator coupler driver for Mediatek MT81xxv
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Merge tag 'soc-drivers-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann:
"As usual, there are lots of minor driver changes across SoC platforms
from NXP, Amlogic, AMD Zynq, Mediatek, Qualcomm, Apple and Samsung.
These usually add support for additional chip variations in existing
drivers, but also add features or bugfixes.
The SCMI firmware subsystem gains a unified raw userspace interface
through debugfs, which can be used for validation purposes.
Newly added drivers include:
- New power management drivers for StarFive JH7110, Allwinner D1 and
Renesas RZ/V2M
- A driver for Qualcomm battery and power supply status
- A SoC device driver for identifying Nuvoton WPCM450 chips
- A regulator coupler driver for Mediatek MT81xxv"
* tag 'soc-drivers-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits)
power: supply: Introduce Qualcomm PMIC GLINK power supply
soc: apple: rtkit: Do not copy the reg state structure to the stack
soc: sunxi: SUN20I_PPU should depend on PM
memory: renesas-rpc-if: Remove redundant division of dummy
soc: qcom: socinfo: Add IDs for IPQ5332 and its variant
dt-bindings: arm: qcom,ids: Add IDs for IPQ5332 and its variant
dt-bindings: power: qcom,rpmpd: add RPMH_REGULATOR_LEVEL_LOW_SVS_L1
firmware: qcom_scm: Move qcom_scm.h to include/linux/firmware/qcom/
MAINTAINERS: Update qcom CPR maintainer entry
dt-bindings: firmware: document Qualcomm SM8550 SCM
dt-bindings: firmware: qcom,scm: add qcom,scm-sa8775p compatible
soc: qcom: socinfo: Add Soc IDs for IPQ8064 and variants
dt-bindings: arm: qcom,ids: Add Soc IDs for IPQ8064 and variants
soc: qcom: socinfo: Add support for new field in revision 17
soc: qcom: smd-rpm: Add IPQ9574 compatible
soc: qcom: pmic_glink: remove redundant calculation of svid
soc: qcom: stats: Populate all subsystem debugfs files
dt-bindings: soc: qcom,rpmh-rsc: Update to allow for generic nodes
soc: qcom: pmic_glink: add CONFIG_NET/CONFIG_OF dependencies
soc: qcom: pmic_glink: Introduce altmode support
...
|
||
|
Linus Torvalds
|
01687e7c93 |
RISC-V Patches for the 6.3 Merge Window, Part 1
There's a bunch of fixes/cleanups throughout the tree as usual, but we
also have a handful of new features.
* Various improvements to the extension detection and alternative
patching infrastructure.
* Zbb-optimized string routines.
* Support for cpu-capacity in the RISC-V DT bindings.
* Zicbom no longer depends on toolchain support.
* Some performance and code size improvements to ftrace.
* Support for ARCH_WANT_LD_ORPHAN_WARN.
* Oops now contain the faulting instruction.
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Merge tag 'riscv-for-linus-6.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
"There's a bunch of fixes/cleanups throughout the tree as usual, but we
also have a handful of new features:
- Various improvements to the extension detection and alternative
patching infrastructure
- Zbb-optimized string routines
- Support for cpu-capacity in the RISC-V DT bindings
- Zicbom no longer depends on toolchain support
- Some performance and code size improvements to ftrace
- Support for ARCH_WANT_LD_ORPHAN_WARN
- Oops now contain the faulting instruction"
* tag 'riscv-for-linus-6.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (67 commits)
RISC-V: add a spin_shadow_stack declaration
riscv: mm: hugetlb: Enable ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
riscv: Add header include guards to insn.h
riscv: alternative: proceed one more instruction for auipc/jalr pair
riscv: Avoid enabling interrupts in die()
riscv, mm: Perform BPF exhandler fixup on page fault
RISC-V: take text_mutex during alternative patching
riscv: hwcap: Don't alphabetize ISA extension IDs
RISC-V: fix ordering of Zbb extension
riscv: jump_label: Fixup unaligned arch_static_branch function
RISC-V: Only provide the single-letter extensions in HWCAP
riscv: mm: fix regression due to update_mmu_cache change
scripts/decodecode: Add support for RISC-V
riscv: Add instruction dump to RISC-V splats
riscv: select ARCH_WANT_LD_ORPHAN_WARN for !XIP_KERNEL
riscv: vmlinux.lds.S: explicitly catch .init.bss sections from EFI stub
riscv: vmlinux.lds.S: explicitly catch .riscv.attributes sections
riscv: vmlinux.lds.S: explicitly catch .rela.dyn symbols
riscv: lds: define RUNTIME_DISCARD_EXIT
RISC-V: move some stray __RISCV_INSN_FUNCS definitions from kprobes
...
|
||
|
Linus Torvalds
|
8395d932d2 |
Devicetree updates for v6.3:
DT core:
- Add node lifecycle unit tests
- Add of_property_present() helper aligned with fwnode API
- Print more information on reserved regions on boot
- Update dtc to upstream v1.6.1-66-gabbd523bae6e
- Use strscpy() to instead of strncpy() in DT core
- Add option for schema validation on %.dtb targets
Bindings:
- Add/fix support for listing multiple patterns in DT_SCHEMA_FILES
- Rework external memory controller/bus bindings to properly support
controller specific child node properties
- Convert loongson,ls1x-intc, fcs,fusb302, sil,sii8620, Rockchip RK3399
PCIe, Synquacer I2C, and Synquacer EXIU bindings to DT schema format
- Add RiscV SBI PMU event mapping binding
- Add missing contraints on Arm SCMI child node allowed properties
- Add a bunch of missing Socionext UniPhier glue block bindings and
example fixes
- Various fixes for duplicate or conflicting type definitions on DT
properties
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Merge tag 'devicetree-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT core:
- Add node lifecycle unit tests
- Add of_property_present() helper aligned with fwnode API
- Print more information on reserved regions on boot
- Update dtc to upstream v1.6.1-66-gabbd523bae6e
- Use strscpy() to instead of strncpy() in DT core
- Add option for schema validation on %.dtb targets
Bindings:
- Add/fix support for listing multiple patterns in DT_SCHEMA_FILES
- Rework external memory controller/bus bindings to properly support
controller specific child node properties
- Convert loongson,ls1x-intc, fcs,fusb302, sil,sii8620, Rockchip
RK3399 PCIe, Synquacer I2C, and Synquacer EXIU bindings to DT
schema format
- Add RiscV SBI PMU event mapping binding
- Add missing contraints on Arm SCMI child node allowed properties
- Add a bunch of missing Socionext UniPhier glue block bindings and
example fixes
- Various fixes for duplicate or conflicting type definitions on DT
properties"
* tag 'devicetree-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (66 commits)
dt-bindings: regulator: Add mps,mpq7932 power-management IC
of: dynamic: Fix spelling mistake "kojbect" -> "kobject"
dt-bindings: drop Sagar Kadam from SiFive binding maintainership
dt-bindings: sram: qcom,imem: document sm8450
dt-bindings: interrupt-controller: convert loongson,ls1x-intc.txt to json-schema
dt-bindings: arm: Add Cortex-A715 and X3
of: dynamic: add lifecycle docbook info to node creation functions
of: add consistency check to of_node_release()
of: do not use "%pOF" printk format on node with refcount of zero
of: unittest: add node lifecycle tests
of: update kconfig unittest help
of: add processing of EXPECT_NOT to of_unittest_expect
of: prepare to add processing of EXPECT_NOT to of_unittest_expect
of: Use preferred of_property_read_* functions
of: Use of_property_present() helper
of: Add of_property_present() helper
of: reserved_mem: Use proper binary prefix
dt-bindings: Fix multi pattern support in DT_SCHEMA_FILES
of: reserved-mem: print out reserved-mem details during boot
dt-bindings: serial: restrict possible child node names
...
|
||
|
Conor Dooley
|
fb4b06f521 |
dt-bindings: drop Sagar Kadam from SiFive binding maintainership
Sagar's email listed in maintainers is bouncing as his division was sold off by the company. I attempted to contact him some days ago on what the bounce email told me was his new contact information, but am yet to receive a response. Paul and Palmer are listed on each of the bindings, both of whom were alive & well as of Wednesday so the bindings remain maintained. CC: Sagar Kadam <sagar.kadam@openfive.com> CC: Sagar Kadam <sagar.kadam@sifive.com> Link: https://lore.kernel.org/all/785425ca-4000-a7e4-16d6-4d68c91b158d@kernel.org/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230217180035.39658-1-conor@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> |
||
|
Linus Torvalds
|
950b6662e2 |
SoC: DT changes for 6.3
About a quarter of the changes are for 32-bit arm, mostly filling in
device support for existing machines and adding minor cleanups, mostly
for Qualcomm and Samsung based machines.
Two new 32-bit SoCs are added, both are quad-core Cortex-A7 chips from
Rockchips that have been around for a while but were lacking kernel
support so far: RV1126 is a Vision SoC with an NPU and is used in the
Edgeble Neural Compute Module 2(Neu2) board, while RK3128 is design for
TV boxes and so far only comes with a dts for its refernece design.
The other 32-bit boards that were added are two ASpeed AST2600 based BMC
boards, the Microchip sam9x60_curiosity development board (Armv5 based!),
the Enclustra PE1 FPGA-SoM baseboard, and a few more boards for i.MX53
and i.MX6ULL.
On the RISC-V side, there are fewer patches, but a total of ten new
single-board computers based on variations of the Allwinner D1/T113 chip,
plus one more board based on Microchip Polarfire.
As usual, arm64 has by far the most changes here, with over 700 non-merge
changesets, among them over 400 alone for Qualcomm. The newly added SoCs
this time are all recent high-end embedded SoCs for various markets,
each on comes with support for its reference board:
- Qualcomm SM8550 (Snapdragon 8 Gen 2) for mobile phones
- Qualcomm QDU1000/QRU1000 5G RAN platform
- Rockchips RK3588/RK3588s for tablets, chromebooks and SBCs
- TI J784S4 for industrial and automotive applications
In total, there are 46 new arm64 machines:
- Reference platforms for each of the five new SoCs
- Three Amlogic based development boards
- Six embedded machines based on NXP i.MX8MM and i.MX8MP
- The Mediatek mt7986a based Banana Pi R3 router
- Six tablets based on Qualcomm MSM8916 (Snapdragon 410),
SM6115 (Snapdragon 662) and SM8250 (Snapdragon 865)
- Two LTE dongles, also based on MSM8916
- Seven mobile phones, based on Qualcomm MSM8953 (Snapdragon 610),
SDM450 and SDM632
- Three chromebooks based on Qualcomm SC7280 (Snapdragon 7c)
- Nine development boards based on Rockchips RK3588, RK3568,
RK3566 and RK3328.
- Five development machines based on TI K3 (AM642/AM654/AM68/AM69)
The cleanup of dtc warnings continues across all platforms, adding
to the total number of changes.
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Merge tag 'soc-dt-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC DT updates from Arnd Bergmann:
"About a quarter of the changes are for 32-bit arm, mostly filling in
device support for existing machines and adding minor cleanups, mostly
for Qualcomm and Samsung based machines.
Two new 32-bit SoCs are added, both are quad-core Cortex-A7 chips from
Rockchips that have been around for a while but were lacking kernel
support so far: RV1126 is a Vision SoC with an NPU and is used in the
Edgeble Neural Compute Module 2(Neu2) board, while RK3128 is design
for TV boxes and so far only comes with a dts for its refernece
design.
The other 32-bit boards that were added are two ASpeed AST2600 based
BMC boards, the Microchip sam9x60_curiosity development board (Armv5
based!), the Enclustra PE1 FPGA-SoM baseboard, and a few more boards
for i.MX53 and i.MX6ULL.
On the RISC-V side, there are fewer patches, but a total of ten new
single-board computers based on variations of the Allwinner D1/T113
chip, plus one more board based on Microchip Polarfire.
As usual, arm64 has by far the most changes here, with over 700
non-merge changesets, among them over 400 alone for Qualcomm. The
newly added SoCs this time are all recent high-end embedded SoCs for
various markets, each on comes with support for its reference board:
- Qualcomm SM8550 (Snapdragon 8 Gen 2) for mobile phones
- Qualcomm QDU1000/QRU1000 5G RAN platform
- Rockchips RK3588/RK3588s for tablets, chromebooks and SBCs
- TI J784S4 for industrial and automotive applications
In total, there are 46 new arm64 machines:
- Reference platforms for each of the five new SoCs
- Three Amlogic based development boards
- Six embedded machines based on NXP i.MX8MM and i.MX8MP
- The Mediatek mt7986a based Banana Pi R3 router
- Six tablets based on Qualcomm MSM8916 (Snapdragon 410), SM6115
(Snapdragon 662) and SM8250 (Snapdragon 865)
- Two LTE dongles, also based on MSM8916
- Seven mobile phones, based on Qualcomm MSM8953 (Snapdragon 610),
SDM450 and SDM632
- Three chromebooks based on Qualcomm SC7280 (Snapdragon 7c)
- Nine development boards based on Rockchips RK3588, RK3568, RK3566
and RK3328.
- Five development machines based on TI K3 (AM642/AM654/AM68/AM69)
The cleanup of dtc warnings continues across all platforms, adding to
the total number of changes"
* tag 'soc-dt-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (1035 commits)
dt-bindings: riscv: correct starfive visionfive 2 compatibles
ARM: dts: socfpga: Add enclustra PE1 devicetree
dt-bindings: altera: Add enclustra mercury PE1
arm64: dts: qcom: msm8996: align RPM G-Link clock-controller node with bindings
arm64: dts: qcom: qcs404: align RPM G-Link node with bindings
arm64: dts: qcom: ipq6018: align RPM G-Link node with bindings
arm64: dts: qcom: sm8550: remove invalid interconnect property from cryptobam
arm64: dts: qcom: sc7280: Adjust zombie PWM frequency
arm64: dts: qcom: sc8280xp-pmics: Specify interrupt parent explicitly
arm64: dts: qcom: sm7225-fairphone-fp4: enable remaining i2c busses
arm64: dts: qcom: sm7225-fairphone-fp4: move status property down
arm64: dts: qcom: pmk8350: Use the correct PON compatible
arm64: dts: qcom: sc8280xp-x13s: Enable external display
arm64: dts: qcom: sc8280xp-crd: Introduce pmic_glink
arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks
arm64: dts: qcom: sm8350-hdk: enable GPU
arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes
arm64: dts: qcom: sm8350: finish reordering nodes
arm64: dts: qcom: sm8350: move more nodes to correct place
arm64: dts: qcom: sm8350: reorder device nodes
...
|
||
|
Conor Dooley
|
e43efb6d71
|
dt-bindings: riscv: correct starfive visionfive 2 compatibles
Using "va" and "vb" doesn't match what's written on the board, or the
communications from StarFive.
Switching to using the silkscreened version number will ease confusion &
the risk of another spin of the board containing a "conflicting" version
identifier.
As the binding has not made it into mainline yet, take the opportunity
to "correct" things.
Suggested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Link: https://lore.kernel.org/linux-riscv/Y+4AxDSDLyL1WAqh@wendy/
Fixes:
|
||
|
Conor Dooley
|
991994509e
|
dt-bindings: riscv: add a capacity-dmips-mhz cpu property
Since commit
|
||
|
Arnd Bergmann
|
ffe4bd3db8 |
- introduce Allwinner D1 DTSI
- add boards: Dongshan Nezha STU, MangoPi MQ (Pro), Sipeed Lichee RV, Nezha - add D1 power controller node - Add SATA regulator to Bananapi M3 - fix regulator reference for nanopi-duo2 - fix GPIO node names - align HDMI CEC node name for h3-beelink-x2 - add DPHY interrupt to A64 and A33 -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSPRixG1tysKC2PKM10Ba7+DO8kkwUCY9RVEwAKCRB0Ba7+DO8k kxOPAP91Bp2oGLEETbHRdytQ13SrgPhuvvz4WS1uITIc/VKS0AEAhZmwAZc4gUjd xczXP58T08vFH8CVf2hyGW3vyHX1cwI= =/7zT -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmPYOdwACgkQmmx57+YA GNmuHg/7B+KIcl+slzhtIApKbEouiqK2sEAemkmrMKdMXBMf02Vl27MHZZMajb1b B4hva6xzV2UOxOJ9e8THo1e28ciQnKBU1EqBKRJhGrBfiQweXFe97JO2vU+MhKsB 3pEzZfGfwuaOp9fjyYGoXZM/mVxjYqfy5tevUzTmOLhTxQiapu+xRaFmHUWgVXS9 fYnlDs0/PPVYbIvSmIfArd8nGfcl/RD99TGm9LOhGjdr3r3LAjrDhxCXkgJi2JyP nWJ2DxlUUXcaslb4ulvErZ+XfQJ+dhoGRsHwhnSFAige24CL2xbzbIHKyIHSTDl3 GT9FxOrJkZjHY7q2WK28w2cUGKwF1fYsNqLXqWs0GMYQSNlxR6eGyeV5HW2gh7xg xmxqzDl2I7YpuxJkf520y9rsWmy7qbM8piM1CwdQMDY6fUBcGryEZJUg6uEaEQw9 FgnqoNdqB6GAjHN6XYtxcQmivUhJA8Jk1zUSdIv4QmWy6M+tseVuKnNxwxwFL/Ab z3uguUCVxOXHKazvs+6LcE+iHUu1S1TjFjGuQQ3TN+TETKeDpn0AwB4/6WJMkbCE rCJ3O8ku7dD3tsp76GCSP6jxT/97b3uEPfcCuZZoBtToy3s8IMBvYFEB8wMftZxp SPeCPiGBYNAmxDIfbTdwwZc9abfJZcLB3/XDlpSpIguLmqdxhJs= =lSwT -----END PGP SIGNATURE----- Merge tag 'sunxi-dt-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt - introduce Allwinner D1 DTSI - add boards: Dongshan Nezha STU, MangoPi MQ (Pro), Sipeed Lichee RV, Nezha - add D1 power controller node - Add SATA regulator to Bananapi M3 - fix regulator reference for nanopi-duo2 - fix GPIO node names - align HDMI CEC node name for h3-beelink-x2 - add DPHY interrupt to A64 and A33 * tag 'sunxi-dt-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: riscv: dts: allwinner: d1: Add power controller node riscv: Add the Allwinner SoC family Kconfig option riscv: dts: allwinner: Add Dongshan Nezha STU devicetree riscv: dts: allwinner: Add MangoPi MQ Pro devicetree riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree riscv: dts: allwinner: Add MangoPi MQ devicetree riscv: dts: allwinner: Add the D1/D1s SoC devicetree dt-bindings: riscv: Add Allwinner D1/D1s board compatibles dt-bindings: vendor-prefixes: Add Allwinner D1/D1s board vendors MAINTAINERS: Match the sun20i family of Allwinner SoCs ARM: dts: sun8i: a83t: bananapi-m3: describe SATA disk regulator ARM: dts: sun8i: nanopi-duo2: Fix regulator GPIO reference ARM: dts: sunxi: Fix GPIO LED node names ARM: dts: sun8i: h3-beelink-x2: align HDMI CEC node names with dtschema arm64: dts: allwinner: a64: Add DPHY interrupt ARM: dts: sun8i: a33: Add DPHY interrupt Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
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Samuel Holland
|
a0097fec3b |
dt-bindings: riscv: Add Allwinner D1/D1s board compatibles
Several SoMs and boards are available that feature the Allwinner D1 or D1s SoC. Document their compatible strings. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230126045738.47903-4-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> |
||
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Conor Dooley
|
d9c36d016f |
Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM"
As it says on the tin, add a DT for this board. It's been sitting on my desk for a while, so may as well have it upstream... The DT is only partially complete, as it needs the fabric content added. Unfortunately, I don't have a reference design in RTL or SmartDesign for it and therefore don't know what that fabric content is. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
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Conor Dooley
|
ea913d8865 |
dt-bindings: riscv: microchip: document the Aldec TySoM
The TySOM-M-MPFS250 is a compact SoC prototyping board featuring a Microchip PolarFire SoC MPFS250T-FCG1152. Document rev2 of this board. Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250 Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
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Palmer Dabbelt
|
6710e07f01
|
Merge patch series "riscv,isa fixups"
Conor Dooley <conor@kernel.org> says: From: Conor Dooley <conor.dooley@microchip.com> I noticed ~today~ while looking at the isa manual that I had not accounted for another couple of edge cases with my regex. As before, I think attempting to validate the canonical order for multiletter stuff makes no sense - but we should totally try to avoid false-positives for combinations that are known to be valid. * b4-shazam-merge: dt-bindings: riscv: fix single letter canonical order dt-bindings: riscv: fix underscore requirement for multi-letter extensions Link: https://lore.kernel.org/r/20221205174459.60195-1-conor@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
||
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Conor Dooley
|
a943385aa8
|
dt-bindings: riscv: fix single letter canonical order
I used the wikipedia table for ordering extensions when updating the pattern here in commit |
||
|
Conor Dooley
|
ec64efc496
|
dt-bindings: riscv: fix underscore requirement for multi-letter extensions
The RISC-V ISA Manual allows the first multi-letter extension to avoid
a leading underscore. Underscores are only required between multi-letter
extensions.
The dt-binding does not validate that a multi-letter extension is
canonically ordered, as that'd need an even worse regex than is here,
but it should not fail validation for valid ISA strings.
Allow the first multi-letter extension to appear immediately after
the single-letter extensions.
Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
Fixes:
|
||
|
Emil Renner Berthing
|
1caf002efa |
dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
This cache controller is also used on the StarFive JH7110 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Emil Renner Berthing
|
97b7ed0727 |
dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
Add device tree bindings for the StarFive JH7110 RISC-V SoC and the VisionFive 2 board equipped with it. VisionFive 2 board has version A and version B, which are different in gmac and phy chip. The version A board has one 1000Mbps and one 100Mbps Ethernet ports while the version B board has two 1000Mbps Ethernet ports. Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
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Krzysztof Kozlowski
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3367934dd3 |
dt-bindings: drop redundant part of title (manual)
The Devicetree bindings document does not have to say in the title that it is a "Devicetree binding" or a "schema", but instead just describe the hardware. Manual updates to various binding titles, including capitalizing them. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC Acked-by: Stephen Boyd <sboyd@kernel.org> # clk Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> # opp Link: https://lore.kernel.org/r/20221216163815.522628-10-krzysztof.kozlowski@linaro.org [robh: add trivial-devices.yaml and net/can/microchip,mcp251xfd.yaml] Signed-off-by: Rob Herring <robh@kernel.org> |
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Arnd Bergmann
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6721cf8585 |
RISC-V DeviceTrees for v6.2
dt-bindings: - new compatibles to support the StarFive VisionFive & thead CPU cores - a fix for the PolarFire SoC's pwm binding, merged through my tree as suggested by the PWM maintainers Microchip: - Non-urgent fix for the node address not matches the reg in a way that the checkers don't complain about - Add GPIO controlled LEDs for Icicle - Support for the "CCC" clocks in the FPGA fabric. Previously these used fixed-frequency clocks in the dt, but if which CCC is in use is known, as in the v2022.09 Icicle Kit Reference Design, the rates can be read dynamically. It's an "is known" as it *can* be set via constraints in the FPGA tooling but does not have to be. - A fix for the Icicle's pwm-cells - Removal of some unused PCI clocks StarFive: - Addition of the VisionFive DT, which has been a long time coming! Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY3tLkQAKCRB4tDGHoIJi 0qM+AP9i7GnanM9SfzeRaftL/JO2RrDcM0QGW9tkE0DVsVyzugD+OxkxV4LJS9GJ O4UBM7APtCNJ7hUvvCQpikdAT2POKAI= =37HZ -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V DeviceTrees for v6.2 dt-bindings: - new compatibles to support the StarFive VisionFive & thead CPU cores - a fix for the PolarFire SoC's pwm binding, merged through my tree as suggested by the PWM maintainers Microchip: - Non-urgent fix for the node address not matches the reg in a way that the checkers don't complain about - Add GPIO controlled LEDs for Icicle - Support for the "CCC" clocks in the FPGA fabric. Previously these used fixed-frequency clocks in the dt, but if which CCC is in use is known, as in the v2022.09 Icicle Kit Reference Design, the rates can be read dynamically. It's an "is known" as it *can* be set via constraints in the FPGA tooling but does not have to be. - A fix for the Icicle's pwm-cells - Removal of some unused PCI clocks StarFive: - Addition of the VisionFive DT, which has been a long time coming! Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles riscv: dts: microchip: remove unused pcie clocks riscv: dts: microchip: remove pcie node from the sev kit riscv: dts: microchip: fix the icicle's #pwm-cells dt-bindings: pwm: fix microchip corePWM's pwm-cells riscv: dts: starfive: Add StarFive VisionFive V1 device tree riscv: dts: starfive: Add common DT for JH7100 based boards dt-bindings: riscv: starfive: Add StarFive VisionFive V1 board riscv: dts: microchip: fix memory node unit address for icicle riscv: dts: microchip: icicle: Add GPIO controlled LEDs riscv: dts: microchip: add the mpfs' fabric clock control Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Conor Dooley
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4563db4b79
|
Merge branch 'riscv-thead_c9xx' into riscv-dt-for-next
The bouffalolabs stuff is going to need the thead,c906 compatible too, so there is no point waiting the D1 stuff to land for it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
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Samuel Holland
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41adc2fbad |
dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C906 core is used in the Allwinner D1 SoC. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
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Lad Prabhakar
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9f643dc28e |
dt-bindings: riscv: Add Andes AX45MP core to the list
The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. In preparation to add support for RZ/Five SoC add the Andes AX45MP core to the list. More details about Andes AX45MP core can be found here: [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Guo Ren <guoren@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221028165921.94487-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
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Lad Prabhakar
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57e1b873c2 |
dt-bindings: riscv: Sort the CPU core list alphabetically
Sort the CPU cores list alphabetically for maintenance. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Guo Ren <guoren@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221028165921.94487-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
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Cristian Ciocaltea
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bd51ad5821 |
dt-bindings: riscv: starfive: Add StarFive VisionFive V1 board
Document the compatibles for StarFive VisionFive V1 SBC. The board is based on the StarFive JH7100 SoC. Link: https://github.com/starfive-tech/VisionFive Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
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Linus Torvalds
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498574970f |
RISC-V Patches for the 6.1 Merge Window, Part 2
* A handful of DT updates for the PolarFire SOC.
* A fix to correct the handling of write-only mappings.
* m{vetndor,arcd,imp}id is now in /proc/cpuinfo
* The SiFive L2 cache controller support has been refactored to also
support L3 caches.
There's also a handful of fixes, cleanups and improvements throughout
the tree.
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Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Palmer Dabbelt:
- DT updates for the PolarFire SOC
- a fix to correct the handling of write-only mappings
- m{vetndor,arcd,imp}id is now in /proc/cpuinfo
- the SiFive L2 cache controller support has been refactored to also
support L3 caches
- misc fixes, cleanups and improvements throughout the tree
* tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits)
MAINTAINERS: add RISC-V's patchwork
RISC-V: Make port I/O string accessors actually work
riscv: enable software resend of irqs
RISC-V: Re-enable counter access from userspace
riscv: vdso: fix NULL deference in vdso_join_timens() when vfork
riscv: Add cache information in AUX vector
soc: sifive: ccache: define the macro for the register shifts
soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes
soc: sifive: ccache: reduce printing on init
soc: sifive: ccache: determine the cache level from dts
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache
riscv: check for kernel config option in t-head memory types errata
riscv: use BIT() marco for cpufeature probing
riscv: use BIT() macros in t-head errata init
riscv: drop some idefs from CMO initialization
riscv: cleanup svpbmt cpufeature probing
riscv: Pass -mno-relax only on lld < 15.0.0
RISC-V: Avoid dereferening NULL regs in die()
dt-bindings: riscv: add new riscv,isa strings for emulators
...
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Palmer Dabbelt
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1a5a2cbd21
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Merge patch series "Use composable cache instead of L2 cache"
Zong Li <zong.li@sifive.com> says: Since composable cache may be L3 cache if private L2 cache exists, we should use its original name "composable cache" to prevent confusion. This patchset contains the modification which is related to ccache, such as DT binding and EDAC driver. * b4-shazam-merge: riscv: Add cache information in AUX vector soc: sifive: ccache: define the macro for the register shifts soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes soc: sifive: ccache: reduce printing on init soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Link: https://lore.kernel.org/r/20220913061817.22564-1-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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Zong Li
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44dce4b084
|
dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache
Since composable cache may be L3 cache if private L2 cache exists, we should use its original name Composable cache to prevent confusion. Signed-off-by: Zong Li <zong.li@sifive.com> Suggested-by: Conor Dooley <conor.dooley@microchip.com> Suggested-by: Ben Dooks <ben.dooks@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220913061817.22564-2-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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Palmer Dabbelt
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1b5964b2f9
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Merge patch series "Fix dt-validate issues on qemu dtbdumps due to dt-bindings"
Conor Dooley <mail@conchuod.ie> says:
From: Conor Dooley <conor.dooley@microchip.com>
The device trees produced automatically for the virt and spike machines
fail dt-validate on several grounds. Some of these need to be fixed in
the linux kernel's dt-bindings, but others are caused by bugs in QEMU.
Patches been sent that fix the QEMU issues [0], but a couple of them
need to be fixed in the kernel's dt-bindings. The first patches add
compatibles for "riscv,{clint,plic}0" which are present in drivers and
the auto generated QEMU dtbs.
Thanks to Rob Herring for reporting these issues [1],
Conor.
To reproduce the errors:
./build/qemu-system-riscv64 -nographic -machine virt,dumpdtb=qemu.dtb
dt-validate -p /path/to/linux/kernel/Documentation/devicetree/bindings/processed-schema.json qemu.dtb
(The processed schema needs to be generated first)
0 - https://lore.kernel.org/linux-riscv/20220810184612.157317-1-mail@conchuod.ie/
1 - https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
* fix-dt-validate:
dt-bindings: riscv: add new riscv,isa strings for emulators
dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible
dt-bindings: timer: sifive,clint: add legacy riscv compatible
Link: https://lore.kernel.org/r/20220823183319.3314940-1-mail@conchuod.ie
[Palmer: some cover letter pruning, and dropped #4 as suggested.]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Conor Dooley
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299824e68b
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dt-bindings: riscv: add new riscv,isa strings for emulators
The QEMU virt and spike machines currently export a riscv,isa string of "rv64imafdcsuh", While the RISC-V foundation has been ratifying a bunch of extenstions etc, the kernel has remained relatively static with what hardware is supported - but the same is not true of QEMU. Using the virt machine and running dt-validate on the dumped dtb fails, partly due to the unexpected isa string. Rather than enumerate the many many possbilities, change the pattern to a regex, with the following assumptions: - ima are required - the single letter order is fixed & we don't care about things that can't even do "ima" - the standard multi letter extensions are all in a "_z<foo>" format where the first letter of <foo> is a valid single letter extension - _s & _h are used for supervisor and hyper visor extensions - convention says that after the first two chars, a standard multi letter extension name could be an english word (ifencei anyone?) so it's not worth restricting the charset - as the above is just convention, don't apply any charset restrictions to reduce future churn - vendor ISA extensions begind with _x and have no charset restrictions - we don't care about an e extension from an OS pov - that attempting to validate the contents of the multiletter extensions with dt-validate beyond the formatting is a futile, massively verbose or unwieldy exercise at best The following limitations also apply: - multi letter extension ordering is not enforced. dt-schema does not appear to allow for named match groups, so the resulting regex would be even more of a headache - ditto for the numbered extensions Finally, add me as a maintainer of the binding so that when it breaks in the future, I can be held responsible! Reported-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Guo Ren <guoren@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220823183319.3314940-4-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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Palmer Dabbelt
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90e0d94d36 |
Microchip RISC-V devicetrees for v6.1
Fixups, reference design changes and new boards:
- The addition of QSPI support for mpfs had a corresponding change to
the devicetree node.
- The v2022.{09,10} reference designs brought with them several memory
map changes which are not backwards compatible. The old devicetrees
from the v2022.08 and earlier releases still work with current
kernels.
- Two new devicetrees for a first-party development kit and for the
Aries Embedded M100FPSEVP kit.
- Corresponding dt-bindings changes for the above.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Merge tag 'dt-for-palmer-v6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into for-next
Microchip RISC-V devicetrees for v6.1
Fixups, reference design changes and new boards:
- The addition of QSPI support for mpfs had a corresponding change to
the devicetree node.
- The v2022.{09,10} reference designs brought with them several memory
map changes which are not backwards compatible. The old devicetrees
from the v2022.08 and earlier releases still work with current
kernels.
- Two new devicetrees for a first-party development kit and for the
Aries Embedded M100FPSEVP kit.
- Corresponding dt-bindings changes for the above.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'dt-for-palmer-v6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: microchip: fix fabric i2c reg size
riscv: dts: microchip: update memory configuration for v2022.10
riscv: dts: microchip: add a devicetree for aries' m100pfsevp
riscv: dts: microchip: add sevkit device tree
riscv: dts: microchip: reduce the fic3 clock rate
riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
riscv: dts: microchip: icicle: update pci address properties
riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
riscv: dts: microchip: add pci dma ranges for the icicle kit
dt-bindings: riscv: microchip: document the sev kit
dt-bindings: riscv: microchip: document the aries m100pfsevp
dt-bindings: riscv: microchip: document icicle reference design
riscv: dts: microchip: add qspi compatible fallback
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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