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1517 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Linus Torvalds
|
36001a2fa6 |
The clk core gains a new set of APIs that allow drivers to both acquire clks
and prepare and enable them at the same time. This also comes with devm support
so that drivers can make a single call to get and prepare and enable the clk
and have that all undone when their driver is removed. Many folks have
requested this feature over the years, but we've had disagreements about how to
implement it and if it was worthwhile to encourage drivers to use such an API.
Now it's here, so let's see how it goes. I hope that by introducing this API we
can identify drivers that would benefit from further consolidation of clk API
usage, possibly by moving such logic to the bus layer and out of drivers
altogether.
Outside of that major API update, we have the usual collection of driver
updates. A few new SoCs are supported, mostly Qualcomm and Renesas this time
around. Then we have the long tail of non-critical fixes and minor feature
additions to various clk drivers. And finally more clk provider migration to
struct clk_parent_data, reducing boot times in the process.
Core:
- devm helpers for clk_get() + clk_prepare() and clk_enable()
New Drivers:
- Support for the camera clock controller in Qualcomm SM8450 and
the display and gpu clock controllers in Qualcomm SM8350
- Add support for the Renesas RZ/Five SoC
Updates:
- Various fixes, new clocks and USB GDSCs are introduced for Qualcomm IPQ8074
- Fixes to Qualcomm MSM8939 for issues introduced by inheriting the MSM8916
GCC driver
- Support for a new type of voteable GDSCs used by Qualcomm SC8280XP PCIe
GDSCs
- Qualcomm SC8280XP pipe clocks transitioned to the new phy-mux implementation
- Qualcomm MSM8996 GCC, RPM clock driver and some clocks in MSM8994 GCC are
migrated to use clk_parent_data
- Corrected the topology for Titan (camera) GDSCs on Qualcomm SDM845 and
SM8250
- Qualcomm MSM8916 gains more possible frequencies for its GP clocks.
- The GCC and tsens handling on Qualcomm MSM8960 is reworked to mimic the
design in IPQ8074 to allow the GCC driver to probe earlier.
- The regulator based mmcx supply for Qualcomm dispcc and videocc is dropped,
as the only upstream target that adapted this interface was transitioned
several kernel versions ago
- Qualcomm GDSCs found to be enabled at boot will now reflect in the enable
count of the supply, as was done with the regulator supplies previously
- Correct adc1, nic_media and edma1's parents for NXP i.MX93
- rdiv, mfd values, the return rate in recalc_rate and add more frequencies in
the table for fracn-gppll on i.MX
- Remove Allwinner workaround logic/compatible in fixed factor code
- MediaTek clk driver cleanups
- Add reset support to more MediaTek clk drivers
- deduplicate Allwinner ccu_clks arrays
- Allwinner H6 GPU DFS support
- Adjust Allwinner Kconfig to limit choice
- Fix initconst confusion on Renesas R-Car Gen4
- Add GPT/POEG (PWM) clocks and resets on Renesas RZ/G2L
- Add PFC and WDT clocks and resets on Renesas RZ/V2M
- Add thermal, SDHI, Z (CPU core), PCIe, and HSCIF (serial) clocks on
Renesas R-Car S4-8
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The clk core gains a new set of APIs that allow drivers to both
acquire clks and prepare and enable them at the same time. This also
comes with devm support so that drivers can make a single call to get
and prepare and enable the clk and have that all undone when their
driver is removed.
Many folks have requested this feature over the years, but we've had
disagreements about how to implement it and if it was worthwhile to
encourage drivers to use such an API.
Now it's here, so let's see how it goes.
I hope that by introducing this API we can identify drivers that would
benefit from further consolidation of clk API usage, possibly by
moving such logic to the bus layer and out of drivers altogether.
Outside of that major API update, we have the usual collection of
driver updates. A few new SoCs are supported, mostly Qualcomm and
Renesas this time around. Then we have the long tail of non-critical
fixes and minor feature additions to various clk drivers.
And finally more clk provider migration to struct clk_parent_data,
reducing boot times in the process.
Summary:
Core:
- devm helpers for clk_get() + clk_prepare() and clk_enable()
New Drivers:
- Support for the camera clock controller in Qualcomm SM8450 and the
display and gpu clock controllers in Qualcomm SM8350
- Add support for the Renesas RZ/Five SoC
Updates:
- Various fixes, new clocks and USB GDSCs are introduced for Qualcomm
IPQ8074
- Fixes to Qualcomm MSM8939 for issues introduced by inheriting the
MSM8916 GCC driver
- Support for a new type of voteable GDSCs used by Qualcomm SC8280XP
PCIe GDSCs
- Qualcomm SC8280XP pipe clocks transitioned to the new phy-mux
implementation
- Qualcomm MSM8996 GCC, RPM clock driver and some clocks in MSM8994
GCC are migrated to use clk_parent_data
- Corrected the topology for Titan (camera) GDSCs on Qualcomm SDM845
and SM8250
- Qualcomm MSM8916 gains more possible frequencies for its GP clocks.
- The GCC and tsens handling on Qualcomm MSM8960 is reworked to mimic
the design in IPQ8074 to allow the GCC driver to probe earlier.
- The regulator based mmcx supply for Qualcomm dispcc and videocc is
dropped, as the only upstream target that adapted this interface
was transitioned several kernel versions ago
- Qualcomm GDSCs found to be enabled at boot will now reflect in the
enable count of the supply, as was done with the regulator supplies
previously
- Correct adc1, nic_media and edma1's parents for NXP i.MX93
- rdiv, mfd values, the return rate in recalc_rate and add more
frequencies in the table for fracn-gppll on i.MX
- Remove Allwinner workaround logic/compatible in fixed factor code
- MediaTek clk driver cleanups
- Add reset support to more MediaTek clk drivers
- deduplicate Allwinner ccu_clks arrays
- Allwinner H6 GPU DFS support
- Adjust Allwinner Kconfig to limit choice
- Fix initconst confusion on Renesas R-Car Gen4
- Add GPT/POEG (PWM) clocks and resets on Renesas RZ/G2L
- Add PFC and WDT clocks and resets on Renesas RZ/V2M
- Add thermal, SDHI, Z (CPU core), PCIe, and HSCIF (serial) clocks on
Renesas R-Car S4-8"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (124 commits)
clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw()
clk: mux: Introduce devm_clk_hw_register_mux_parent_hws()
clk: divider: Introduce devm_clk_hw_register_divider_parent_hw()
clk: qcom: gcc-msm8994: use parent_hws for gpll0/4
clk: qcom: clk-rpm: convert to parent_data API
dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc
clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies
clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies
clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies
clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions
clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock
clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk
clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled
clk: qcom: Drop mmcx gdsc supply for dispcc and videocc
clk: qcom: fix build error initializer element is not constant
clk: sprd: Add dt-bindings include file for UMS512
dt-bindings: clk: sprd: Add bindings for ums512 clock controller
clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS
dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources
clk: qcom: add support for SM8350 DISPCC
...
|
||
|
Linus Torvalds
|
da8d07af4b |
Devicetree updates for v6.0:
Bindings:
- Add spi-peripheral-props.yaml references to various SPI device
bindings
- Convert qcom,pm8916-wdt, ds1307, Qualcomm BAM DMA, is31fl319x,
skyworks,aat1290, Rockchip EMAC, gpio-ir-receiver, ahci-ceva, Arm CCN
PMU, rda,8810pl-intc, sil,sii9022, ps2-gpio, and arm-firmware-suite
bindings to DT schema format
- New bindings for Arm virtual platforms display, Qualcomm IMEM memory
region, Samsung S5PV210 ChipID, EM Microelectronic EM3027 RTC, and
arm,cortex-a78ae
- Add vendor prefixes for asrock, bytedance, hxt, ingrasys, inventec,
quanta, and densitron
- Add missing MSI and IOMMU properties to host-generic-pci
- Remove bindings for removed EFM32 platform
- Remove old chosen.txt binding (replaced by schema)
- Treewide add missing type information for properties
- Treewide fixing of typos and its vs. it's in bindings. Its all good
now.
- Drop unnecessary quoting in power related schemas
- Several LED binding updates which didn't get picked up
- Move various bindings to proper directories
DT core code:
- Convert unittest GPIO related tests to use fwnode
- Check ima-kexec-buffer against memory bounds
- Print reserved-memory allocation/reservation failures as errors
- Cleanup early_init_dt_reserve_memory_arch()
- Simplify of_overlay_fdt_apply() tail
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Merge tag 'devicetree-for-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"Bindings:
- Add spi-peripheral-props.yaml references to various SPI device
bindings
- Convert qcom,pm8916-wdt, ds1307, Qualcomm BAM DMA, is31fl319x,
skyworks,aat1290, Rockchip EMAC, gpio-ir-receiver, ahci-ceva, Arm
CCN PMU, rda,8810pl-intc, sil,sii9022, ps2-gpio, and
arm-firmware-suite bindings to DT schema format
- New bindings for Arm virtual platforms display, Qualcomm IMEM
memory region, Samsung S5PV210 ChipID, EM Microelectronic EM3027
RTC, and arm,cortex-a78ae
- Add vendor prefixes for asrock, bytedance, hxt, ingrasys, inventec,
quanta, and densitron
- Add missing MSI and IOMMU properties to host-generic-pci
- Remove bindings for removed EFM32 platform
- Remove old chosen.txt binding (replaced by schema)
- Treewide add missing type information for properties
- Treewide fixing of typos and its vs. it's in bindings. Its all good
now.
- Drop unnecessary quoting in power related schemas
- Several LED binding updates which didn't get picked up
- Move various bindings to proper directories
DT core code:
- Convert unittest GPIO related tests to use fwnode
- Check ima-kexec-buffer against memory bounds
- Print reserved-memory allocation/reservation failures as errors
- Cleanup early_init_dt_reserve_memory_arch()
- Simplify of_overlay_fdt_apply() tail"
* tag 'devicetree-for-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (65 commits)
dt-bindings: mtd: microchip,mchp48l640: use spi-peripheral-props.yaml
dt-bindings: power: supply: drop quotes when not needed
dt-bindings: power: reset: drop quotes when not needed
dt-bindings: power: drop quotes when not needed
dt-bindings: PCI: host-generic-pci: Allow IOMMU and MSI properties
of/fdt: declared return type does not match actual return type
devicetree/bindings: correct possessive "its" typos
dt-bindings: net: convert emac_rockchip.txt to YAML
dt-bindings: eeprom: microchip,93lc46b: move to eeprom directory
dt-bindings: eeprom: at25: use spi-peripheral-props.yaml
dt-bindings: display: use spi-peripheral-props.yaml
dt-bindings: watchdog: qcom,pm8916-wdt: convert to dtschema
dt-bindings: power: reset: qcom,pon: use absolute path to other schema
dt-bindings: iio/dac: adi,ad5766: Add missing type to 'output-range-microvolts'
dt-bindings: power: supply: charger-manager: Add missing type for 'cm-battery-stat'
dt-bindings: panel: raydium,rm67191: Add missing type to 'video-mode'
of/fdt: Clean up early_init_dt_reserve_memory_arch()
dt-bindings: PCI: fsl,imx6q-pcie: Add missing type for 'reset-gpio-active-high'
dt-bindings: rtc: Add EM Microelectronic EM3027 bindings
dt-bindings: rtc: ds1307: Convert to json-schema
...
|
||
|
Stephen Boyd
|
dfcbbd73dd |
Merge branches 'clk-renesas', 'clk-spreadtrum', 'clk-imx' and 'clk-qcom' into clk-next
* clk-renesas: (22 commits) clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_config clk: renesas: r9a07g043: Add support for RZ/Five SoC dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions clk: renesas: r8a779f0: Add HSCIF clocks clk: renesas: r8a779f0: Add PCIe clocks clk: renesas: r8a779f0: Add Z0 and Z1 clock support dt-bindings: clock: renesas,rzg2l: Simplify header file references clk: renesas: rza1: Remove struct rz_cpg clk: renesas: r8a7779: Remove struct r8a7779_cpg clk: renesas: r8a7778: Remove struct r8a7778_cpg clk: renesas: sh73a0: Remove sh73a0_cpg.reg clk: renesas: r8a7740: Remove r8a7740_cpg.reg clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg clk: renesas: r8a779f0: Add SDHI0 clock clk: renesas: r8a779f0: Add thermal clock clk: renesas: rzg2l: Fix reset status function clk: renesas: r9a06g032: Fix UART clkgrp bitsel clk: renesas: r9a06g032: Drop some unused fields clk: renesas: r9a09g011: Add WDT clock and reset entries clk: renesas: r9a09g011: Add PFC clock and reset entries ... * clk-spreadtrum: clk: sprd: Add dt-bindings include file for UMS512 dt-bindings: clk: sprd: Add bindings for ums512 clock controller * clk-imx: clk: imx: clk-fracn-gppll: Add more freq config for video pll clk: imx: clk-fracn-gppll: correct rdiv clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate() clk: imx: clk-fracn-gppll: fix mfd value clk: imx93: Correct the edma1's parent clock clk: imx93: correct nic_media parent clk: imx93: use adc_root as the parent clock of adc1 * clk-qcom: (62 commits) clk: qcom: gcc-msm8994: use parent_hws for gpll0/4 clk: qcom: clk-rpm: convert to parent_data API dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled clk: qcom: Drop mmcx gdsc supply for dispcc and videocc clk: qcom: fix build error initializer element is not constant dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources clk: qcom: add support for SM8350 DISPCC clk: qcom: add support for SM8350 GPUCC clk: qcom: add camera clock controller driver for SM8450 SoC clk: qcom: clk-alpha-pll: add Rivian EVO PLL configuration interfaces clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces clk: qcom: clk-alpha-pll: limit exported symbols to GPL licensed code clk: qcom: clk-alpha-pll: fix clk_trion_pll_configure description ... |
||
|
Stephen Boyd
|
f04ed3d9f8 |
Merge branches 'clk-basic', 'clk-mtk', 'clk-devm-enable' and 'clk-ti-dt' into clk-next
- Remove allwinner workaround logic/compatible in fixed factor code - MediaTek clk driver cleanups - Add reset support to more MediaTek clk drivers - devm helpers for clk_get() + clk_prepare() and clk_enable() * clk-basic: clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw() clk: mux: Introduce devm_clk_hw_register_mux_parent_hws() clk: divider: Introduce devm_clk_hw_register_divider_parent_hw() dt-bindings: clock: fixed-factor: Drop Allwinner A10 compatible clk: fixed: Remove Allwinner A10 special-case logic * clk-mtk: clk: mediatek: reset: Add infra_ao reset support for MT8186 dt-bindings: arm: mediatek: Add #reset-cells property for MT8186 dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186 clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195 dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 clk: mediatek: reset: Add reset support for simple probe clk: mediatek: reset: Add new register reset function with device clk: mediatek: reset: Change return type for clock reset register function clk: mediatek: reset: Support inuput argument index mode clk: mediatek: reset: Support nonsequence base offsets of reset registers clk: mediatek: reset: Revise structure to control reset register clk: mediatek: reset: Merge and revise reset register function clk: mediatek: reset: Extract common drivers to update function clk: mediatek: reset: Refine and reorder functions in reset.c clk: mediatek: reset: Fix written reset bit offset clk: mediatek: reset: Add reset.h clk: mediatek: Delete MT8192 msdc gate dt-bindings: ARM: Mediatek: Remove msdc binding of MT8192 clock * clk-devm-enable: clk: Remove never used devm_clk_*unregister() clk: Fix pointer casting to prevent oops in devm_clk_release() clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled() clk: Provide new devm_clk helpers for prepared and enabled clocks clk: generalize devm_clk_get() a bit clk: Improve documentation for devm_clk_get() and its optional variant * clk-ti-dt: clk: ti: Stop using legacy clkctrl names for omap4 and 5 |
||
|
Linus Torvalds
|
dd65b96492 |
ARM: new SoC support for 6.0
This adds initial support for two SoC families that have been under review for a while. In both cases, the origonal idea was to have a minimally functional version, but we ended up leaving out the clk drivers that are still under review and will be merged through the corresponding subsystem tree. The Nuvoton NPCM8xx is a 64-bit Baseboard Management Controller and based on the 32-bit NPCM7xx family but is now getting added to arch/arm64 as well. Sunplus SP7021, also known as Plus1, is a general-purpose System-in-Package design based on the 32-bit Cortex-A7 SoC on the main chip, plus an I/O chip and memory in the same -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLo+24ACgkQmmx57+YA GNkPVw//XAC/uK7WR4oz1D1YaPPNhEvFa6hV1gjGB7Iif72SzyDJmC+36MATU/AY neQjCOLJMhxI0hpDGY9nLYe+aP1C6vD32zsjffjt/+s9em+YZZCUkRJuQ5xO3fID Uk8ZAnCIcOqX9sjXr9ChW8irlcWFbKzhgWXnPqwQmycIaE7QVz1wx32dbc64YuAK S+290U8wbj8bukr33TyZPMdYlfqNU3c1W+dCaeVsQlX1juoHEV3stmIjslRefd6X Jre22YJE41VlPufZej76nHXuVnjKf54Oi347TcbPOWNDtEAIESt3mzKy+zICBT2p v01rNBf0SogyOtSbWDPTFCAH9W9hujSOJIUOWpbOLaPdfElXxcoTBwj2e2LMoW0k ke7YR1m6FKDam5GFU9Oe98CWIiVm/GnTA5mnhhETU1QTXQ3KeZ+Z8X779YuSWPv9 kJuOPRSk9NdcfRtxZz1vpCvhv/2hBbeBuz+GZi3bisMWdvVqS3lFqVbr6kziQbJZ kE6KJH48FdL0VLVvuy+aNSF2umLT42b+5+cmQFuP2zePQgo1DEMKEtFXpZjQJbha 3iu3sHnieOFMLcbNzbqSz2im3yYNBjl1M5qoGEXaw3Rkzqiht0kMNvAa4LmAejbh E+5BIczwWNbaUKgToV1ij65O4a78Bw98m2SIS7awEZC5MW/nXYA= =7Id+ -----END PGP SIGNATURE----- Merge tag 'arm-newsoc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM new SoC support from Arnd Bergmann: "This adds initial support for two SoC families that have been under review for a while. In both cases, the origonal idea was to have a minimally functional version, but we ended up leaving out the clk drivers that are still under review and will be merged through the corresponding subsystem tree. The Nuvoton NPCM8xx is a 64-bit Baseboard Management Controller and based on the 32-bit NPCM7xx family but is now getting added to arch/arm64 as well. Sunplus SP7021, also known as Plus1, is a general-purpose System-in-Package design based on the 32-bit Cortex-A7 SoC on the main chip, plus an I/O chip and memory in the same" * tag 'arm-newsoc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits) MAINTAINERS: rectify entry for ARM/NUVOTON NPCM ARCHITECTURE arm64: defconfig: Add Nuvoton NPCM family support arm64: dts: nuvoton: Add initial NPCM845 EVB device tree arm64: dts: nuvoton: Add initial NPCM8XX device tree arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string dt-bindings: arm: npcm: Add maintainer reset: npcm: Add NPCM8XX support dt-bindings: reset: npcm: Add support for NPCM8XX reset: npcm: using syscon instead of device data ARM: dts: nuvoton: add reset syscon property dt-bindings: reset: npcm: add GCR syscon property dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock dt-bindings: watchdog: npcm: Add npcm845 compatible string dt-bindings: timer: npcm: Add npcm845 compatible string ARM: dts: Add Sunplus SP7021-Demo-V3 board device tree ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig ARM: sunplus: Add initial support for Sunplus SP7021 SoC irqchip: Add Sunplus SP7021 interrupt controller driver ... |
||
|
Randy Dunlap
|
be55492e01 |
devicetree/bindings: correct possessive "its" typos
Correct all uses of "it's" that are meant to be possessive "its". Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220801025221.30563-1-rdunlap@infradead.org |
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Slark Xiao
|
12e5bde18d |
dt-bindings: Fix typo in comment
Fix typo in the comment Signed-off-by: Slark Xiao <slark_xiao@163.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220721011746.19663-1-slark_xiao@163.com |
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Arnd Bergmann
|
2d0f3f13a9 |
Merge branch 'nuvoton/newsoc' into arm/newsoc
Merge the new SoC support from Tomer Maimon: "This patchset adds initial support for the Nuvoton Arbel NPCM8XX Board Management controller (BMC) SoC family. The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC. The NPCM8XX computing subsystem comprises a quadcore ARM Cortex A35 ARM-V8 architecture. This patchset adds minimal architecture and drivers such as: Clocksource, Clock, Reset, and WD. Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX. This patchset was tested on the Arbel NPCM8XX evaluation board." I'm leaving out the clk controller driver, which is still under review. * nuvoton/newsoc: arm64: defconfig: Add Nuvoton NPCM family support arm64: dts: nuvoton: Add initial NPCM845 EVB device tree arm64: dts: nuvoton: Add initial NPCM8XX device tree arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string dt-bindings: arm: npcm: Add maintainer reset: npcm: Add NPCM8XX support dt-bindings: reset: npcm: Add support for NPCM8XX reset: npcm: using syscon instead of device data ARM: dts: nuvoton: add reset syscon property dt-bindings: reset: npcm: add GCR syscon property dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock dt-bindings: watchdog: npcm: Add npcm845 compatible string dt-bindings: timer: npcm: Add npcm845 compatible string |
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Tomer Maimon
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08e950449c |
dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
Add binding for the Arbel BMC NPCM8XX Clock controller. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Christian Marangi
|
4970f3139d |
dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc
qcom,rpmcc describe 2 different kind of device. Currently we have definition for rpm-smd based device but we lack Documentation for simple rpm based device. Add the missing clk for ipq806x, apq8060, msm8660 and apq8064 and provide additional example to describe these new simple rpm based devices. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706225321.26215-2-ansuelsmth@gmail.com |
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Arnd Bergmann
|
e0a5925055 |
Qualcomm ARM64 DTS updates for v5.20
This introduces initial support for Lenovo ThinkPad X13s, Qualcomm 8cx Gen 3 Compute Reference Device, SA8295P Automotive Development Platform, Xiaomi Mi 5s Plus, five new SC7180 Chrome OS boards, Inforce IFC6560, LG G7 ThinQ and LG V35 ThinQ. With IPQ8074 gaining GDSC support, this was expressed in the gcc node and defined for the USB nodes. The SDHCI reset line was defined to get the storage devices into a known state. For MSM8996 interconnect providers, the second DSI interface, resets for SDHCI are introduced. Support for the Xiaomi Mi 5s Plus is introduced and the Dragonboard 820c gains definitions for its LEDs. The MSM8998 platform changes consists of a various cleanup patches, the FxTec Pro1 is split out from using the MTP dts and Sony Xperia devices on the "Yoshino" platform gains ToF sensor. On SC7180 five new Trogdor based boards are added and the description of keyboard and detachables is improved. On the SC7280-based Herobrine board DisplayPort is enabled, SPI flash clock rate is changed, WiFi is enabled and the modem firmware path is updated. The Villager boards gains touchscreen, and keyboard backlight. This introduces initial support for the SC8280XP (aka 8cx Gen 3) and related automotive platforms are introduced, with support for the Qualcomm reference board, the Lenovo Thinkpad X13s and the SA8295P Automotive Development Platform. In addition to a wide range of smaller fixes on the SDM630 and SDM660 platforms, support for the secondary high speed USB controller is introduced and the Sony Xperia "Nile" platform gains support for the RGB status LED. Support for the Inforce IFC6560 board is introduced. On SDM845 the bandwidth monitor for the CPU subsystem is introduced, to scale LLCC clock rate based on profiling. CPU and cluster idle states are switched to OSI hierarchical states. DB845c and SHIFT 6mq gains LED support and new support for the LG G7 ThinQ and LG V35 ThinQ boards are added. DLL/DDR configuration for SDHCI nodes are defined for SM6125. On SM8250 the GPU per-process page tables is enabled and for RB5 the Light Pulse Generator-based LEDs are added. The display clock controller is introduced for SM8350. On SM8450 this introduces the camera clock controller and the UART typically used for Bluetooth. The interconnect path for the crypto engine is added to the SCM node, to ensure this is adequately clocked. The assigned-clock-rate for the display processor is dropped from several platforms, now that the driver derrives the min and max from the clock. In addition to this a wide range of fixes for stylistic issues and issues discovered through Devicetree binding validation across many platforms and boards are introduced. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmLPLQkbHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3Fe7gQAKK2W3OKC5uKllNc7ICE rTeQeVNoZPxtqgvTcpAViarDCZin1jo21vDusK3q1iLICSN3XPvfvEYnYIRit/AU lRK0O/OBfVzzf+6qsTZqAUybLF2heYA6woESbcIoZMcmZYPwNTmVQvMuPnd0uBro yasN7Nm/wcWBlbnyWWAwnU8sYlBx0OfiXq/3z60adDJFJr5DoEFeapkrV/wr9dpx YR6kLRM7h9zzqctjOmqM/ZPxI8z3dS83eMS/4k1CkeuTKxQ+pIaBDm5WqhoWuuHH CY5Ebc7PzsbEWsx9Qt+bxur5lbeT5brAlGFLNtpn55hz9JQyCrUTIRgPJI21vT7O swlGFfW3IYsp8sU3cV7cQ8W7TGrv/1syUbEA+vCEudd00+TEUM+QJmI7bzZVHPUx Ari4poAb0D8w2517dTHEiBVQ7a7eRGbMqvJEraWNtklcbNAocV53U6Sz7XAr4Bjm 0FFbCc18C+DuvMd12B8Vp92Vy8Q62M0fcnaMiL5+QVzGx1fj1bq1aL7kUuUhgsP/ 3esJUw4dNVK3d4b2uy3DR3trobr8jjirMuXKa5V8WUvr3vP9z4hRLTM9l6fecGRW 0qrzf5iehwJ8itiUYtm/AyGYq1TjkJYxbhtQW8oRiQAJBIyRPjtPITq54l0yLz7/ w1faJprsybDMh+ESmaHYPbZK =89g4 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLQL/QACgkQmmx57+YA GNmMUxAAu7iL+YiuKDOxO9vD3INq5XukdZvbCOaiyWkwafsyf0YqhlIXUV0LD/q3 dpDm2/od9KQGvMG9WE34Fdq2e9nj35NiRHkKM5wLVTuypgh62VmP1PH8q0z+L+hr A9IdxwzgXd+ZoDMSkPVHjZauBrALeqxuQshoEvBE11EncCIeQrsxHDIzGjIBlohc yZ5EGAYBRDt7dmRv2M3Vpk68gJc5F264zc/mljbrnf1iW/C1b3z6PXtRZXt6p+iq Dzfbh+LeWIo2ddrkXhcU3ZFiafMZ5zTLZWWtKystqU9lk3fVvvp1ZcoeEgg9j5tQ 2TgddYBJTOHm9vlJIYD6zo/AL6adixYOPZOnSzWY17zC8Yq7e5lbc/A4NkoL3lUZ oTbEtjmR55hJG2C6JNLsCDuI2eo5zJ9KZB8rE9CBp+kWh2UExjKVbk1LDjUQcLQl 0cYDbIDeLJFSwSMQ18GeoLbsp3rSlPUOMuoUCdKCsCp9xLzWIxBR7LbthO/R3OOE mXsxGQTwn2PbEZEqFddW3vvcBF+FL1IQ/YgC6F/1MKbvU60KjdWNYqeXSz9PZ/AR 6HyszhnGyGUU0xCWx93XHgfSCKTr8zkjD1zloWy5ibX4rUUg+iC2TnQ3n7srQNCj S8bpFED4JXfFj+LfgR9vZr5sUM+C1oYiIVXccZ9QLwiNWLfAfFQ= =XnF9 -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt Qualcomm ARM64 DTS updates for v5.20 This introduces initial support for Lenovo ThinkPad X13s, Qualcomm 8cx Gen 3 Compute Reference Device, SA8295P Automotive Development Platform, Xiaomi Mi 5s Plus, five new SC7180 Chrome OS boards, Inforce IFC6560, LG G7 ThinQ and LG V35 ThinQ. With IPQ8074 gaining GDSC support, this was expressed in the gcc node and defined for the USB nodes. The SDHCI reset line was defined to get the storage devices into a known state. For MSM8996 interconnect providers, the second DSI interface, resets for SDHCI are introduced. Support for the Xiaomi Mi 5s Plus is introduced and the Dragonboard 820c gains definitions for its LEDs. The MSM8998 platform changes consists of a various cleanup patches, the FxTec Pro1 is split out from using the MTP dts and Sony Xperia devices on the "Yoshino" platform gains ToF sensor. On SC7180 five new Trogdor based boards are added and the description of keyboard and detachables is improved. On the SC7280-based Herobrine board DisplayPort is enabled, SPI flash clock rate is changed, WiFi is enabled and the modem firmware path is updated. The Villager boards gains touchscreen, and keyboard backlight. This introduces initial support for the SC8280XP (aka 8cx Gen 3) and related automotive platforms are introduced, with support for the Qualcomm reference board, the Lenovo Thinkpad X13s and the SA8295P Automotive Development Platform. In addition to a wide range of smaller fixes on the SDM630 and SDM660 platforms, support for the secondary high speed USB controller is introduced and the Sony Xperia "Nile" platform gains support for the RGB status LED. Support for the Inforce IFC6560 board is introduced. On SDM845 the bandwidth monitor for the CPU subsystem is introduced, to scale LLCC clock rate based on profiling. CPU and cluster idle states are switched to OSI hierarchical states. DB845c and SHIFT 6mq gains LED support and new support for the LG G7 ThinQ and LG V35 ThinQ boards are added. DLL/DDR configuration for SDHCI nodes are defined for SM6125. On SM8250 the GPU per-process page tables is enabled and for RB5 the Light Pulse Generator-based LEDs are added. The display clock controller is introduced for SM8350. On SM8450 this introduces the camera clock controller and the UART typically used for Bluetooth. The interconnect path for the crypto engine is added to the SCM node, to ensure this is adequately clocked. The assigned-clock-rate for the display processor is dropped from several platforms, now that the driver derrives the min and max from the clock. In addition to this a wide range of fixes for stylistic issues and issues discovered through Devicetree binding validation across many platforms and boards are introduced. * tag 'qcom-arm64-for-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (193 commits) arm64: dts: qcom: sc8280xp: fix DP PHY node unit addresses arm64: dts: qcom: sc8280xp: fix usb_0 HS PHY ref clock arm64: dts: qcom: sc7280: fix PCIe clock reference docs: arm: index.rst: add google/chromebook-boot-flow arm64: dts: qcom: msm8996: clean up PCIe PHY node arm64: dts: qcom: msm8996: use non-empty ranges for PCIe PHYs arm64: dts: qcom: sm8450: drop UFS PHY clock-cells arm64: dts: qcom: sm8250: drop UFS PHY clock-cells arm64: dts: qcom: sc8280xp: drop UFS PHY clock-cells arm64: dts: qcom: sm8450: drop USB PHY clock index arm64: dts: qcom: sm8350: drop USB PHY clock index arm64: dts: qcom: msm8998: drop USB PHY clock index arm64: dts: qcom: ipq8074: drop USB PHY clock index arm64: dts: qcom: ipq6018: drop USB PHY clock index arm64: dts: qcom: sm8250: add missing PCIe PHY clock-cells arm64: dts: qcom: sc7280: drop PCIe PHY clock index Revert "arm64: dts: qcom: Fix 'reg-names' for sdhci nodes" arm64: dts: qcom: sc7180-idp: add vdds supply to the DSI PHY arm64: dts: qcom: sc7280: use constants for gpucc clocks and power-domains arm64: dts: qcom: msm8996: add missing DSI clock assignments ... Link: https://lore.kernel.org/r/20220713203939.1431054-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Cixi Geng
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6a3a6c7ae0 |
dt-bindings: clk: sprd: Add bindings for ums512 clock controller
Add a new bindings to describe ums512 clock compatible string. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Signed-off-by: Cixi Geng <cixi.geng1@unisoc.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220505101433.1575096-2-gengcixi@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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Arnd Bergmann
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8128bfe3d7 |
i.MX DT bindings update for 5.20:
- Compatibles for new boards: i.MX7 based Toradex Colibri, DH electronics i.MX8M Plus DHCOM and PDK2, TQMa8MPxL, Carrier for Toradex i.MX6 Apalis, i.MX93 EVK, PHYTEC i.MX8MM based board. - A series from Abel Vesa (and Viorel Suman) to split fsl,scu.txt bindings into multiple subsystem bindings in yaml format. - Fix 'line too long' warning caused by Toradex Colibri boards. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmLJK7EUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM4icAgAlDCVfJs6fS5FNFGx0CtCvi18nI5+ mtnyKv2k+PEDuAN00LzAtww08wZQW0AQBPrmFdXVjT4KodWRwFNFFPJYEdgMf+zn cONkq4JE0YNmVCIsFHhqKbobGbgOGivm9mBsA/c31z4AXxicEuZLg7AWD4Fs/dsA FjvWGIrn6kvQIFrHo1kycY6rj5DygWzgQxVJnpL/yjqDr6cGOAH6EFn6kynNYknW rrEoGMynM15D0M1YdnB7O9bYDfglDRqwmzmhB4Y7KthN1DYRr4cNeGRfV3R+6tDr oSzrvUjFOA/RtK4aqx79+mgJ7LcrnVeWN+t4cHWceHbI5G+HJgxyiGMdQQ== =7pMF -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLMRKAACgkQmmx57+YA GNlvgQ//UacpQk+mU2Z1Iq6spUqKd+X7aowbRaaEM3VCZ58yoJJ7VtO8+Nd22pLT 6NCiTykVSFQfkn+/bZLtZdboyHeW5mSxl0HKgQo0jl0MVRZY+gysJzpz1M2WYtHq MKoroTJZ1bNuptru02oU1DCtSLBPzYuLiKtzBsqc4mRh7QTw7O6ZnF0kQZZ5vykr Fn5s88+gOeYUWQgIXg1OZIemvfoD37iao3FpGkK+c1UgfEqkBJ22y13M8qncvhEn Hz6FemHxJRHN2/hFICyxJt2GQh38hcK07CidNyGvzntVDIzULNdG9Gp6o8On9U6k X8B/902XMnqZrYjHzOqa/bPws6FamDbw0BZRenFO3hFbmg9W7nukA44oIYObSAe2 j9uIIF0/Q0Eir4APFcGOLftA8tnU9YpGLc0iOUMQrV1hYUYVyeHZRQ87Fg7Gwrit AuFCcNCwga2M9mmqKi8qQYtrgISUDEWl5ZWj2+C08E62o5HGbUATrL7I7cJ6245Z 9f6IrOyuQoq3K2A0ESaaKuS3E6oMV5EcAJtUzbk1l8DaKXjHKXSPIjQsU6zgvXhu 0RmDSuAr+rmRs+XBh5qSt2ayFA61zlzFW/P9CcOP3BhOuRscSxNAt5VnuU4j+OR2 mhFgzsslVLBvXzE+m1QT2vXU2jzfH3LZv2Ks3pV6dcwoBOIz1FQ= =8UqQ -----END PGP SIGNATURE----- Merge tag 'imx-bindings-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX DT bindings update for 5.20: - Compatibles for new boards: i.MX7 based Toradex Colibri, DH electronics i.MX8M Plus DHCOM and PDK2, TQMa8MPxL, Carrier for Toradex i.MX6 Apalis, i.MX93 EVK, PHYTEC i.MX8MM based board. - A series from Abel Vesa (and Viorel Suman) to split fsl,scu.txt bindings into multiple subsystem bindings in yaml format. - Fix 'line too long' warning caused by Toradex Colibri boards. * tag 'imx-bindings-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: arm: add TQMa8MPxL board dt-bindings: firmware: Add fsl,scu yaml file dt-bindings: watchdog: Add fsl,scu-wdt yaml file dt-bindings: thermal: Add fsl,scu-thermal yaml file dt-bindings: rtc: Add fsl,scu-rtc yaml file dt-bindings: power: Add fsl,scu-pd yaml file dt-bindings: nvmem: Add fsl,scu-ocotp yaml file dt-bindings: input: Add fsl,scu-key yaml file dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file dt-bindings: clk: imx: Add fsl,scu-clk yaml file bindings: arm: fsl: Add PHYTEC i.MX8MM devicetree bindings dt-bindings: arm: fsl: Add carrier for toradex,apalis-imx6q dt-bindings: arm: fsl: Decrease the line length dt-bindings: arm: Add DH electronics i.MX8M Plus DHCOM and PDK2 dt-bindings: arm: fsl: add toradex,colibri-imx7s/d/d-emmc-iris/-v2 dt-bindings: arm: fsl: add imx93 11x11 evk board dt-bindings: arm: fsl: correct 1g vs. 1gb in toradex,colibri-imx6ull-* Link: https://lore.kernel.org/r/20220709082951.15123-3-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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859dd6d3e6 |
- whitespace fixes
- replaced RTC indexes with constants - gpio-key nodes aligned with dtschema - fixed LED node for Orange Pi Win - added OPP table for R40 CPU and thermal points - updated I2C controller compatibles - added compatibles for MBUS, D1 DE2 clocks, D1 USB - enable internal HMIC bias on Pinephone -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSPRixG1tysKC2PKM10Ba7+DO8kkwUCYsh7YwAKCRB0Ba7+DO8k k3aLAP0dXcVZyUMO4WSRYIYbXd7fzOjFrHw/Zk0tYonCqTCHnwEAgUpkZFLPNrGe rg1lj8qSadFrupmqa32sYR9ypToy8gc= =KOKj -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLMQnMACgkQmmx57+YA GNkweBAAqq7bCNCcrJG25L/sxh2Jrq33RaBVkP0Eyo0pN8ECbeEGckG/siIZNod7 JFt74y5GqGag3IGQQFhzAoA4sjSMFn/twpKTTLTdh90enZn9ci2r3GLb8xxcrgdY v+XH4kA9cjVmtw81AKwzkYiL2YT6exJ1sOC7Hai3XuWSFamLU5Y3/VGkyeieFSYD F4kFc+6huYPH/I/0K2BxZ0nlH2/FGw3erK49RDPppx4cN/zrN5RGao8esF2WSfW5 YXnIYlScavl8aTuwY+skO27RoZ5d76tgtDvRw5OMWsMsvwFVu39LvmKpkeqYSIyF 8ELmVK0/PnuPabSzoe4ZXcJOtvZsPsRL/jdsMr6Or8W4ESLgTCon2tadjc/pjXeN WzOtkjuHhlf3C/lnGS5Q2P5lJ1cc3nNuzMgZpusrVRsxizf+cqgnYciSfRe24gU/ OJaNBagJLEma5ied58/EqzZlru27amrUdNrDwAGbxVX1PNkwXtzQJ/SUi1X9jlUm L9sFa3uGBpZopTAXQ1CQJQ/Lcg3ba9NV7RZfesGWylzGb81DCJglyIabWwj+BFsC F0QLqI7efncnT2sL58th0BcUEROKNm9Sou4QmwV0Qgg6kaXYKR2daP23AYVrZM3c 76aBLg5+Tb+tZrMaCI8VkwTzOpTCxAwNmpEUKKjbU+6YZoi4l8Q= =Q624 -----END PGP SIGNATURE----- Merge tag 'sunxi-dt-for-5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt - whitespace fixes - replaced RTC indexes with constants - gpio-key nodes aligned with dtschema - fixed LED node for Orange Pi Win - added OPP table for R40 CPU and thermal points - updated I2C controller compatibles - added compatibles for MBUS, D1 DE2 clocks, D1 USB - enable internal HMIC bias on Pinephone * tag 'sunxi-dt-for-5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: pinephone: Enable internal HMIC bias dt-bindings: arm: sunxi: Add several MBUS compatibles dt-bindings: arm: sunxi: Default to the full MBUS binding dt-bindings: usb: generic-ohci: Add Allwinner D1 compatible dt-bindings: usb: generic-ehci: Add Allwinner D1 compatible dt-bindings: usb: sunxi-musb: Add Allwinner D1 compatible arm64: dts: allwinner: a100: Update I2C controller fallback dt-bindings: i2c: mv64xxx: Add variants with offload support ARM: dts: sun8i-r40: Add thermal trip points/cooling maps ARM: dts: sun8i-r40: add opp table for cpu ARM: dts: sun8i-r40: Add "cpu-supply" node for sun8i-r40 based board arm64: dts: allwinner: a64: orangepi-win: Fix LED node name dt-bindings: clock: Add compatible for D1 DE2 clocks ARM: dts: allwinner: align gpio-key node names with dtschema arm64: dts: allwinner: align gpio-key node names with dtschema arm64: dts: allwinner: Use constants for RTC clock indexes ARM: dts: sunxi: Use constants for RTC clock indexes ARM: dts: sun5i: adjust whitespace around '=' Link: https://lore.kernel.org/r/Ysh8qRH0Q5Xv9Qhf@kista.localdomain Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Qin Jian
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5543604a05 |
dt-bindings: clock: Add bindings for SP7021 clock driver
Add documentation to describe Sunplus SP7021 clock driver bindings. Signed-off-by: Qin Jian <qinjian@cqplus1.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Abel Vesa
|
9056aa0451 |
dt-bindings: clk: imx: Add fsl,scu-clk yaml file
In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'clock' child node of the SCU main node. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org> |
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Dmitry Baryshkov
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2b4e75a7a7 |
dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources
Add additional GCC clock sources. This includes PCIe and USB PIPE and
UFS symbol clocks.
Fixes:
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Bjorn Andersson
|
1352b15288 | Merge branch '20220706154337.2026269-1-robert.foss@linaro.org' into arm64-for-5.20 | ||
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Bjorn Andersson
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7e06c69221 | Merge branch '20220706154337.2026269-1-robert.foss@linaro.org' into clk-for-5.20 | ||
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Bjorn Andersson
|
fb162534b3 | Merge branch '20220701062622.2757831-2-vladimir.zapolskiy@linaro.org' into clk-for-5.20 | ||
|
Vladimir Zapolskiy
|
494e984af5 |
dt-bindings: clock: add QCOM SM8450 camera clock bindings
The change adds device tree bindings for camera clock controller found on SM8450 SoC. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220701062622.2757831-2-vladimir.zapolskiy@linaro.org |
||
|
Jonathan Marek
|
909e5be2ca |
dt-bindings: clock: Add Qcom SM8350 DISPCC bindings
Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250 bindings. Update the documentation with the new compatible. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706154337.2026269-4-robert.foss@linaro.org |
||
|
Robert Foss
|
e67a004482 |
dt-bindings: clock: Add Qcom SM8350 GPUCC bindings
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmityr.baryshkov@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706154337.2026269-2-robert.foss@linaro.org |
||
|
Arnd Bergmann
|
888c173e31 |
STM32 DT for v5.20, round 1
Highlights:
----------
- MCU:
-Fix whitespace coding style. No functional changes.
- MPU:
- General:
- Remove specific IPCC wakeup interrupt on STM32MP15.
- Enable OPTEE firmware and scmi support (clock/reset) on
STM32MP13. It allows to enable RCC clock driver.
- Add new pins configurations groups.
- DH boards:
- Add DHCOR based DRC Compact board. It embeds: 2xETH, 1xCAN,
uSD, USB, eMMC and SDIO wifi.
- Add ST MIPID02 bindings to AV96 (not enabled by default)
- OSD32:
- Correct vcc-supply for eeprom.
- fix missing internally connected voltage regulator (ldo3
supplied by vdd_ddr).
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Merge tag 'stm32-dt-for-v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT for v5.20, round 1
Highlights:
----------
- MCU:
-Fix whitespace coding style. No functional changes.
- MPU:
- General:
- Remove specific IPCC wakeup interrupt on STM32MP15.
- Enable OPTEE firmware and scmi support (clock/reset) on
STM32MP13. It allows to enable RCC clock driver.
- Add new pins configurations groups.
- DH boards:
- Add DHCOR based DRC Compact board. It embeds: 2xETH, 1xCAN,
uSD, USB, eMMC and SDIO wifi.
- Add ST MIPID02 bindings to AV96 (not enabled by default)
- OSD32:
- Correct vcc-supply for eeprom.
- fix missing internally connected voltage regulator (ldo3
supplied by vdd_ddr).
* tag 'stm32-dt-for-v5.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (25 commits)
ARM: dts: stm32: Add ST MIPID02 bindings to AV96
ARM: dts: stm32: Add alternate pinmux for RCC pin
ARM: dts: stm32: Add alternate pinmux for DCMI pins
ARM: dts: stm32: Add DHCOR based DRC Compact board
ARM: dts: stm32: Add alternate pinmux for UART5 pins
ARM: dts: stm32: Add alternate pinmux for UART4 pins
ARM: dts: stm32: Add alternate pinmux for UART3 pins
ARM: dts: stm32: Add alternate pinmux for SPI2 pins
ARM: dts: stm32: Add alternate pinmux for CAN1 pins
dt-bindings: arm: stm32: Add compatible string for DH electronics DHCOR DRC Compact
ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15
ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk
ARM: dts: stm32: add RCC on STM32MP13x SoC family
ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13
dt-bindings: rcc: stm32: select the "secure" path for stm32mp13
ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32
ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1
ARM: dts: stm32: adjust whitespace around '=' on MCU boards
ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI
ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151
...
Link: https://lore.kernel.org/r/a250f32b-f67c-2922-0748-e39dc791e95c@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
|
Alexandre Torgue
|
f3af33a8ee |
dt-bindings: rcc: stm32: select the "secure" path for stm32mp13
Like for stm32mp15, when stm32 RCC node is used to interact with a secure context (using clock SCMI protocol), a different path has to be used for yaml verification. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> |
||
|
Dmitry Baryshkov
|
621f984840 |
dt-bindings: clock: qcom,gcc-apq8064: split tsens to the child node
Split tsens properties to the child node of the gcc. This follows the lead of ipq8064 (which also uses a separate node for tsens) and makes device tree closer to other platforms, where tsens is a completely separate device. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220521151437.1489111-3-dmitry.baryshkov@linaro.org |
||
|
Dmitry Baryshkov
|
91a4cbf933 |
dt-bindings: clock: qcom,gcc-apq8064: move msm8960 compat from gcc-other.yaml
MSM8960 shares the design (and the driver) of the global clock controller with APQ8064. Move it from clock/qcom,gcc-other.yaml to clock/qcom,gcc-apq8064.yaml. As the example in gcc-other.yaml was using qcom,gcc-msm8960 compat string, change it to qcom,gcc-msm8974. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220521151437.1489111-2-dmitry.baryshkov@linaro.org |
||
|
Arnd Bergmann
|
813b080890 |
Samsung DTS ARM64 changes for v5.20
1. Add CPU cache, UFS to Tesla FSD.
2. Add reboot-mode (boot into specific bootloader mode) to ExynosAutov9.
3. Add watchdogs to ExynosAutov9.
4. Add eMMC to Exynos7885 JackpotLTE (Samsung Galaxy A8).
5. DTS cleanup: white-spaces, node names, LED color/function.
6. Switch to DTS-local header for pinctrl register values instead of
bindings header. The bindings header is being deprecated because it
does not reflect the purpose of bindings.
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Merge tag 'samsung-dt64-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM64 changes for v5.20
1. Add CPU cache, UFS to Tesla FSD.
2. Add reboot-mode (boot into specific bootloader mode) to ExynosAutov9.
3. Add watchdogs to ExynosAutov9.
4. Add eMMC to Exynos7885 JackpotLTE (Samsung Galaxy A8).
5. DTS cleanup: white-spaces, node names, LED color/function.
6. Switch to DTS-local header for pinctrl register values instead of
bindings header. The bindings header is being deprecated because it
does not reflect the purpose of bindings.
* tag 'samsung-dt64-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add internal eMMC support to jackpotlte
dt-bindings: clock: Add indices for Exynos7885 TREX clocks
dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS
arm64: dts: exynos: enable secondary ufs devices ExynosAutov9 SADK
arm64: dts: exynos: add secondary ufs devices in ExynosAutov9
arm64: dts: fsd: use local header for pinctrl register values
arm64: dts: exynos: use local header for pinctrl register values
arm64: dts: exynos: align MMC node name with dtschema
arm64: dts: exynos: adjust DT style of ufs nodes in ExynosAutov9
arm64: dts: exynos: adjust whitespace around '='
arm64: dts: fsd: add ufs device node
arm64: dts: exynos: add watchdog in ExynosAutov9
arm64: dts: exynos: add syscon reboot/reboot_mode support in ExynosAutov9
dt-bindings: soc: add samsung,boot-mode definitions
arm64: dts: fsd: Add cpu cache information
Link: https://lore.kernel.org/r/20220624080746.31947-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
|
Robert Marko
|
2c930dc1e3 |
dt-bindings: clocks: qcom,gcc-ipq8074: support power domains
GCC inside of IPQ8074 also provides power management via built-in GDSCs. In order to do so, '#power-domain-cells' must be set to 1. Signed-off-by: Robert Marko <robimarko@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220515210048.483898-7-robimarko@gmail.com |
||
|
Rob Herring
|
ef314d213d |
Merge branch 'dt/linus' into dt/next
Pull in the binding fixes so we don't have all the warnings. |
||
|
Krzysztof Kozlowski
|
d62cac46b0 |
dt-bindings: clock: qcom,gcc-sdm845: add parent power domain
Allow Qualcomm GCC to register its parent power domain (e.g. RPMHPD) to properly pass performance state from children. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220513061347.46480-2-krzysztof.kozlowski@linaro.org |
||
|
Samuel Holland
|
0ac1311a77 |
dt-bindings: clock: Add compatible for D1 DE2 clocks
Allwinner D1 contains a display engine 2.0. Its clock controller matches the layout of the H5 DE2 clocks (2 mixers, no rotation engine, and separate resets), so use that compatible as a fallback. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220411044002.37579-1-samuel@sholland.org |
||
|
David Virag
|
cd268e309c |
dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS
CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, MMC_SDIO), and USB30DRD. Add clock indices and bindings documentation for CMU_FSYS domain. Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220601233743.56317-2-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
||
|
Wolfram Sang
|
ee774c40fa |
dt-bindings: efm32: remove bindings for deleted platform
Commit
|
||
|
Geert Uytterhoeven
|
fc9e01676c |
dt-bindings: clock: renesas,rzg2l: Simplify header file references
The bindings already uses <dt-bindings/clock/r9a0*-cpg.h> to refer to the header files with DT binding definitions for core clocks. Use more wildcards to simplify more references to these files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/f274ad16010798dd4a45d2dca5f870da8acbb470.1654696009.git.geert+renesas@glider.be |
||
|
Samuel Holland
|
b5b3edb5a3 |
dt-bindings: clock: fixed-factor: Drop Allwinner A10 compatible
This compatible is part of the legacy sunxi clock support, and has not
been used since commit
|
||
|
Luca Ceresoli
|
216d1a8013 |
dt-bindings: update Luca Ceresoli's e-mail address
My Bootlin address is preferred from now on. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220603155727.1232061-2-luca@lucaceresoli.net |
||
|
Jeffrey Hugo
|
304e4d53dd |
dt-bindings: clock: Update my email address
Update my email address from the defunct codeaurora.org domain to the current quicinc.com domain. Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1654118992-4026-1-git-send-email-quic_jhugo@quicinc.com |
||
|
Linus Torvalds
|
b00ed48bb0 |
dmaengine updates for v5.19-rc1
New support: - Tegra gpcdma Driver support - Qualcomm SM8350, Sm8450 and SC7280 Device support - Renesas RZN1 dma and platform support Updates: - stm32 device pause/resume support and updates - DMA memset ops Documentation and usage clarification - Deprecate '#dma-channels' & '#dma-requests' bindings - Driver updates for stm32, ptdma idsx etc -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAmKTr5oACgkQfBQHDyUj g0ePBw//UP+A+PPvTdQdlq/spO9Hb76lB1UZ7x7nVsObovyO2hxQl61b5Xo9o8eH 0VIIVB9OU4ysp8eX5Y6m7CUFKa/4MyUSU1HKdspseoap3JKg1EAHEGdhjR++V/dF mqPN7VvmTbW8YDQ6b7Xz/mZedxOSJZL+wltCT2AQGLV1PD+BPZyBfkPl9NarpaX6 OeKatnMiJlZwFjQeVijiqCUx0xZV0G1XfQJDIEzRaBBvYAiHYTjbPUBZVsu5BjoC 70HtxhDKHJu0JFPa91gm7rqhj8XTKFoIGQU7jZqlpgr1IoYvfnotHoQeURa3yviZ lZ6oW0+Y3RKyCcMH5iir2YEGdeaDXEPRb1YS/rz1vcf9b8JNqxXuM9i8Z2EXCVjd qVxC9HzVCBh5EHuJGi1DFoHMrw/NXUanbWqW8C0FzqqTcqvp6DceAgzqcd1FJjwl lgZM7Y5r0WXMzbbhOeOQP34ps+mY17rsBn210K/H75fZW8kTsdwiCOL4VlaK1p/z CCJPYXkxEChbrIYoshXNTqg61bt9F2sEgJ+7FFUbUUOTLlQKFJUZ7fuoU896rDto GndspWpxaslgAzdPuWSKBeR+b9IubgLgKF1BKSTYR6coyUt+hRJFiAx1juAOYbHe CrJat0luP+hELgt1f2TjyYYZFj9Wc84tnqI+ThzXK0GyEN4Ax1c= =ANxH -----END PGP SIGNATURE----- Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine updates from Vinod Koul: "Nothing special, this includes a couple of new device support and new driver support and bunch of driver updates. New support: - Tegra gpcdma driver support - Qualcomm SM8350, Sm8450 and SC7280 device support - Renesas RZN1 dma and platform support Updates: - stm32 device pause/resume support and updates - DMA memset ops Documentation and usage clarification - deprecate '#dma-channels' & '#dma-requests' bindings - driver updates for stm32, ptdma idsx etc" * tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (87 commits) dmaengine: idxd: make idxd_wq_enable() return 0 if wq is already enabled dmaengine: sun6i: Add support for the D1 variant dmaengine: sun6i: Add support for 34-bit physical addresses dmaengine: sun6i: Do not use virt_to_phys dt-bindings: dma: sun50i-a64: Add compatible for D1 dmaengine: tegra: Remove unused switch case dmaengine: tegra: Fix uninitialized variable usage dmaengine: stm32-dma: add device_pause/device_resume support dmaengine: stm32-dma: rename pm ops before dma pause/resume introduction dmaengine: stm32-dma: pass DMA_SxSCR value to stm32_dma_handle_chan_done() dmaengine: stm32-dma: introduce stm32_dma_sg_inc to manage chan->next_sg dmaengine: stm32-dmamux: avoid reset of dmamux if used by coprocessor dmaengine: qcom: gpi: Add support for sc7280 dt-bindings: dma: pl330: Add power-domains dmaengine: stm32-mdma: use dev_dbg on non-busy channel spurious it dmaengine: stm32-mdma: fix chan initialization in stm32_mdma_irq_handler() dmaengine: stm32-mdma: remove GISR1 register dmaengine: ti: deprecate '#dma-channels' dmaengine: mmp: deprecate '#dma-channels' dmaengine: pxa: deprecate '#dma-channels' and '#dma-requests' ... |
||
|
Linus Torvalds
|
6b0e34a030 |
Mainly driver updates this time around. There's a single patch to the core clk
framework that simplifies a runtime PM call. Otherwise the majority of the diff
falls to a few SoC drivers: Qualcomm, STM32 and MediaTek. Those SoCs gain some
new hardware support and what comes along with that is quite a few lines of
data and some clk_ops code. Beyond the new hardware support we have the usual
pile of driver updates that add missing clks on already supported SoCs or fix
up problems like bad clk tree descriptions. It's nice to see that more drivers
are moving to clk_hw based APIs too.
New Drivers:
- Add STM32MP13 RCC driver (Reset Clock Controller)
- MediaTek MT8186 SoC clk support
- Airoha EN7523 SoC system clocks
- Clock driver for exynosautov9 SoC
- Renesas R-Car V4H and RZ/V2M SoCs
- Renesas RZ/G2UL SoC
- LPASS clk driver for Qualcomm sc7280 SoC
- GCC clk driver for Qualcomm SC8280XP SoC
Updates:
- SDCC uses floor clk ops on Qualcomm MSM8976
- Add modem reset and fix RPM clks on Qualcomm MSM8976
- Add the two missing CLKOUT clocks for U8500/DB8500 SoC
- Mark some clks critical on Ingenic X1000
- Convert ux500 to clk_hw
- Move MediaTek driver to clk_hw provider APIs
- Use i2c driver probe_new to avoid id scans
- Convert a number of Rockchip dt bindings to YAML
- Mark hclk_vo critical on Rockchip rk3568
- Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
- Various cleanups like memory allocation error checks and plugged leaks
- Allwinner H6 RTC clock support
- Allwinner H616 32 kHz clock support
- Add the Universal Flash Storage clock on Renesas R-Car S4-8
- Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on Renesas RZ/G2UL
- Add display clock support on Renesas RZ/G2L
- Add RPC (QSPI/HyperFlash) clocks on Renesas R-Car E3 and D3
- Add 27 MHz phy PLL ref clock on i.MX
- Add mcore_booted module parameter to tell kernel M core has already booted
for i.MX
- Remove snvs clock on i.MX because it was for secure world only
- Add dt bindings for i.MX8MN GPT
- Add DISP2 pixel clock for i.MX8MP
- Add clkout1/2 for i.MX8MP
- Fix parent clock of ubs_root_clk for i.MX8MP
- Implement better RCG parking on Qualcomm SoCs using the shared RCG clk ops
- Kerneldoc fixes
- Switch Tegra BPMP to determine_rate clk op
- Add a pointer to dt schema for generic clock bindings
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Mainly driver updates this time around.
There's a single patch to the core clk framework that simplifies a
runtime PM call. Otherwise the majority of the diff falls to a few SoC
drivers: Qualcomm, STM32 and MediaTek. Those SoCs gain some new
hardware support and what comes along with that is quite a few lines
of data and some clk_ops code.
Beyond the new hardware support we have the usual pile of driver
updates that add missing clks on already supported SoCs or fix up
problems like bad clk tree descriptions. It's nice to see that more
drivers are moving to clk_hw based APIs too.
New Drivers:
- Add STM32MP13 RCC driver (Reset Clock Controller)
- MediaTek MT8186 SoC clk support
- Airoha EN7523 SoC system clocks
- Clock driver for exynosautov9 SoC
- Renesas R-Car V4H and RZ/V2M SoCs
- Renesas RZ/G2UL SoC
- LPASS clk driver for Qualcomm sc7280 SoC
- GCC clk driver for Qualcomm SC8280XP SoC
Updates:
- SDCC uses floor clk ops on Qualcomm MSM8976
- Add modem reset and fix RPM clks on Qualcomm MSM8976
- Add the two missing CLKOUT clocks for U8500/DB8500 SoC
- Mark some clks critical on Ingenic X1000
- Convert ux500 to clk_hw
- Move MediaTek driver to clk_hw provider APIs
- Use i2c driver probe_new to avoid id scans
- Convert a number of Rockchip dt bindings to YAML
- Mark hclk_vo critical on Rockchip rk3568
- Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
- Various cleanups like memory allocation error checks and plugged
leaks
- Allwinner H6 RTC clock support
- Allwinner H616 32 kHz clock support
- Add the Universal Flash Storage clock on Renesas R-Car S4-8
- Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on Renesas
RZ/G2UL
- Add display clock support on Renesas RZ/G2L
- Add RPC (QSPI/HyperFlash) clocks on Renesas R-Car E3 and D3
- Add 27 MHz phy PLL ref clock on i.MX
- Add mcore_booted module parameter to tell kernel M core has already
booted for i.MX
- Remove snvs clock on i.MX because it was for secure world only
- Add dt bindings for i.MX8MN GPT
- Add DISP2 pixel clock for i.MX8MP
- Add clkout1/2 for i.MX8MP
- Fix parent clock of ubs_root_clk for i.MX8MP
- Implement better RCG parking on Qualcomm SoCs using the shared RCG
clk ops
- Kerneldoc fixes
- Switch Tegra BPMP to determine_rate clk op
- Add a pointer to dt schema for generic clock bindings"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (168 commits)
Revert "clk: qcom: regmap-mux: add pipe clk implementation"
Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc()
clk: stm32mp13: add safe mux management
clk: stm32mp13: add multi mux function
clk: stm32mp13: add all STM32MP13 kernel clocks
clk: stm32mp13: add all STM32MP13 peripheral clocks
clk: stm32mp13: manage secured clocks
clk: stm32mp13: add composite clock
clk: stm32mp13: add stm32 divider clock
clk: stm32mp13: add stm32_gate management
clk: stm32mp13: add stm32_mux clock management
clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)
dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
clk: ti: clkctrl: replace usage of found with dedicated list iterator variable
clk: ti: composite: Prefer kcalloc over open coded arithmetic
dt-bindings: clock: exynosautov9: correct count of NR_CLK
clk: mediatek: mt8173: Switch to clk_hw provider APIs
clk: mediatek: Switch to clk_hw provider APIs
...
|
||
|
Linus Torvalds
|
16477cdfef |
asm-generic changes for 5.19
The asm-generic tree contains three separate changes for linux-5.19:
- The h8300 architecture is retired after it has been effectively
unmaintained for a number of years. This is the last architecture we
supported that has no MMU implementation, but there are still a few
architectures (arm, m68k, riscv, sh and xtensa) that support CPUs with
and without an MMU.
- A series to add a generic ticket spinlock that can be shared by most
architectures with a working cmpxchg or ll/sc type atomic, including
the conversion of riscv, csky and openrisc. This series is also a
prerequisite for the loongarch64 architecture port that will come as
a separate pull request.
- A cleanup of some exported uapi header files to ensure they can be
included from user space without relying on other kernel headers.
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Merge tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic
Pull asm-generic updates from Arnd Bergmann:
"The asm-generic tree contains three separate changes for linux-5.19:
- The h8300 architecture is retired after it has been effectively
unmaintained for a number of years. This is the last architecture
we supported that has no MMU implementation, but there are still a
few architectures (arm, m68k, riscv, sh and xtensa) that support
CPUs with and without an MMU.
- A series to add a generic ticket spinlock that can be shared by
most architectures with a working cmpxchg or ll/sc type atomic,
including the conversion of riscv, csky and openrisc. This series
is also a prerequisite for the loongarch64 architecture port that
will come as a separate pull request.
- A cleanup of some exported uapi header files to ensure they can be
included from user space without relying on other kernel headers"
* tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic:
h8300: remove stale bindings and symlink
sparc: add asm/stat.h to UAPI compile-test coverage
powerpc: add asm/stat.h to UAPI compile-test coverage
mips: add asm/stat.h to UAPI compile-test coverage
riscv: add linux/bpf_perf_event.h to UAPI compile-test coverage
kbuild: prevent exported headers from including <stdlib.h>, <stdbool.h>
agpgart.h: do not include <stdlib.h> from exported header
csky: Move to generic ticket-spinlock
RISC-V: Move to queued RW locks
RISC-V: Move to generic spinlocks
openrisc: Move to ticket-spinlock
asm-generic: qrwlock: Document the spinlock fairness requirements
asm-generic: qspinlock: Indicate the use of mixed-size atomics
asm-generic: ticket-lock: New generic ticket-based spinlock
remove the h8300 architecture
|
||
|
Linus Torvalds
|
ae86218328 |
ARM: DT changes for 5.19, part 1
There are 40 branches this time, adding a lot of new hardware
support, and cleanups. Krzysztof Kozlowski continues his treewide
cleanups.
There are a number of new SoCs, all of them as part of existing
families, and typically added along with a reference board:
- Renesas RZ/G2UL (R9A07G043) is the single-core version of the RZ/G2L
general-purpose MPU.
- Renesas RZ/V2M (R9A09G011) is a smart camera SoC
- Renesas R-Car V4H (R8A779G0) is an automotive chip with Cortex-A76
cores and deep learning accerlation.
- Broadcom BCM47622 is a new broadband SoC based on a quad Cortex-A7
and dual Wifi-6.
- Corstone1000 is a generic platform from Arm that is used for designing
custom SoCs, the support for now is for the Fixed Virtual Platform
emulation for it.
- Mediatek MT8195 (Kompanio 1200) is a high-end consumer chip used
in upcoming Chromebooks.
- NXP i.MXRT1050 is a Cortex-M7 based microcontroller, the first
MMU-less SoC to be added in a while
New machines based on already supported SoCs this time are mainly
for 32-bit platforms and include:
- Two wireless routers based on Broadcom bcm4708
- 30 new boards based on NXP i.MX6, i.MX7 and i.MX8 families, mostly
for the industrial embedded market, and on NXP LS1021A based
IOT board.
- Two ethernet switches based on Microchip LAN966
- Eight Qualcomm Snapdragon based machines, including a smartwatch,
a Chromebook board and some phones
- Another phone based on the old ST-Ericsson Ux500 platform
- Seven STM32MP1 based boards
- Four single-board computers based on Rockchip RK3566/RK3568
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Merge tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM DT updates from Arnd Bergmann:
"There are 40 branches this time, adding a lot of new hardware support,
and cleanups. Krzysztof Kozlowski continues his treewide cleanups.
There are a number of new SoCs, all of them as part of existing
families, and typically added along with a reference board:
- Renesas RZ/G2UL (R9A07G043) is the single-core version of the
RZ/G2L general-purpose MPU.
- Renesas RZ/V2M (R9A09G011) is a smart camera SoC
- Renesas R-Car V4H (R8A779G0) is an automotive chip with Cortex-A76
cores and deep learning accerlation.
- Broadcom BCM47622 is a new broadband SoC based on a quad Cortex-A7
and dual Wifi-6.
- Corstone1000 is a generic platform from Arm that is used for
designing custom SoCs, the support for now is for the Fixed Virtual
Platform emulation for it.
- Mediatek MT8195 (Kompanio 1200) is a high-end consumer chip used in
upcoming Chromebooks.
- NXP i.MXRT1050 is a Cortex-M7 based microcontroller, the first
MMU-less SoC to be added in a while
New machines based on already supported SoCs this time are mainly for
32-bit platforms and include:
- Two wireless routers based on Broadcom bcm4708
- 30 new boards based on NXP i.MX6, i.MX7 and i.MX8 families, mostly
for the industrial embedded market, and on NXP LS1021A based IOT
board.
- Two ethernet switches based on Microchip LAN966
- Eight Qualcomm Snapdragon based machines, including a smartwatch, a
Chromebook board and some phones
- Another phone based on the old ST-Ericsson Ux500 platform
- Seven STM32MP1 based boards
- Four single-board computers based on Rockchip RK3566/RK3568"
* tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (791 commits)
ARM: dts: kswitch-d10: enable networking
ARM: dts: lan966x: add switch node
ARM: dts: lan966x: add serdes node
ARM: dts: lan966x: add reset switch reset node
ARM: dts: lan966x: add MIIM nodes
ARM: dts: lan966x: add hwmon node
ARM: dts: lan966x: add basic Kontron KSwitch D10 support
ARM: dts: lan966x: add flexcom I2C nodes
ARM: dts: lan966x: add flexcom SPI nodes
ARM: dts: lan966x: add all flexcom usart nodes
ARM: dts: lan966x: add missing uart DMA channel
ARM: dts: lan966x: add sgpio node
ARM: dts: lan966x: swap dma channels for crypto node
ARM: dts: lan966x: rename pinctrl nodes
ARM: dts: at91: sama7g5: remove interrupt-parent from gic node
ARM: dts: at91: use generic node name for dataflash
ARM: dts: turris-omnia: Add atsha204a node
arm64: dts: mt8192: Follow binding order for SCP registers
arm64: dts: mediatek: add mtk-snfi for mt7622
arm64: dts: mediatek: mt8195-demo: enable uart1
...
|
||
|
Linus Torvalds
|
86c87bea6b |
Devicetree updates for v5.19:
Bindings:
- Convert smsc,lan91c111, qcom,spi-qup, qcom,msm-uartdm, qcom,i2c-qup,
qcom,gsbi, i2c-mt65xx, TI wkup_m3_ipc (and new props), qcom,smp2p, TI
timer, Mediatek gnss, Mediatek topckgen, Mediatek apmixedsys, Mediatek
infracfg, fsl,ls-extirq, fsl,layerscape-dcfg, QCom PMIC SPMI,
rda,8810pl-timer, Xilinx zynqmp_ipi, uniphier-pcie, and Ilitek
touchscreen controllers
- Convert various Arm Ltd peripheral IP bindings to schemas
- New bindings for Menlo board CPLD, DH electronics board CPLD,
Qualcomm Geni based QUP I2C, Renesas RZ/G2UL OSTM, Broafcom BCM4751
GNSS, MT6360 PMIC, ASIX USB Ethernet controllers, and Microchip/SMSC
LAN95xx USB Ethernet controllers
- Add vendor prefix for Enclustra
- Add various compatible string additions
- Various example fixes and cleanups
- Remove unused hisilicon,hi6220-reset binding
- Treewide fix properties missing type definition
- Drop some empty and unreferenced .txt bindings
- Documentation improvements for writing schemas
DT driver core:
- Drop static IRQ resources for DT platform devices as IRQ setup is
dynamic and drivers have all been converted to use platform_get_irq()
and friends
- Rework memory allocations and frees for overlays
- Continue overlay notifier callbacks on successful calls and add
unittests
- Handle 'interrupts-extended' in early DT IRQ setup
- Fix of_property_read_string() errors to match documentation
- Ignore disabled nodes in FDT API calls
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Merge tag 'devicetree-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"Bindings:
- Convert smsc,lan91c111, qcom,spi-qup, qcom,msm-uartdm,
qcom,i2c-qup, qcom,gsbi, i2c-mt65xx, TI wkup_m3_ipc (and new
props), qcom,smp2p, TI timer, Mediatek gnss, Mediatek topckgen,
Mediatek apmixedsys, Mediatek infracfg, fsl,ls-extirq,
fsl,layerscape-dcfg, QCom PMIC SPMI, rda,8810pl-timer, Xilinx
zynqmp_ipi, uniphier-pcie, and Ilitek touchscreen controllers
- Convert various Arm Ltd peripheral IP bindings to schemas
- New bindings for Menlo board CPLD, DH electronics board CPLD,
Qualcomm Geni based QUP I2C, Renesas RZ/G2UL OSTM, Broafcom BCM4751
GNSS, MT6360 PMIC, ASIX USB Ethernet controllers, and
Microchip/SMSC LAN95xx USB Ethernet controllers
- Add vendor prefix for Enclustra
- Add various compatible string additions
- Various example fixes and cleanups
- Remove unused hisilicon,hi6220-reset binding
- Treewide fix properties missing type definition
- Drop some empty and unreferenced .txt bindings
- Documentation improvements for writing schemas
DT driver core:
- Drop static IRQ resources for DT platform devices as IRQ setup is
dynamic and drivers have all been converted to use
platform_get_irq() and friends
- Rework memory allocations and frees for overlays
- Continue overlay notifier callbacks on successful calls and add
unittests
- Handle 'interrupts-extended' in early DT IRQ setup
- Fix of_property_read_string() errors to match documentation
- Ignore disabled nodes in FDT API calls"
* tag 'devicetree-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (86 commits)
of/irq: fix typo in comment
dt-bindings: Fix properties without any type
Revert "dt-bindings: mailbox: qcom-ipcc: add missing properties into example"
dt-bindings: input: touchscreen: ilitek_ts_i2c: Absorb ili2xxx bindings
dt-bindings: timer: samsung,exynos4210-mct: define strict clock order
dt-bindings: timer: samsung,exynos4210-mct: drop unneeded minItems
dt-bindings: timer: cdns,ttc: drop unneeded minItems
dt-bindings: mailbox: zynqmp_ipi: convert to yaml
dt-bindings: usb: ci-hdrc-usb2: fix node node for ethernet controller
dt-bindings: net: add schema for Microchip/SMSC LAN95xx USB Ethernet controllers
dt-bindings: net: add schema for ASIX USB Ethernet controllers
of/fdt: Ignore disabled memory nodes
dt-bindings: arm: fix typos in compatible
dt-bindings: mfd: Add bindings child nodes for the Mediatek MT6360
dt-bindings: display: convert Arm Komeda to DT schema
dt-bindings: display: convert Arm Mali-DP to DT schema
dt-bindings: display: convert Arm HDLCD to DT schema
dt-bindings: display: convert PL110/PL111 to DT schema
dt-bindings: arm: convert vexpress-config to DT schema
dt-bindings: arm: convert vexpress-sysregs to DT schema
...
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Stephen Boyd
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71cc785d29 |
Merge branch 'clk-qcom' into clk-next
* clk-qcom: Revert "clk: qcom: regmap-mux: add pipe clk implementation" Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks" Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks" clk: qcom: rcg2: Cache CFG register updates for parked RCGs clk: qcom: add sc8280xp GCC driver dt-bindings: clock: Add Qualcomm SC8280XP GCC bindings clk: qcom: gcc-msm8976: Add modem reset dt-bindings: clk: qcom: gcc-msm8976: Add modem reset clk: qcom: gcc-msm8976: Set floor ops for SDCC dt-bindings: clock: qcom,gcc-apq8064: Fix typo in compatible and split apq8084 clk: qcom: smd: Update MSM8976 RPM clocks. clk: qcom: gcc-msm8998: add SSC-related clocks dt-bindings: clock: gcc-msm8998: Add definitions of SSC-related clocks dt-bindings: clock: qcom,rpmcc: add clocks property dt-bindings: clock: qcom,rpmcc: convert to dtschema clk: qcom: lpass: Add support for LPASS clock controller for SC7280 dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks clk: qcom: regmap-mux: add pipe clk implementation |
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Stephen Boyd
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d75c26a926 |
Merge branches 'clk-rockchip', 'clk-ingenic', 'clk-bindings', 'clk-samsung' and 'clk-stm' into clk-next
- Mark some clks critical on Ingenic X1000 - Add STM32MP13 RCC driver (Reset Clock Controller) * clk-rockchip: dt-bindings: clock: convert rockchip,rk3368-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3228-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3036-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3308-cru.txt to YAML dt-bindings: clock: convert rockchip,px30-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3188-cru.txt to YAML dt-bindings: clock: convert rockchip,rk3288-cru.txt to YAML dt-bindings: clock: convert rockchip,rv1108-cru.txt to YAML dt-binding: clock: Add missing rk3568 cru bindings clk: rockchip: Mark hclk_vo as critical on rk3568 dt-bindings: clock: fix rk3399 cru clock issues dt-bindings: clock: use generic node name for pmucru example in rockchip,rk3399-cru.yaml dt-bindings: clock: replace a maintainer for rockchip,rk3399-cru.yaml dt-bindings: clock: fix some conversion style issues for rockchip,rk3399-cru.yaml * clk-ingenic: clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCs mips: ingenic: Do not manually reference the CPU clock clk: ingenic: Mark critical clocks in Ingenic SoCs clk: ingenic: Allow specifying common clock flags * clk-bindings: dt-bindings: clock: Replace common binding with link to schema * clk-samsung: dt-bindings: clock: exynosautov9: correct count of NR_CLK clk: samsung: exynosautov9: add cmu_peric1 clock support clk: samsung: exynosautov9: add cmu_peric0 clock support clk: samsung: exynosautov9: add cmu_fsys2 clock support clk: samsung: exynosautov9: add cmu_busmc clock support clk: samsung: exynosautov9: add cmu_peris clock support clk: samsung: exynosautov9: add cmu_core clock support clk: samsung: add top clock support for Exynos Auto v9 SoC dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings dt-bindings: clock: add clock binding definitions for Exynos Auto v9 * clk-stm: clk: stm32mp13: add safe mux management clk: stm32mp13: add multi mux function clk: stm32mp13: add all STM32MP13 kernel clocks clk: stm32mp13: add all STM32MP13 peripheral clocks clk: stm32mp13: manage secured clocks clk: stm32mp13: add composite clock clk: stm32mp13: add stm32 divider clock clk: stm32mp13: add stm32_gate management clk: stm32mp13: add stm32_mux clock management clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller) dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC |
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Stephen Boyd
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d3d88716a6 |
Merge branches 'clk-ux500', 'clk-mtk', 'clk-tegra', 'clk-allwinner' and 'clk-imx' into clk-next
- Convert ux500 to clk_hw - Add the two missing CLKOUT clocks for U8500/DB8500 SoC - MediaTek MT8186 SoC clk support - Move MediaTek driver to clk_hw provider APIs * clk-ux500: clk: ux500: fix a possible off-by-one in u8500_prcc_reset_base() clk: ux500: Implement the missing CLKOUT clocks clk: ux500: Rewrite PRCMU clocks to use clk_hw_* clk: ux500: Drop .is_prepared state from PRCMU clocks clk: ux500: Drop .is_enabled state from PRCMU clocks dt-bindings: clock: u8500: Add clkout clock bindings * clk-mtk: (22 commits) clk: mediatek: mt8173: Switch to clk_hw provider APIs clk: mediatek: Switch to clk_hw provider APIs clk: mediatek: Replace 'struct clk' with 'struct clk_hw' clk: mediatek: apmixed: Drop error message from clk_register() failure clk: mediatek: Make mtk_clk_register_composite() static clk: mediatek: use en_mask as a pure div_en_mask clk: mediatek: update compatible string for MT7986 ethsys clk: mediatek: Add MT8186 ipesys clock support clk: mediatek: Add MT8186 mdpsys clock support clk: mediatek: Add MT8186 camsys clock support clk: mediatek: Add MT8186 vencsys clock support clk: mediatek: Add MT8186 vdecsys clock support clk: mediatek: Add MT8186 imgsys clock support clk: mediatek: Add MT8186 wpesys clock support clk: mediatek: Add MT8186 mmsys clock support clk: mediatek: Add MT8186 mfgsys clock support clk: mediatek: Add MT8186 imp i2c wrapper clock support clk: mediatek: Add MT8186 apmixedsys clock support clk: mediatek: Add MT8186 infrastructure clock support clk: mediatek: Add MT8186 topckgen clock support ... * clk-tegra: clk: tegra: Update kerneldoc to match prototypes clk: tegra: Replace .round_rate() with .determine_rate() clk: tegra: Register clocks from root to leaf clk: tegra: Add missing reset deassertion * clk-allwinner: clk: sunxi-ng: h616: Add PLL derived 32KHz clock clk: sunxi-ng: h6-r: Add RTC gate clock * clk-imx: clk: imx8mp: fix usb_root_clk parent clk: imx8mp: add clkout1/2 support clk: imx: scu: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage clk: imx8mp: Add DISP2 pixel clock clk: imx: scu: fix a potential memory leak in __imx_clk_gpr_scu() clk: imx: Add check for kcalloc clk: imx8mn: add GPT support dt-bindings: imx: add clock bindings for i.MX8MN GPT clk: imx: Remove the snvs clock clk: imx8m: check mcore_booted before register clk clk: imx: add mcore_booted module paratemter clk: imx8mq: add 27m phy pll ref clock |
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Stephen Boyd
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2c29798c5d |
Merge branches 'clk-ti', 'clk-cleanup', 'clk-airoha', 'clk-i2c-simple' and 'clk-renesas' into clk-next
- Airoha EN7523 SoC system clocks
- Use i2c driver probe_new to avoid id scans
* clk-ti:
clk: ti: clkctrl: replace usage of found with dedicated list iterator variable
clk: ti: composite: Prefer kcalloc over open coded arithmetic
clk: keystone: syscon-clk: Add support for AM62 epwm-tbclk
dt-bindings: clock: ehrpwm: Add AM62 specific compatible
* clk-cleanup:
clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc()
clk: fixed-rate: Remove redundant if statement
clk: mux: remove redundant initialization of variable width
clk: using pm_runtime_resume_and_get instead of pm_runtime_get_sync
clk: actions: remove redundant assignment after a mask operation
* clk-airoha:
clk: en7523: fix wrong pointer check in en7523_clk_probe()
clk: en7523: Add clock driver for Airoha EN7523 SoC
dt-bindings: Add en7523-scu device tree binding documentation
* clk-i2c-simple:
clk: renesas-pcie: use simple i2c probe function
clk: si570: use i2c_match_id and simple i2c probe
clk: si544: use i2c_match_id and simple i2c probe
clk: si5351: use i2c_match_id and simple i2c probe
clk: si5341: use simple i2c probe function
clk: si514: use simple i2c probe function
clk: max9485: use simple i2c probe function
clk: cs2000-cp: use simple i2c probe function
clk: cdce925: use i2c_match_id and simple i2c probe
clk: cdce706: use simple i2c probe function
* clk-renesas: (48 commits)
clk: renesas: r9a09g011: Add eth clock and reset entries
clk: renesas: Add RZ/V2M support using the rzg2l driver
clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg
clk: renesas: rzg2l: Make use of CLK_MON registers optional
clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
clk: renesas: rzg2l: Add read only versions of the clk macros
clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro
dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC
clk: renesas: r9a07g044: Fix OSTM1 module clock name
clk: renesas: r9a07g043: Add clock and reset entries for ADC
clk: renesas: r9a07g043: Add TSU clock and reset entry
clk: renesas: r9a07g043: Add RSPI clock and reset entries
clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller
clk: renesas: r9a07g044: Add DSI clock and reset entries
clk: renesas: r9a07g044: Add LCDC clock and reset entries
clk: renesas: r9a07g044: Add M4 Clock support
clk: renesas: r9a07g044: Add M3 Clock support
clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support
clk: renesas: r9a07g044: Add M1 clock support
clk: renesas: rzg2l: Add DSI divider clk support
...
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Gabriel Fernandez
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722dc8a1d5 |
dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
New compatible to manage clock and reset of STM32MP13 SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-2-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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Arnd Bergmann
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b2441b3bdc |
h8300: remove stale bindings and symlink
These four files are left over from the h8300 removal. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
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Rob Herring
|
f538ce1123 |
dt-bindings: clock: Replace common binding with link to schema
The contents of the clock binding have been moved to the clock binding schema in the dtschema repository. The desire is for common bindings to be hosted in the dtschema repository. Replace the contents with a link to the clock binding schema as there are still many references to clock-bindings.txt in the tree. This will prevent additions without a schema. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220428154154.2284317-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> |