There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The oxnas NAND driver is only needed for a specific platform, do
not propose it on other platforms unless build-testing.
Signed-off-by: Jean Delvare <jdelvare@suse.de>
Fixes: 6685924924 ("mtd: nand: Add OX820 NAND Support")
Cc: Rob Herring <robh@kernel.org>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The FSMC driver has an execution path and a header file in
<linux/mtd/fsmc.h> that serves to support passing in platform
data through board files, albeit no upstream users of this
mechanism exist.
The header file also contains function headers for functions that
do not exist in the kernel.
Delete this and move the platform data struct, parsing and
handling into the driver, assume we are using OF and make the
driver depend on OF, remove the ifdefs making that optional.
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
devm_ioremap_resource() does a NULL check on the 'rc' argument, so
remove the unneeded manual NULL check.
While at it, place the 'rc' assignment just before
devm_ioremap_resource() to improve readability.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Semantics of NR_IRQS is different on machines with SPARSE_IRQ option
disabled or enabled, in the latter case IRQs are allocated starting
at least from the value specified by NR_IRQS and going upwards, so
the check of (irq >= NR_IRQ) to decide about an error code returned by
platform_get_irq() is completely invalid, don't attempt to overrule
irq subsystem in the driver.
The change fixes LPC32xx NAND MLC driver initialization on boot.
Fixes: 8cb17b5ed0 ("irqchip: Add LPC32xx interrupt controller driver")
Cc: stable@kernel.org # v4.7+
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Linux should not expect the boot loader to properly configure the
peripheral bus "pad mode", so reset PBUS_PAD_MODE to raw.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Visually separate register ranges (address/size pairs) in reg prop.
Change DMA channel name, for consistency with other drivers.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fix build errors on arch/um, which does not support HAS_IOMEM,
while the oxnas_nand.c driver uses interfaces that are
supplied by HAS_IOMEM.
(loadable module build:)
ERROR: "devm_ioremap_resource" [drivers/mtd/nand/oxnas_nand.ko] undefined!
or (built-in build:)
drivers/built-in.o: In function `oxnas_nand_probe':
drivers/mtd/nand/oxnas_nand.c:102: undefined reference to `devm_ioremap_resource'
Fixes: 6685924924 ("mtd: nand: Add OX820 NAND Support")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Remove the usage of modules functions to make this driver compile
again. Otherwise an include of linux/modules.h would be needed.
Fixes: 024366750c ("mtd: nand: xway: convert to normal platform driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The xway_nand driver accesses the ltq_ebu_membase symbol which is not
exported. This also should not get exported and we should handle the
EBU interface in a better way later. This quick fix just deactivated
support for building as module.
Fixes: 99f2b10792 ("mtd: lantiq: Add NAND support on Lantiq XWAY SoC.")
Cc: <stable@vger.kernel.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Provide proper copyright notice and license information.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
- new tango NAND controller driver
- new ox820 NAND controller driver
- addition of a new full-ID entry in the nand_ids table
- rework of the s3c240 driver to support DT
- extension of the nand_sdr_timings to expose tCCS, tPROG and tR
- addition of a new flag to ask the core to wait for tCCS when sending
a RNDIN/RNDOUT command
- addition of a new flag to ask the core to let the controller driver
send the READ/PROGPAGE command
This pull request also contains minor fixes/cleanup/cosmetic changes:
- properly support 512 ECC step size in the sunxi driver
- improve the error messages in the pxa probe path
- fix module autoload in the omap2 driver
- cleanup of several nand drivers to return nand_scan{_tail}() error
code instead of returning -EIO
- various cleanups in the denali driver
- cleanups in the ooblayout handling (MTD core)
- fix an error check in nandsim
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYOu/YAAoJEGXtNgF+CLcAVZ4P/0Vi50SSLZ2EUOQqAbiQcUPV
iO/20OPkTAXz6+Mi/csKZEnPGqpy2srn8MOgJx0gVO7b7hrhli6aBQJDxHLhGHVl
N1hpTkZewZisLC1ewc9SA2SF/6zs93Bfk9cw0i4YxgE2gKPvZWT89Y9aZ/m/OWyW
su0kis5YhMcAz2Oqq6oaCfRmbcMR62KkcjfB4U17FgXK56C5ziO7MoLjeAyYpi+f
vHGzWFoDKHLfo4ISFq5inqB8pk6nQtkaERhx+y4WCwOcvMoOjOU9gWN1yyLyLsdp
jimqdJegRlC63RkLoO5KNJqa3AlSTIpccIJaL2p8yHf/dtJQmhHXOl/gKgiO217n
LMmeVJhMqUA652BJeXnyqg4VScTQFhwITccUFFauMEiRCzJWM6W1uzJZiGoWsrLG
aKBYlWv+Z1dPGILf5AQobz16FuEsdVc60Fc4M02sL4QiH9TO2mg103licgiYdPIw
0YcJ23t7KDf66uyGKvZwcDJSkJEKPkf5YEDi7VOFZF4CuaYKMqMo7oCb8PTKNMBP
tMQpQ9cjaVBGv/vXHneBsyin/1wsKN0tAnbuh/cUT1sGa+JiEjGdeCm9o30G3334
9YUZrPCwcN6mw5rOrD7Ts33OYONDAqCHJoP5IZovD8pbguEYAYZ2KFyHgu2KRQa3
kMVq7QE0jvn956SVw1uD
=og/Y
-----END PGP SIGNATURE-----
Merge tag 'nand/for-4.10' of github.com:linux-nand/linux
From Boris Brezillon:
"""
This pull request contains the following notable changes:
- new tango NAND controller driver
- new ox820 NAND controller driver
- addition of a new full-ID entry in the nand_ids table
- rework of the s3c240 driver to support DT
- extension of the nand_sdr_timings to expose tCCS, tPROG and tR
- addition of a new flag to ask the core to wait for tCCS when sending
a RNDIN/RNDOUT command
- addition of a new flag to ask the core to let the controller driver
send the READ/PROGPAGE command
This pull request also contains minor fixes/cleanup/cosmetic changes:
- properly support 512 ECC step size in the sunxi driver
- improve the error messages in the pxa probe path
- fix module autoload in the omap2 driver
- cleanup of several nand drivers to return nand_scan{_tail}() error
code instead of returning -EIO
- various cleanups in the denali driver
- cleanups in the ooblayout handling (MTD core)
- fix an error check in nandsim
"""
The nand_to_mtd() helper is here to hide internal mtd_info <-> nand_chip
association and ease future refactors.
Make use of this helper instead of directly accessing chip->mtd.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
debugfs_create_dir() and debugfs_create_file() returns NULL on error or
a pointer on success. They do not return the error value with ERR_PTR.
So we should not check the return with IS_ERR_OR_NULL, instead we
should just check for NULL.
Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Drop raw_write return value (no longer used).
Drop raw_read return value (for symmetry).
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Enable NAND_ECC_CUSTOM_PAGE_ACCESS in the tango NFC driver.
Fixup the "raw" page accessors to send the proper NAND commands.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
If your controller already sends the required NAND commands when
reading or writing a page, then the framework is not supposed to
send READ0 and SEQIN/PAGEPROG respectively.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Such debug lines might be useful when debugging the driver first,
but should be deleted from the upstream code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Remove parentheses surrounding the whole right side of an assignment.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident/tail() returns an appropriate error value when
it fails. Use it instead of the fixed -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The devm_request_irq() returns an appropriate error value when it
fails. Use it instead of the fixed -ENODEV.
While we are here, reword the comment to make it fit in a single
line, fixing the misspelling of "initialization".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Use the managed variant instead of request_irq() and free_irq().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The denali->blksperchip is set, but not referenced any more. The
denali->totalblks is used only for calculating denali->blksperchip.
Both of them are unneeded.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
As far as I understood from the Kconfig menu deleted by commit
be7f39c5ec ("Staging: delete spectra driver"), the "Spectra" is
specific to Intel Moorestown Platform.
The Denali NAND controller IP is used for various SoCs such as
Altera SOCFPGA, Socionext UniPhier, etc. The platform specific
strings are not preferred in this driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The denali->fwblks is set by detect_partition_feature(), but it is
not referenced from anywhere. That means the struct member fwblks
and the whole of detect_partition_feature() are unneeded.
The comment block implies this function is only for Intel platforms.
I found drivers/staging/spectra used to exist, but it was deleted by
commit be7f39c5ec ("Staging: delete spectra driver") 5 years ago.
So, I guess nobody would need this function any more.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The interrupt handler is setup in denali_init(), not in
denali_drv_init(). This comment is false.
Such a comment adds no value, so just delete it instead of move.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The struct member "idx" was used as an index for debug_array long
ago, but the DEBUG_DENALI feature was removed by commit 7cfffac06c
("nand/denali: use dev_xx debug function to replace nand_dbg_print
and some printk"). Since then, this has been only initialized, but
never referenced.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The driver calls devm_kzalloc()/devm_kfree() to allocate/free memory.
They are declared in <linux/device.h>, not in <linux/slab.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
For this driver, there is nothing between nand_scan_ident() and
nand_scan_tail(). They can be merged into nand_scan().
Also, nand_scan() returns an appropriate error value when it fails.
Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident/tail() never returns a positive value when it
fails.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident() returns an appropriate error value when it
fails. Use it instead of the fixed error code -ENODEV.
(This driver is already doing so for nand_scan_tail().)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident() returns an appropriate error value when it
fails. Use it instead of the fixed error code -ENODEV.
(This driver is already doing so for nand_scan_tail().)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident() returns an appropriate error value when it
fails. Use it instead of the fixed error code -ENXIO.
(This driver is already doing so for nand_scan_tail().)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident/tail() returns an appropriate error value when
it fails. Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident/tail() returns an appropriate error value when
it fails. Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident/tail() returns an appropriate error value when
it fails. Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident/tail() returns an appropriate error value when
it fails. Use it instead of the fixed error code -ENODEV.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident/tail() returns an appropriate error value when
it fails. Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident/tail() returns an appropriate error value when
it fails. Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident/tail() returns an appropriate error value when
it fails. Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan_ident/tail() returns an appropriate error value when
it fails. Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan() returns an appropriate error value when it fails.
Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan() returns an appropriate error value when it fails.
Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan() returns an appropriate error value when it fails.
Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan() returns an appropriate error value when it fails.
Use it instead of the fixed error code -ENODEV.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan() returns an appropriate error value when it fails.
Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan() returns an appropriate error value when it fails.
Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan() returns an appropriate error value when it fails.
Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan() returns an appropriate error value when it fails.
Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The nand_scan() returns an appropriate error value when it fails.
Use it instead of the fixed error code -ENXIO.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Since commit d1e1f4e42b ("mtd: nand: add support for reading ONFI
parameters from NAND device"), the returned "type" is never used in
nand_scan_ident().
Make nand_get_flash_type() simply return an integer value in order
to avoid unnecessary ERR_PTR/PTR_ERR dance.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The denali_dt_probe() calls clk_disable_unprepare() in the bailout
path, whereas denali_dt_remove calls clk_disable(), inconsistently.
Replace the latter with clk_disable_unprepare() to make sure to
unprepare the clock.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This driver supports the NAND Flash controller embedded in recent
Tango chips, such as SMP8758 and SMP8759.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
For some error paths alloc_nand_resource() emitted an error message, for
others it didn't. Make it consistently print a message including the
error code where it's not constant and drop the hardly helpful
additional message printed by the caller of alloc_nand_resource.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Drivers implementing ->cmd_ctrl() and relying on the default ->cmdfunc()
implementation usually don't wait tCCS when a column change (RNDIN or
RNDOUT) is requested.
Add an option flag to ask the core to do so (note that we keep this as
an opt-in to avoid breaking existing implementations), and make use of
the ->data_interface information is available (otherwise, wait 500ns).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Add the tR_max, tBERS_max, tPROG_max and tCCS_min timings to the
nand_sdr_timings struct.
Assign default/safe values for the statically defined timings, and
extract them from the ONFI parameter table if the NAND is ONFI
compliant.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode
field in the drivers's platform data structure so it can be selectable
via platform data.
Also setting this field to NAND_ECC_SOFT in all boards using this
driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.
Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
When building with -Wmaybe-uninitialized, gcc produces a silly false positive
warning for the mtk_ecc_encode function:
drivers/mtd/nand/mtk_ecc.c: In function 'mtk_ecc_encode':
drivers/mtd/nand/mtk_ecc.c:402:15: error: 'val' may be used uninitialized in this function [-Werror=maybe-uninitialized]
The function for some reason contains a double byte swap on big-endian
builds to get the OOB data into the correct order again, and is written
in a slightly confusing way.
Using a simple memcpy32_fromio() to read the data simplifies it a lot
so it becomes more readable and produces no warning. However, the
output might not have 32-bit alignment, so we have to use another
memcpy to avoid taking alignment faults or writing beyond the end
of the array.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: RogerCC Lin <rogercc.lin@mediatek.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
When changing from one data interface setting to another, one has to
ensure a specific sequence which is described in the ONFI spec.
One of these constraints is that the CE line has go high after a reset
before a command can be sent with the new data interface setting, which
is not guaranteed by the current implementation.
Rework the nand_reset() function and all the call sites to make sure the
CE line is asserted and released when required.
Also make sure to actually apply the new data interface setting on the
first die.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: d8e725dd83 ("mtd: nand: automate NAND timings selection")
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
We should disable the previously enabled GPMI clocks in the error paths.
Also, when gpmi_enable_clk() fails simply return the error
code immediately rather than jumping to to the 'err_out' label.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Add NAND driver to support the Oxford Semiconductor OX820 NAND Controller.
This is a simple memory mapped NAND controller with single chip select and
software ECC.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Add the description of the Toshiba TC58NVG2S0H SLC nand to the nand_ids
table so we can use the NAND ECC infos and the ONFI timings.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The driver is incorrectly assuming that the ECC block size is always 1k
which is not always true.
Also take the other cases into account.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
If the driver is built as a module, autoload won't work because the module
alias information is not filled. So user-space can't match the registered
device with the corresponding module.
Export the module alias information using the MODULE_DEVICE_TABLE() macro.
Before this patch:
$ modinfo drivers/mtd/nand/omap2_nand.ko | grep alias
alias: platform:omap2-nand
After this patch:
$ modinfo drivers/mtd/nand/omap2_nand.ko | grep alias
alias: platform:omap2-nand
alias: of:N*T*Cti,omap2-nandC*
alias: of:N*T*Cti,omap2-nand
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
NAND:
* Add the infrastructure to automate NAND timings configuration
* Provide a generic DT property to maximize ECC strength
* Some refactoring in the core bad block table handling, to help with
improving some of the logic in error cases.
* Minor cleanups and fixes
MTD:
* Add APIs for handling page pairing; this is necessary for reliably
supporting MLC and TLC NAND flash, where paired-page disturbance affects
reliability. Upper layers (e.g., UBI) should make use of these in the near
future.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJX+cr9AAoJEFySrpd9RFgtSmcP/AvaNRXlrmKbZKg07kpJj3Ja
XtxhftUwz7ncbjls99TD6ObGxWThIJ8U3oLsI5yoofJWiik5KaUk4jXUIVkGF5hm
m1cDUX4biCwctdJzG03jboquFgwKP/atxxFCvEigauW3EafmUL4KrkrQ/bqOu7qN
TDDyDL2K+v96lR2lYhCxWMZHcwK2ORGxbxdxfTqVE/NMLk217gHcrJEfJISPodfb
A9dU/h7gLYF49E5L04Cko1I5HTnyhGPjQGIB/h8dIUlxtrzy1NRGG3IYo5gkdbve
7yRSzbQB0jokcFdz1kg2SLXJZRArs9pYWUkFGGnYFaDGuFentyySaKgs+SO9gJHG
wY48IL+RFlR0PF2PKVSdXLf9vgcjoVg9Oi2X5Ap4QJDZaTQqf0P0uz4aRTUbphQx
/zY6X4Z6DWUXmLncz2tJ+ruwGoEZaUdXvX3/2ov0UnDjZ+w8hGuNNscE6xrrnKGf
S9qiGOkxamS1Sg+jy2IWb/KBkkZgDXRkt02HecPJtV6kkA0fyLe281FiQU2/BHsb
+aPA2zavaNMY+UGSkPci2kMZ0lMuIWxTDmH1L1XnscLsowHGrPd9D04zdeZNEP74
mSnMrldlCt8xWD3xKV6Knh9AgPkXCB9MrsumrG9/RTpplnvEAPfic2YU7hRftKkn
BJZXNhX1pg4qqhcHT0O5
=/PuY
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20161008' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris:
"I've not been very active this cycle, so these are mostly from Boris,
for the NAND flash subsystem.
NAND:
- Add the infrastructure to automate NAND timings configuration
- Provide a generic DT property to maximize ECC strength
- Some refactoring in the core bad block table handling, to help with
improving some of the logic in error cases.
- Minor cleanups and fixes
MTD:
- Add APIs for handling page pairing; this is necessary for reliably
supporting MLC and TLC NAND flash, where paired-page disturbance
affects reliability. Upper layers (e.g., UBI) should make use of
these in the near future"
* tag 'for-linus-20161008' of git://git.infradead.org/linux-mtd: (35 commits)
mtd: nand: fix trivial spelling error
mtdpart: Propagate _get/put_device()
mtd: nand: Provide nand_cleanup() function to free NAND related resources
mtd: Kill the OF_MTD Kconfig option
mtd: nand: mxc: Test CONFIG_OF instead of CONFIG_OF_MTD
mtd: nand: Fix nand_command_lp() for 8bits opcodes
mtd: nand: sunxi: Support ECC maximization
mtd: nand: Support maximizing ECC when using software BCH
mtd: nand: Add an option to maximize the ECC strength
mtd: nand: mxc: Add timing setup for v2 controllers
mtd: nand: mxc: implement onfi get/set features
mtd: nand: sunxi: switch from manual to automated timing config
mtd: nand: automate NAND timings selection
mtd: nand: Expose data interface for ONFI mode 0
mtd: nand: Add function to convert ONFI mode to data_interface
mtd: nand: convert ONFI mode into data interface
mtd: nand: Introduce nand_data_interface
mtd: nand: Create a NAND reset function
mtd: nand: remove unnecessary 'extern' from function declarations
MAINTAINERS: Add maintainer entry for Ingenic JZ4780 NAND driver
...
Introduced by commit fde85cfd2d ("mtd: nand: Fix nand_command_lp() for
8bits opcodes") and I didn't have the heart to have Boris rewrite his
pull request just for that. Anyway, there's some value in having stable
commit hashes.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
- add the infrastructure to automate NAND timings configuration
- provide a generic DT property to maximize ECC strength
The rest is just a bunch of minor drivers and core fixes/cleanup
patches.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJX6BreAAoJEGXtNgF+CLcAR3sQAKi+nPui3AaMyI8ZtNOG0xRL
GscApY4RyGztDtTn+U46y9uRH5Dsgh4eM1SVlP4cyPHd8aB3X82weqivHGjX3m7c
BJVXEQts7UctjPJzVRwBWo/9VG+eDeXnzfZoCZV5FxhuFVY1LhM94HJMGf/z3XHB
oy6rWYvGFK7s9buY7UxP2dBf1Z4xuqqJEhGhP79fSmMjByaBtwjDk8mE9/9oIe6e
U1nw1BR9JPvNmtlxNK2FmePYZGzBt2H/5iuJuSWdOJgkyciGbfhidDFVwHLFZG6H
uguAVe56fSlNz2+S2eeH0b9MzV8oS4c/mG0u+duDkv0YQT9GfjXAdGIjHHEMNlXw
JF5G7PQDxCLb/ZZnZbgOFnwfVRq5ooIpm+G5AjmHxB+Xt00ch7ye2w2j9LbNmnTm
prUGawUu/r5xFh2MdwPlKM7KDcXQ4WFTgsEd6hGsiKhh5jJ+mfzC9IctXNXvZ3Kr
wrzaSu0li5n/qma9eQqCigxJ/bMyLiz0TL644/HJk0QCqGwoH5H1D8YQFXUtw+EM
PoTAh+F7cb9sEBlrhcmRIRYUWiUnFBZ2M870AzWPQWBv2dv+erq1u6sHo365Jxai
uJggBQy7arZ2/4lk8h1/Cn9iAJvzvmbeXEgza+Uhbgz7Q6UWioxjbbVXMlaGsR2y
HBp+RZbnBTht2F/On/CN
=mscR
-----END PGP SIGNATURE-----
Merge tag 'for-4.9' of github.com:linux-nand/linux
"
Notable core changes:
- add the infrastructure to automate NAND timings configuration
- provide a generic DT property to maximize ECC strength
The rest is just a bunch of minor drivers and core fixes/cleanup
patches.
"
Also not noted: some refactoring in the core bad block table handling,
to help with improving some of the logic in error cases.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Davinci NAND: fix a long-standing bug in how we clear/prep 4-bit ECC
OMAP NAND: an error-handling fix that made it into v4.8-rc1 caused
error-handling cases in other configurations/code-paths; this fixes the fix
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJX7Bv2AAoJEFySrpd9RFgtgn4P/0kmLaMl9/mnU8yV7o09uifR
pwDW1sd6TCG9htjsILkZ2s8gAHEeXqH/5aN0rRpIng4OFaVGyihCsBOAnV9YojXC
SlUEKLVqLNQxwp9rfCv4fe6amoBWEzw5BZRkSn5SPYP30JTyxCT1vZIYu+Nw22c2
H0YBRZKI8HnNapeScy9ccI+6Hvm9hUl33kFKuh/pNtHq16ocQvGeNNic8avW6ALr
hmmRBR0lmzBgRmJiykEe/xmjRjsFhB2Tb6GoxanTUOgcPIje5J4ly7YP8dfeXXIW
WDXG8wKaHrP5Igh0gLZlPTmjbdd6FAh/qQQkByPxhjMlu+OLZWwDzTw/F9ZvVmZa
ekcnH4UzYIKez4DFvZ2c0y5z4S64Qy2ajFJ28/3KNTATyBVtvUriGO2hafDUoGOu
6P0ZeAKr3iIHddFVFZaHb2lbNAhi+3JBv93LXOxMHyu4xroSIw1Sr2NdkBRs2t5J
+SRmdAjW612oVO7h6L2jEjAoWZMX2rn/ovNSp7AoQA+72BHTkOpGAv9KVI5cZezE
+08DhatIQdyP4Y0r5w6aMJLBiia33ofe+4hPiWlbZfyt0HkPuXYXDlxNXXyQKEcy
Vy2Jq0kB+hMMzYis+1lhasrvMBe67ykCKud8wSSE4L+kM8SMvibh9Hw4aCQVKKkb
fIpTwk2WzsRyMB+8+0d8
=coFg
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20160928' of git://git.infradead.org/linux-mtd
Pull late MTD fixes from Brian Norris:
"Another round of MTD fixes for v4.8
My apologies for sending this so late. I've been fairly absent as a
maintainer this cycle, but I did queue these up weeks ago. In the
meantime, Richard was able to handle some other fixes (thanks!) but
didn't pick these up.
On the bright side, these are very simple changes that should carry
little risk.
Summary:
- Davinci NAND: fix a long-standing bug in how we clear/prep 4-bit ECC
- OMAP NAND: an error-handling fix that made it into v4.8-rc1 caused
error-handling cases in other configurations/code-paths; this fixes
the fix"
* tag 'for-linus-20160928' of git://git.infradead.org/linux-mtd:
mtd: nand: davinci: Reinitialize the HW ECC engine in 4bit hwctl
mtd: nand: omap2: Don't call dma_release_channel() if dma_request_chan() failed
Provide a nand_cleanup() function to free all nand related resources
without unregistering the mtd device.
This should allow drivers to call mtd_device_unregister() and handle
its return value and still being able to cleanup all nand related
resources.
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Daniel Walter <dwalter@sigma-star.at>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
We are about to drop the OF_MTD Kconfig option. Test CONFIG_OF
activation instead of CONFIG_OF_MTD.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
8 bits opcodes should be followed by a single address cycle. Make the
2nd address cycle dependent of !nand_opcode_8bits(command).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Add support for ECC maximization when software BCH with
nand_ooblayout_lp_ops layout is used.
Other cases should be handled by the NAND controller driver.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The generic NAND DT bindings allows one to tweak the ECC strength and
step size to their need. It can be used to lower the ECC strength to
match a bootloader/firmware config, but might also be used to get a better
reliability.
In the latter case, the user might want to use the maximum ECC strength
without having to explicitly calculate the exact value (this value not
only depends on the OOB size, but also on the NAND controller, and can
be tricky to extract).
Add a generic 'nand-ecc-maximize' DT property and the associated
NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best
ECC strength and step-size on their own.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
So far we relied on reset default or the bootloader to configure a
suitable clk rate for the Nand controller. This works but we can
optimize the timing for better performance. This sets the clk rate for
v2 controllers (i.MX25/35) based on the timing mode read from the ONFI
parameter page. This may also enable the symmetric mode (aks EDO mode)
if necessary which reads one word per clock cycle.
Tested on an i.MX25 with a Micron MT29F4G08ABBDAHC attached.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
To be able to support different ONFI timing modes we have to implement
the onfi_set_features and onfi_get_features. Tested on an i.MX25 SoC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The NAND framework is now able to select the best NAND timings for us.
All we have to do is implement a ->setup_data_interface() function to
apply those timings and remove the timing selection code from the sunxi
driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The NAND framework provides several helpers to query timing modes supported
by a NAND chip, but this implies that all NAND controller drivers have
to implement the same timings selection dance. Also currently NAND
devices can be resetted at arbitrary places which also resets the timing
for ONFI chips to timing mode 0.
Provide a common logic to select the best timings based on ONFI or
->onfi_timing_mode_default information. Hook this into nand_reset()
to make sure the new timing is applied each time during a reset.
NAND controller willing to support timings adjustment should just
implement the ->setup_data_interface() method.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The nand layer will need ONFI mode 0 to use it as timing mode
before and right after reset.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
onfi_init_data_interface() initializes a data interface with
values from a given ONFI mode.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
struct nand_data_interface is the designated type to pass to
the NAND drivers to configure the timing. To simplify further
patches convert the onfi_sdr_timings array from type struct
nand_sdr_timings nand_data_interface.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
When NAND devices are resetted some initialization may have to be done,
like for example they have to be configured for the timing mode that
shall be used. To get a common place where this initialization can be
implemented create a nand_reset() function. This currently only issues
a NAND_CMD_RESET to the NAND device. The places issuing this command
manually are replaced with a call to nand_reset().
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Some Keystone devices (e.g. K2G) include a OMAP NAND IP.
Allow the NAND driver to be usable for both
Keystone and OMAP devices.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This patch adds big endian and ONFI support for various iProc based
SoCs that use the core brcmstb NAND controller
This patch was originally implemented by Prafulla Kota
<prafulla.kota@broadcom.com> and fully tested on iProc based NS2 SVK
Signed-off-by: Prafulla Kota <prafulla.kota@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Kamal Dasu <kdasu.kdev@gmail.com>
Acked-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
If erasing or writing the BBT fails, we should mark the current BBT
block as bad and use the BBT descriptor to scan for the next available
unused block in the BBT. We should only return a failure if there isn't
any space left.
Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com>
Suggested-by: Jeff Westfahl <jeff.westfahl@ni.com>
Tested-by: Kyle Roeschley <kyle.roeschley@ni.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This clarifies the write_bbt() function by removing the write label
and simplifying the error/exit path.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Kyle Roeschley <kyle.roeschley@ni.com>
In the ONFI spec, the tRR_min entry is defined before the tRST_max one.
Reoder the definition to make it easier to review.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
ONFI 4.0 spec defines different values for the tADL_min timing.
Since we don't want to have different timings depending on the ONFI
version, we just set tADL_min to the maximum value (the one specified
in the ONFI 4.0 spec).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
change the way to calculate pagesize to get correct free oob space for
legacy_set_geometry function.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Some build tools noticed that 'cookie' is being set but not used. Might
as well catch the errors here and handle them the same way we handle
other DMA prep steps.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The driver registered for CPU frequency transitions to recalculate its
clock when ARM clock frequency changes (ratio between frequencies of
ARM's parent clock (fclk) and clock for peripherals remains fixed).
This is needed only on S3C24xx platform when cpufreq driver is enabled
so limit the ifdef to respective cpufreq Kconfig.
Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Using "goto" and "switch" statement only makes it harder to follow
control flow and doesn't bring any advantages. Rewrite the code to avoid
using "goto".
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
If no user specified chip->select_chip() function is provided, code in
nand_base.c will automatically set this hook to nand_select_chip(),
which in turn depends on chip->cmd_ctrl() hook being valid. Not
providing both of those functions in NAND controller driver (for example
by mistake) will result in a bit cryptic segfault. Same is true for
chip->cmdfunc().
To avoid the above scenario add a check in nand_scan_dent and error out
if cmd_ctrl() is not provided.
Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Suggested-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Config MTD_NAND_FSL_IFC is already located inside 'if MTD_NAND'
statment, so there's no need to explicitly specify it as a dependency.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
MTD_NAND_FSL_ELBC selects FSL_LBC that in turn depends on FSL_SOC, so
depending on PPC instead of FSL_SOC leads to this message:
warning: (MPC836x_RDK && MTD_NAND_FSL_ELBC &&
MTD_NAND_FSL_UPM) selects FSL_LBC which has unmet direct
dependencies (FSL_SOC)
when doing
make ARCH=powerpc \
CROSS_COMPILE=powerpc-e500v2-linux-gnuspe- \
allmodconfig"
Changing dependency to FSL_SOC fixes that.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The code to initialize a struct nand_hw_control is duplicated across
several drivers. Factorize it using an inline function.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
commit a894cf6c5a ("mtd: nand: mxc: switch to mtd_ooblayout_ops")
introduced a regression accessing the OOB area from the mxc_nand
driver due to an Obiwan error in the mxc_nand_v[12]_ooblayout_free()
functions. They report a bogus oobregion { 64, 7 } which leads to
errors accessing bogus data when reading the oob area.
Prior to the commit the mtd-oobtest module could be run without any
errors. With the offending commit, this test fails with results like:
|Running mtd-oobtest
|
|=================================================
|mtd_oobtest: MTD device: 5
|mtd_oobtest: MTD device size 524288, eraseblock size 131072, page size 2048, count of eraseblocks 4, pages per eraseblock 64, OOB size 64
|mtd_test: scanning for bad eraseblocks
|mtd_test: scanned 4 eraseblocks, 0 are bad
|mtd_oobtest: test 1 of 5
|mtd_oobtest: writing OOBs of whole device
|mtd_oobtest: written up to eraseblock 0
|mtd_oobtest: written 4 eraseblocks
|mtd_oobtest: verifying all eraseblocks
|mtd_oobtest: error @addr[0x0:0x19] 0x9a -> 0x78 diff 0xe2
|mtd_oobtest: error @addr[0x0:0x1a] 0xcc -> 0x0 diff 0xcc
|mtd_oobtest: error @addr[0x0:0x1b] 0xe0 -> 0x85 diff 0x65
|mtd_oobtest: error @addr[0x0:0x1c] 0x60 -> 0x62 diff 0x2
|mtd_oobtest: error @addr[0x0:0x1d] 0x69 -> 0x45 diff 0x2c
|mtd_oobtest: error @addr[0x0:0x1e] 0xcd -> 0xa0 diff 0x6d
|mtd_oobtest: error @addr[0x0:0x1f] 0xf2 -> 0x60 diff 0x92
|mtd_oobtest: error: verify failed at 0x0
[...]
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Fixes: a894cf6c5a ("mtd: nand: mxc: switch to mtd_ooblayout_ops")
Cc: <stable@vger.kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
When mtk_nfc_do_write_page() comparing the sector number,because the
sector number field is at the 12th-bit position of NFI_BYTELEN
register,the masked register should be shifted 12 bits before being
compared.The result of this bug may cause the second subpage has
incomplete ECC parity bytes.
Signed-off-by: RogerCC Lin <rogercc.lin@mediatek.com>
Fixes: 1d6b1e4649 ("mtd: mediatek: driver for MTK Smart Device")
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
When mtk_ecc_encode() is writing the ECC parity data to the OOB
region,because each register is 4 bytes in length,but the len's unit is
in bytes,the operation in the for loop will cross the ECC's boundary.
Signed-off-by: RogerCC Lin <rogercc.lin@mediatek.com>
Fixes: 1d6b1e4649 ("mtd: mediatek: driver for MTK Smart Device")
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This fixes subpage writes when using 4-bit HW ECC.
There has been numerous reports about ECC errors with devices using this
driver for a while. Also the 4-bit ECC has been reported as broken with
subpages in [1] and with 16 bits NANDs in the driver and in mach* board
files both in mainline and in the vendor BSPs.
What I saw with 4-bit ECC on a 16bits NAND (on an LCDK) which got me to
try reinitializing the ECC engine:
- R/W on whole pages properly generates/checks RS code
- try writing the 1st subpage only of a blank page, the subpage is well
written and the RS code properly generated, re-reading the same page
the HW detects some ECC error, reading the same page again no ECC
error is detected
Note that the ECC engine is already reinitialized in the 1-bit case.
Tested on my LCDK with UBI+UBIFS using subpages.
This could potentially get rid of the issue workarounded in [1].
[1] 28c015a9da ("mtd: davinci-nand: disable subpage write for keystone-nand")
Fixes: 6a4123e581 ("mtd: nand: davinci_nand, 4-bit ECC for smallpage")
Cc: <stable@vger.kernel.org>
Signed-off-by: Karl Beldan <kbeldan@baylibre.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
dma_request_chan() can fail returning an error pointer. In this case
prevent calling dma_release_channel() to prevent a ERR_PTR() dereference.
As error path can be called even with no DMA configuration, info->dma can
be NULL so don't call dma_release_channel() for that case either.
Fixes: de3bfc4a16: ("mtd: nand: omap2: fix return value check in omap_nand_probe()")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
NAND:
Updates from Boris:
"""
This pull request contains only one notable change:
* Addition of the MTK NAND controller driver
And a bunch of specific NAND driver improvements/fixes. Here are the
changes that are worth mentioning:
* A few fixes/improvements for the xway NAND controller driver
* A few fixes for the sunxi NAND controller driver
* Support for DMA in the sunxi NAND driver
* Support for the sunxi NAND controller IP embedded in A23/A33 SoCs
* Addition for bitflips detection in erased pages to the brcmnand driver
* Support for new brcmnand IPs
* Update of the OMAP-GPMC binding to support DMA channel description
"""
In addition, some small fixes around error handling, etc., as well as one
long-standing corner case issue (2.6.20, I think?) with writing 1 byte less
than a page.
NOR:
* Rework some error handling on reads and writes, so we can better handle (for
instance) SPI controllers which have limitations on their maximum transfer size
* Add new Cadence Quad SPI flash controller driver
* Add new Atmel QSPI flash controller driver
* Add new Hisilicon SPI flash controller driver
* Support a few new flash, and update supported features on others
* Fix the logic used for detecting a fully-unlocked flash
And other miscellaneous small fixes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXn/j0AAoJEFySrpd9RFgto58P/j1huB0d21zFen3teo8YKKr1
dLi65mFbqtpU1BLqD07uc2gsH17kvezFJCtx8H8Jp/yCjLF2kYIKL7wDTf6OJPtn
aYGS5dG5jhMIq+6CD2olKqy+IVLfL9GvCf44Z3fpVta5lOn09y7Jm0AkBjmJcH45
SdJi+iUkSKhqRY3O2udyauGyL4JWG7eHUonrG9g8ROrO0GWQkT4Ijm1ZwIBlFDkJ
e1N960OqPg5ISOzuTeM14Ok9IUyeb7wiXhqRfOJgzNk6iBcN1YC2ono3C7RH2sN7
wiyCqqUpDDCDBDiFdGOdpc9cjzNysrt02ypWRsZIpQVCm89nPLSutqQEWLuo0qzq
/eIzdwbk1AxX96CeQohOezqL+n6+RHP9AIvwzL9GeWjipD1LBvfM1l3CmuSKK5jb
bQ4CA/FVz1tO/25q8tuLJfpFzhFE2PC3pphVf8tREL/U6OR/97NgDMuQIuqiQpRc
4nJtu79yacAzEiztZh0bsx+t94QFE+kfs/6d8m+llLEyx2sI8HKZeDvNRwEB0OsD
wQ5bjyd54m7+i4H8njrnOTP+K2YrwNjGlbTo7qrRSpFMDr4mD0VQLap03Srvo5xV
OYB6uGZhGV2L3k6nG5wywM2z6Hw0QfHxjrpcLyG51xABmni2QF3lOdYSllRtRTXp
aYLfPUqgIgSUI2GTDHyW
=HQr0
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20160801' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris:
"NAND:
Quoting Boris:
'This pull request contains only one notable change:
- Addition of the MTK NAND controller driver
And a bunch of specific NAND driver improvements/fixes. Here are the
changes that are worth mentioning:
- A few fixes/improvements for the xway NAND controller driver
- A few fixes for the sunxi NAND controller driver
- Support for DMA in the sunxi NAND driver
- Support for the sunxi NAND controller IP embedded in A23/A33 SoCs
- Addition for bitflips detection in erased pages to the brcmnand driver
- Support for new brcmnand IPs
- Update of the OMAP-GPMC binding to support DMA channel description'
In addition, some small fixes around error handling, etc., as well
as one long-standing corner case issue (2.6.20, I think?) with
writing 1 byte less than a page.
NOR:
- rework some error handling on reads and writes, so we can better
handle (for instance) SPI controllers which have limitations on
their maximum transfer size
- add new Cadence Quad SPI flash controller driver
- add new Atmel QSPI flash controller driver
- add new Hisilicon SPI flash controller driver
- support a few new flash, and update supported features on others
- fix the logic used for detecting a fully-unlocked flash
And other miscellaneous small fixes"
* tag 'for-linus-20160801' of git://git.infradead.org/linux-mtd: (60 commits)
mtd: spi-nor: don't build Cadence QuadSPI on non-ARM
mtd: mtk-nor: remove duplicated include from mtk-quadspi.c
mtd: nand: fix bug writing 1 byte less than page size
mtd: update description of MTD_BCM47XXSFLASH symbol
mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller
mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver
mtd: nand: brcmnand: Change BUG_ON in brcmnand_send_cmd
mtd: pmcmsp-flash: Allocating too much in init_msp_flash()
mtd: maps: sa1100-flash: potential NULL dereference
mtd: atmel-quadspi: add driver for Atmel QSPI controller
mtd: nand: omap2: fix return value check in omap_nand_probe()
Documentation: atmel-quadspi: add binding file for Atmel QSPI driver
mtd: spi-nor: add hisilicon spi-nor flash controller driver
mtd: spi-nor: support dual, quad, and WP for Gigadevice
mtd: spi-nor: Added support for n25q00a.
memory: Update dependency of IFC for Layerscape
mtd: nand: jz4780: Update MODULE_AUTHOR email address
mtd: nand: sunxi: prevent a small memory leak
mtd: nand: sunxi: add reset line support
mtd: nand: sunxi: update DT bindings
...
nand_do_write_ops() determines if it is writing a partial page with the
formula:
part_pagewr = (column || writelen < (mtd->writesize - 1))
When 'writelen' is exactly 1 byte less than the NAND page size the formula
equates to zero, so the code doesn't process it as a partial write,
although it should.
As a consequence the function remains in the while(1) loop with 'writelen'
becoming 0xffffffff and iterating endlessly.
The bug may not be easy to reproduce in Linux since user space tools
usually force the padding or round-up the write size to a page-size
multiple.
This was discovered in U-Boot where the issue can be reproduced by
writing any size that is 1 byte less than a page-size multiple.
For example, on a NAND with 2K page (0x800):
=> nand erase.part <partition>
=> nand write $loadaddr <partition> 7ff
[Editor's note: the bug was added in commit 29072b9607, but moved
around in commit 66507c7bc8 ("mtd: nand: Add support to use nand_base
poi databuf as bounce buffer")]
Fixes: 29072b9607 ("[MTD] NAND: add subpage write support")
Signed-off-by: Hector Palacios <hector.palacios@digi.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change the BUG_ON() condition in brcmnand_send_cmd() which checks for
the interrupt status "controller ready" bit to a WARN_ON.
There is no good reason to kill the system when this condition occur
because we could have systems which listed the NAND controller as
available (e.g: from Device Tree), but the NAND chip could be
malfunctioning and not responding.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In case of error, the function dma_request_chan() returns ERR_PTR() and
never returns NULL. The NULL test in the return value check should be
replaced with IS_ERR().
Fixes: aa7abd312c ('mtd: nand: omap2: Support parsing dma channel
information from DT')
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* Addition of the MTK NAND controller driver
And a bunch of specific NAND driver improvements/fixes. Here are the
changes that are worth mentioning:
* A few fixes/improvements for the xway NAND controller driver
* A few fixes for the sunxi NAND controller driver
* Support for DMA in the sunxi NAND driver
* Support for the sunxi NAND controller IP embedded in A23/A33 SoCs
* Addition for bitflips detection in erased pages to the brcmnand driver
* Support for new brcmnand IPs
* Update of the OMAP-GPMC binding to support DMA channel description
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXg0MnAAoJEGXtNgF+CLcABPcP/jSXHzYUk0vEPNLV6ToaZPgW
+Ct9oQEt6A96M/JOekAo5EyO04wD/CJncXao4ARy7tfvb7MG9bXA7FXsx2ihk22s
npmMV7zOSJisTpYKtX9gI4hJ8Jv8fusm+UIE78NiTJdhbQ/dQrReY7XAyUQin8lV
JIpWRfv2paQeBHn6MLj3MxvNCFxkQhHQOG6ohc2zCkfrQw2rKDWYLnhGLbbTHQV9
kxem+lf5FLk5TxN41NgnVcCfEnxawnNTmbs/i0tj6IqKwFR5fOO6Tcvyi/ZeL75c
3/78hxo3NMVuR9AUqbypbIJZayZiDNQCPpQUcgFbvrToRJoVA8u21+0C/IcKfzZc
mRYtMjU7+PzfbnKOo3IW/6Rbf2kc2q+6p0tMMbjPquWs8oPPRL8HMQu0h+PXXtyw
mz7qVGFjvUUA/vA9ebaUWwXYeHpQ2490wVOhvp523686IZv9kJhhxQWTqTYqCnZK
Ul2+UEYSpNH4ebnOeGbqyYVqee0+zokGMlEQZLyTjsm3rox13MCpOmhr1Qwl480y
fPIb2BLAsXdNqWSo6k7Bg/pTzDoq+i+w3vlKuQnKhOySEnPoV/D4MsAcwx4wkuiD
xxq/bu14vhnxF7Dbmjb3cylhQAz4xJomwixNjGfOg/+AyQQYh1iu0CY026N3F1VV
FmnnhJgQUi3PFGAupMOb
=8Aeb
-----END PGP SIGNATURE-----
Merge tag 'nand/for-4.8' of github.com:linux-nand/linux into mtd
Pull NAND changes from Boris Brezillon:
"""
This pull request contains only one notable change:
* Addition of the MTK NAND controller driver
And a bunch of specific NAND driver improvements/fixes. Here are the
changes that are worth mentioning:
* A few fixes/improvements for the xway NAND controller driver
* A few fixes for the sunxi NAND controller driver
* Support for DMA in the sunxi NAND driver
* Support for the sunxi NAND controller IP embedded in A23/A33 SoCs
* Addition for bitflips detection in erased pages to the brcmnand driver
* Support for new brcmnand IPs
* Update of the OMAP-GPMC binding to support DMA channel description
"""
commit c9711ec525 ("mtd: nand: omap: Clean up device tree support")
removes the check for the old elm phandle binding.
Add it again to keep backward compatibility.
Fixes: commit c9711ec525 ("mtd: nand: omap: Clean up device tree support")
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch enables IFC NAND support on ARM layerscape platform.
It fixes the dependency to enable NAND. The include files are being modified
to ensure complilation for both PowerPC and ARM architectures.
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Acked-by: Scott Wood <oss@buserror.net>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Emails will bounce from my imgtec address, so update it to a new one.
Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
Cc: Harvey Hunt <harveyhuntnexus@gmail.com>
Cc: linux-mtd@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
I moved the sanity check on ecc->size before the allocation so that we
don't leak memory on error.
Fixes: 05af074a4b73 ('mtd: nand: sunxi: check ecc->size values')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The NAND controller on some sun8i chips needs its reset line to be
deasserted before they can enter working state.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Instead of using IO_ADDR_W and IO_ADDR_R use an own pointer to the NAND
controller memory area.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This driver needs a special write_buf and read_buf function, because we
have to read from a specific address to tell the controller this is a
read from the nand controller.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Extract the functions to read and write to the register of the NAND
flash controller.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The external Bus Unit (EBU) can control different flash devices, but
these NAND flash commands have to be atomic and should not be
interrupted in between. Lock the EBU from the beginning of the command
till the end by moving the lock to the chip select.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
nand_scan() already resets the NAND flash chip, this driver does not
have to call it manually. The xway_reset_chip() functions does the same
as the normal NAND reset function. The waiting for the NAND_WAIT_WR_C
is done in xway_cmd_ctrl().
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The ->cmd_ctrl() function is adjusting the ->IO_ADDR_W value depending
on the command type each time NAND_CTRL_CHANGE is passed. This is not
only useless but can lead to an ->IO_ADDR_W corruption.
Get rid of this logic and rely on the NAND_CLE and NAND_ALE flags to
deduce the iomem address to write the cmd argument to.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Instead of hacking this into the plat_nand driver just make this a
normal nand driver.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This adds some register documentation which should make it easier to
understand how this controller works. In addition it makes now use of
BIT() macro and adds some more defines.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implement ecc->write_subpage() to prevent core code from assigning this
hook to nand_write_subpage_hwecc(). This default implementation tries
to call ecc->hwctl() which in our case is NULL, thus leading to a NULL
pointer dereference.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Verify that the ecc->size value is either 512 or 1024 bytes.
This should always be the case if this field was assigned to the
nand->ecc_step_size_ds value, but can be wrong when the user overloaded
this value with the nand-ecc-step-size DT property.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Switching to 1k ECC blocks when possible provides better resistance against
concentrated bitflips. Say you have those two configurations:
1/ 16bits/512bytes
2/ 32bits/1024bytes
Both of them require the same amount of ECC bytes (only true for this
specific engine), but the second config allows you to correct the case
where most of your bitflips are concentrated in a single 512bytes portion.
This fact makes the 1k ECC block size more advantageous than the 512bytes
one.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The column address passed to the RNDOUT operation was missing the page
size offset.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 614049a8d9 ("mtd: nand: sunxi: add support for DMA assisted operations")
Add support for mediatek's SDG1 NFC nand controller embedded in SoC
2701
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Xiaolei Li <xiaolei.li@mediatek.com>
In case of error, the function dmaengine_prep_slave_sg() returns NULL
pointer not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Fixes: 614049a8d9 ("mtd: nand: sunxi: add support for DMA assisted operations")
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This change provides a fix for controller bug where nand
controller could have a possible sticky error after a PIO
followed by a DMA read. The fix retries a read if we see
a uncorr_ecc after read to detect such sticky errors.
The fix applies to only controller version 7.0 and 7.1.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Check for erased page bitflips in a page. And if well within
threshold return data as all 0xff. Apply sw check for controller
version < 7.2. Controller vesion >= 7.2 has hw support.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
I got device with ESMT (Elite Semiconductor Memory Technology Inc)
F59L1G81MA flash that was detected as:
[ 0.852034] nand: device found, Manufacturer ID: 0xc8, Chip ID: 0xd1
[ 0.858402] nand: Unknown NAND 128MiB 3,3V 8-bit
[ 0.863031] nand: 128MiB, SLC, page size: 2048, OOB size: 64
According to the F59L1G81MA datasheet (and Read Id documentation) C8h is
a "Maker Code" which should mean ESMT. Add it to fix above "Unknown".
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The sunxi NAND controller is able to pipeline ECC operations only when
operated in DMA mode, which improves a lot NAND throughput while keeping
CPU usage low.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The 7.2 controller differs in a few area compared to its predecssor (7.1):
- NAND scrambler, which we are not using just yet
- higher ECC levels (up to 120 bits) per 1KB data blocks, also not supported yet
- up to 128B OOB
This patch adds the necessary code to support such a controller
generation and updates the Device Tree binding.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Kamal Dasu <kdasu.kdev@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Switch from dma_request_channel to allow passing dma channel
information from DT rather than hardcoding a value.
Also provide a handle to the GPMC's dev so it can be used to parse the DMA
channel information within the GPMC's DT node.
Performance Numbers via mtd_speedtest now that EDMA based prefetch works:
AM335x Performance numbers:
DMA
CPULOAD Write: 54% Read: 35%
page write speed -23% (vs non dma)
page read speed -35% (vs non dma)
NO DMA (prefetch-polled)
CPULOAD Write: 98% Read: 98%
AM437x Performance numbers:
DMA
CPU LOAD Write: 56% Read: 36%
page write speed -16% (vs non dma)
page read speed -22% (vs non dma)
NO DMA (prefetch-polled)
CPULOAD Write: 93% Read: 93%
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
We've already noticed a few flaws in the MTD work for v4.7-rc1:
* The Atmel folks got ahead of themselves on trying to support their latest
hardware and were working off incorrect documentation. Fix up the NAND
driver to get this correct.
* Fix up device tree example documentation to use the latest recommendations
for describing NAND ECC algorithms.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXSH51AAoJEFySrpd9RFgtSnsQAK+UrSM1gFAiMBEWPJuCK100
WZRZG8FxftzGbU33DiSgXDU/RmZBupIBHSZNGoWBkumdd9uozfIWp+s2T40k2ot6
E7ckF3lGaZOWMmzt/MN5lkeTm6Pzs63DemP/a1wSRqfvCTE8kB8EREzUiTQuNnWi
6YMvXuVnwouh5v91vuwKOKmGWuYidy6sF91w8ucd+W/A7p0Rnj8Nr7cGur3Xn+6L
MNjvfvD8tfyKk3b7aaNMyR6oIJQ9awR2TewBbB/6mJQR/eDOPnpq3Z+rJSwEoSJH
Hd/pG0zx9KeZyOF7kbZZmfk9DyPM50qCxiX/Z9kaSMGxyEQgwMjmQslJbDvRGOz5
2s5NAT8Nm3OcedAJgjGLmUlO/NH4XIQt+c35nftikeNplUqNNbZLjMgpfnLWB8FN
5cerUeFBwFZztJIWN1eQfZ7lERwk8bJPr0IRfPASj0xjTXi1DZze7WijA/BrsvEc
rUQ8J1YAXvjVyQZUmJyq8MFVeyEewv1MZ0O5w0t0u7kXtVI3HLQiJCLy1ZD3rDm2
dW4hMVtLOu6WDGZ27a229QtXOEm5L0YXCQGea75zR+gQObiY8mMIN3Qy68W4zSSJ
yGMPY9u8E8oPHh7TeNtc4E8MkYbujqknIshcgTBN2k4HufK6GPZOTvwfor1zdHAe
HGk9MiFRrACPTQIuxfhd
=kb+w
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20160527' of git://git.infradead.org/linux-mtd
Pull MTD fixes from Brian Norris:
"We've already noticed a few flaws in the MTD work for v4.7-rc1:
- The Atmel folks got ahead of themselves on trying to support their
latest hardware and were working off incorrect documentation. Fix
up the NAND driver to get this correct.
- Fix up device tree example documentation to use the latest
recommendations for describing NAND ECC algorithms"
* tag 'for-linus-20160527' of git://git.infradead.org/linux-mtd:
Documentation: dt: mtd: drop "soft_bch" from example
Revert "mtd: atmel_nand: Support variable RB_EDGE interrupts"
This reverts commit 5ddc7bd43c ("mtd: atmel_nand: Support variable
RB_EDGE interrupts")
Because for current SoCs, the RB_EDGE3(i.e. bit 27) of HSMC_SR
register does not exist, the RB_EDGE0 (i.e. bit 24) is the ready/busy
line edge status bit. It is a datasheet bug.
Cc: <stable@vger.kernel.org>
Fixes: commit 5ddc7bd43c ("mtd: atmel_nand: Support variable RB_EDGE interrupts")
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
First cycle with Boris as NAND maintainer! Many (most) bullets stolen from him.
Generic:
* Migrated NAND LED trigger to be a generic MTD trigger
NAND:
* Introduction of the "ECC algorithm" concept, to avoid overloading the ECC
mode field too much more
* Replaced the nand_ecclayout infrastructure with something a little more
flexible (finally!) and future proof
* Rework of the OMAP GPMC and NAND drivers; the TI folks pulled some of
this into their own tree as well
* Prepare the sunxi NAND driver to receive DMA support
* Handle bitflips in erased pages on GPMI revisions that do not support
this in hardware.
SPI NOR:
* Start using the spi_flash_read() API for SPI drivers that support it (i.e.,
SPI drivers with special memory-mapped flash modes)
And other small scattered improvments.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXQ9oUAAoJEFySrpd9RFgttf0P/3oIVCvLHSFIsi7XiUusWJWk
Cb+xW3ujFd2kNUqAQGnyvPUGU1amgjAjy2kwMpvpOG07DVgSnxQVGaQLins8Zwpw
auWxH8llISmC6UkNsS1jV0d7KzSMCT2Ne+BenRAn68kq3ovXPPB3B19B6dFj8ail
s83ajoZhsn1+eyctiKtbhXgZWkJHlRmBeXPKAJcS0lBcSibR+6N+O//JEAMnyYvc
7azuw0KMVwQNnNYFAfd9dilV5juZ9bZptTJYH7XuF+44FhxmSKvTX2a9gmp0C4Bm
FszUiPrIWF+t98nSQxxSn/zPlyllFyoisa6F7eGnDHIz+bH0Emf2oVwsSG5ASl42
XTml0kB0jCfuBfgAiyhYU2Uds7rSYs/ZcHr3iPgpUY3Sc3dgoArDdahMJXwqaoa8
UdChu6A+rjhi9PqhzNNVTarbilp3pOVgKAUVEWTdpQ1wGU4c+9SNlTTwhPy4g7RB
uKlqbMeiZ/5rPiihaMUNtzxMxSe9OGYW2HVNVExvmlF2Ca42M1xJJBMlAA6IIXyS
35d3Y4F5zPP7U6GCVla06WHkL5ahXJWmI0Xhf+2jCnDMipeAl6eCEiAJY5EmvAnr
FTpZ4qkspED69mO8oZW9ORje0n6PCm4XPOi4Vl8kci8tlBsEJMk9jaedWwGlZkRk
I5leUP4NEougvuHce2Cn
=J6KN
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20160523' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris:
"First cycle with Boris as NAND maintainer! Many (most) bullets stolen
from him.
Generic:
- Migrated NAND LED trigger to be a generic MTD trigger
NAND:
- Introduction of the "ECC algorithm" concept, to avoid overloading
the ECC mode field too much more
- Replaced the nand_ecclayout infrastructure with something a little
more flexible (finally!) and future proof
- Rework of the OMAP GPMC and NAND drivers; the TI folks pulled some
of this into their own tree as well
- Prepare the sunxi NAND driver to receive DMA support
- Handle bitflips in erased pages on GPMI revisions that do not
support this in hardware.
SPI NOR:
- Start using the spi_flash_read() API for SPI drivers that support
it (i.e., SPI drivers with special memory-mapped flash modes)
And other small scattered improvments"
* tag 'for-linus-20160523' of git://git.infradead.org/linux-mtd: (155 commits)
mtd: spi-nor: support GigaDevice gd25lq64c
mtd: nand_bch: fix spelling of "probably"
mtd: brcmnand: respect ECC algorithm set by NAND subsystem
gpmi-nand: Handle ECC Errors in erased pages
Documentation: devicetree: deprecate "soft_bch" nand-ecc-mode value
mtd: nand: add support for "nand-ecc-algo" DT property
mtd: mtd: drop NAND_ECC_SOFT_BCH enum value
mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping
mtd: nand: read ECC algorithm from the new field
mtd: nand: fsmc: validate ECC setup by checking algorithm directly
mtd: nand: set ECC algorithm to Hamming on fallback
staging: mt29f_spinand: set ECC algorithm explicitly
CRIS v32: nand: set ECC algorithm explicitly
mtd: nand: atmel: set ECC algorithm explicitly
mtd: nand: davinci: set ECC algorithm explicitly
mtd: nand: bf5xx: set ECC algorithm explicitly
mtd: nand: omap2: Fix high memory dma prefetch transfer
mtd: nand: omap2: Start dma request before enabling prefetch
mtd: nandsim: add __init attribute
mtd: nand: move of_get_nand_xxx() helpers into nand_base.c
...
Pull LED updates from Jacek Anaszewski:
"In this merge cycle we had an interaction with MTD subsystem, that
included converting drivers/mtd/nand/nand_base.c to use newly
introduced MTD (NAND/NOR) LED trigger instead of implementing it on
its own.
Related MTD patches are intended to be merged through the LED tree,
before MTD tree is merged, since further MTD development is based on
those modifications.
Summary:
LEDs:
- Introduce a kernel panic LED trigger
- Introduce a MTD (NAND/NOR) trigger
- led-tca6507: silence an uninitialized variable warning
- ledtrig-ide-disk: Move ide_blink_delay to ledtrig_ide_activity()
- leds-ss4200: Add depend on x86 arch
- leds-ss4200: add DMI data for FSC SCALEO Home Server
- leds-triggers: Allow to switch the trigger to "panic" on a kernel panic
- devicetree: leds: Introduce "panic-indicator" optional property
- leds-gpio: Support the "panic-indicator" firmware property
MTD:
- Uninline mtd_write_oob and move it to mtdcore.c
- Remove the "nand-disk" LED trigger
- Hook I/O activity to the MTD LED trigger"
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds:
leds: gpio: Support the "panic-indicator" firmware property
devicetree: leds: Introduce "panic-indicator" optional property
leds: triggers: Allow to switch the trigger to "panic" on a kernel panic
leds: ss4200: add DMI data for FSC SCALEO Home Server
leds: ss4200: Add depend on x86 arch
leds: ledtrig-ide-disk: Move ide_blink_delay to ledtrig_ide_activity()
leds: tca6507: silence an uninitialized variable warning
mtd: Hook I/O activity to the MTD LED trigger
mtd: nand: Remove the "nand-disk" LED trigger
leds: trigger: Introduce a MTD (NAND/NOR) trigger
mtd: Uninline mtd_write_oob and move it to mtdcore.c
leds: trigger: Introduce a kernel panic LED trigger
* introduction of the ECC algo concept to extend the ECC mode one
* replacement of the nand_ecclayout infrastructure by something more
future-proof.
* addition of an mtd-activity led trigger to replace the nand-activity
one
And a bunch of specific NAND driver improvements/fixes. Here are the
changes that are worth mentioning:
* rework of the OMAP GPMC and NAND drivers
* prepare the sunxi NAND driver to receive DMA support
* handle bitflips in erased pages on GPMI revisions that do not support
this in hardware.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXK8LCAAoJEGXtNgF+CLcAX/AP/A/pgi/MZU8+T8mCiq3xBu97
bLjdn+fSVn834YEjGoumD5bvTANisbDOy/K9MpcLT6e+jXdKZbgNNneoJLmCAVVW
0hraHaX3zU28G9SRe7VasKJSMglN8+7r/+PR6/NBH0pAHv7BYsxfREC7Jf7LMTIb
PNrywfIGd/NPhI0stgL0+rzT3Z3GVO9p2y/OLJ7AmExGQO7wVvyQW/WYpk/ncEwG
wSiWLMR7tfEdmrkvpvzo+B0ZuBENCWz/HAhKJ6mCZdTbVMdFPsufG2pTnUaXrxLg
gRdkdj09S5b5VcqufjtSSRopHX9H5FFAzNmMPgDgCTiPu1b3wwD0CyxNfevewhTi
AFRZrq5z8TUm3/6Sh0g2Pti3Nr7Tm1rodpR1oaTMrMT1avrerTstenfi+0XaWEce
LiBSivbQizUsmaNtVlEYD0wEQoLN4Kmqhe6sD/24n92PpFPIxYbwdti4ybwpY7N1
8QwWNe8UFryG+7eAUvw69Yr6eetr3tAsjq2vqq0wblNDLH9kACFVrpijAxCX8pYK
PB5RUDLmJlQy3Jyq4eUylr+v3cLgkQ2NWP49tgsIT4nsbYpi9BCum0pfeD2kAbQh
mIpy/vlL0D5bqtriTNJjM2IhaJ8vyRNPo9cOgqoMRyLZDgGAn/XvecMVziZ2L0HK
x0DZ/HX4Sec4RNRSvfQ5
=PYza
-----END PGP SIGNATURE-----
Merge tag 'nand/for-4.7' of github.com:linux-nand/linux
Updates from Boris Brezillon:
This pull request contains the following infrastructure changes:
* introduction of the ECC algo concept to extend the ECC mode one
* replacement of the nand_ecclayout infrastructure by something more
future-proof.
* addition of an mtd-activity led trigger to replace the nand-activity
one
And a bunch of specific NAND driver improvements/fixes. Here are the
changes that are worth mentioning:
* rework of the OMAP GPMC and NAND drivers
* prepare the sunxi NAND driver to receive DMA support
* handle bitflips in erased pages on GPMI revisions that do not support
this in hardware.
* tag 'nand/for-4.7' of github.com:linux-nand/linux: (152 commits)
mtd: brcmnand: respect ECC algorithm set by NAND subsystem
gpmi-nand: Handle ECC Errors in erased pages
Documentation: devicetree: deprecate "soft_bch" nand-ecc-mode value
mtd: nand: add support for "nand-ecc-algo" DT property
mtd: mtd: drop NAND_ECC_SOFT_BCH enum value
mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping
mtd: nand: read ECC algorithm from the new field
mtd: nand: fsmc: validate ECC setup by checking algorithm directly
mtd: nand: set ECC algorithm to Hamming on fallback
staging: mt29f_spinand: set ECC algorithm explicitly
CRIS v32: nand: set ECC algorithm explicitly
mtd: nand: atmel: set ECC algorithm explicitly
mtd: nand: davinci: set ECC algorithm explicitly
mtd: nand: bf5xx: set ECC algorithm explicitly
mtd: nand: omap2: Fix high memory dma prefetch transfer
mtd: nand: omap2: Start dma request before enabling prefetch
mtd: nandsim: add __init attribute
mtd: nand: move of_get_nand_xxx() helpers into nand_base.c
mtd: nand: sh_flctl: rely on generic DT parsing done in nand_scan_ident()
mtd: nand: mxc: rely on generic DT parsing done in nand_scan_ident()
...
This is more obvious than guessing based on ECC strength. It allows
using NAND on devices with BCH-1 (e.g. D-Link DIR-885L).
This maintains DT backward compatibility by defaulting to Hamming if a
1-bit ECC algorithm is specified without a corresponding algorithm
selection. i.e., to use BCH-1, you must specify:
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
nand-ecc-algo = "bch";
Also adds a check to ensure we haven't allowed someone to get by with SW
ECC. If we want to support SW ECC, we need to refactor some other pieces
of this driver.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
ECC is only calculated for written pages. As erased pages are not
actively written the ECC is always invalid. For this purpose the
Hardware BCH unit is able to check for erased pages and does not raise
an ECC error in this case. This behaviour can be influenced using the
BCH_MODE register which sets the number of allowed bitflips in an erased
page. Unfortunately the unit is not capable of fixing the bitflips in
memory.
To avoid complete software checks for erased pages, we can simply check
buffers with uncorrectable ECC errors because we know that any erased
page with errors is uncorrectable by the BCH unit.
This patch adds the generic nand_check_erased_ecc_chunk() to gpmi-nand
to correct erased pages. To have the valid data in the buffer before
using them, this patch moves the read_page_swap_end() call before the
ECC status checking for-loop.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
[Squashed patches by Stefan and Boris to check ECC area]
Tested-by: Stefan Christ <s.christ@phytec.de>
Acked-by: Han xu <han.xu@nxp.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
So far it was only possible to specify ECC algorithm using "soft" and
"soft_bch" values of nand-ecc-mode prop. There wasn't a way to specify
it for a hardware ECC mode.
Now that we have independent field in NAND subsystem for storing info
about ECC algorithm we may also add support for this new DT property.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This value should not be part of nand_ecc_modes_t as it specifies
algorithm not a mode. We successfully managed to introduce new "algo"
field which is respected now.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
There isn't any difference between handling NAND_ECC_SOFT and
NAND_ECC_SOFT_BCH now. What matters is the new field called "algo".
Please note we're keeping backward DT compatibility. We are still
treating "soft_bch" value as the one setting Hamming algorithm, it's
just handled in of_get_nand_ecc_algo now.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Now we have all drivers properly setting this new field we can start
using it. For a very short period of time we should support both values:
NAND_ECC_SOFT and NAND_ECC_SOFT_BCH treating them the same. It's because
of_get_nand_ecc_mode may still be setting NAND_ECC_SOFT_BCH.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
NAND core sets ECC algorithm in algo field now and it should be
preferred over the mode field. This also prepares driver for dropping
NAND_ECC_SOFT_BCH.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Based on DMA documentation and testing using high memory buffer when doing
dma transfers can lead to various issues including kernel panics.
To workaround this simply use cpu copy.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The prefetch engine sends a dma request once a FIFO threshold has
been met. No other requests are received until the previous request
is handled.
Starting a dma transfer (dma_async_issue_pending) results in any
previous event for the dma channel to be cleared. Therefore, starting
the prefetch engine before initiating the dma transfer may result in
the prefetch triggering a dma request but instead of it being handled
it can end up being cleared. This will result in a hang since the code
will continue to wait for the dma request to complete.
By initiating the dma request before enabling the prefetch engine this
race condition is avoided and no dma request are missed/cleared.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Add __init attribute on functions that are only called from other __init
functions and that are not inlined, at least with gcc version 4.8.4 on an
x86 machine with allyesconfig. Currently, the functions are put in the
.text.unlikely segment. Declaring them as __init will cause them to be
put in the .init.text and to disappear after initialization.
The result of objdump -x on the functions before the change is as follows:
000000000000059a l F .text.unlikely 0000000000000239 alloc_device
000000000000034e l F .text.unlikely 000000000000002e get_partition_name
00000000000007d3 l F .text.unlikely 00000000000005da init_nandsim
And after the change it is as follows:
0000000000000029 l F .init.text 0000000000000234 alloc_device
0000000000000000 l F .init.text 0000000000000029 get_partition_name
000000000000025d l F .init.text 00000000000005d5 init_nandsim
Done with the help of Coccinelle. The semantic patch checks for local
static non-init functions that are called from an __init function and are
not called from any other function.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Now that all drivers go through nand_set_flash_node() to parse the generic
NAND properties, we can move all of_get_nand_xxx() helpers in to
nand_base.c, make them static and remove of_mtd.c and of_mtd.h.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Han xu <han.xu@nxp.com>
Move constants to the right of binary operators.
Generated by: scripts/coccinelle/misc/compare_const_fl.cocci
CC: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Now that all NAND drivers have switched to mtd_ooblayout_ops, we can kill
the ecc->layout field.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Archit Taneja <architt@codeaurora.org>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Harvey Hunt <harvey.hunt@imgtec.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Han Xu <han.xu@nxp.com>
Tested-by: Han Xu <han.xu@nxp.com>
Now that mtd_ooblayout_ecc() returns the ECC byte position using the
OOB free method, we can get rid of the fsmc_nand_eccplace struct.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Replace the nand_ecclayout definition by the equivalent mtd_ooblayout_ops
definition.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Replace the default nand_ecclayout definitions for large and small page
devices with the equivalent mtd_ooblayout_ops.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Use the mtd_set_ecclayout() helper instead of directly assigning the
mtd->ecclayout field.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The mtd_ooblayout_xxx() helper functions have been added to avoid direct
accesses to ecclayout fields, and thus ease for future reworks.
Use these helpers in all places where the oobfree[] and eccpos[] arrays
where directly accessed.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Archit Taneja <architt@codeaurora.org>
The mtd_ooblayout_xxx() helper functions have been added to avoid direct
accesses to the ecclayout field, and thus ease for future reworks.
Use these helpers in all places where the oobfree[] and eccpos[] arrays
where directly accessed.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The mtd_ooblayout_xxx() helper functions have been added to avoid direct
accesses to the ecclayout field, and thus ease for future reworks.
Use these helpers in all places where the oobfree[] and eccpos[] arrays
where directly accessed.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The mtd_ooblayout_xxx() helper functions have been added to avoid direct
accesses to the ecclayout field, and thus ease for future reworks.
Use these helpers in all places where the oobfree[] and eccpos[] arrays
where directly accessed.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The mtd_ooblayout_xxx() helper functions have been added to avoid direct
accesses to the ecclayout field, and thus ease for future reworks.
Use these helpers in all places where the oobfree[] and eccpos[] arrays
where directly accessed.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The mtd_ooblayout_xxx() helper functions have been added to avoid direct
accesses to the ecclayout field, and thus ease for future reworks.
Use these helpers in all places where the oobfree[] and eccpos[] arrays
where directly accessed.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The mtd_ooblayout_xxx() helper functions have been added to avoid direct
accesses to the ecclayout field, and thus ease for future reworks.
Use these helpers in all places where the oobfree[] and eccpos[] arrays
where directly accessed.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Allow for NULL cur_offs values when the caller does not know where the
NAND page register pointer points to.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
sunxi_nfc_hw_ecc_read_chunk() always retrieves the ECC and protected free
bytes, no matter if the user really asked for it or not. This can take a
non negligible amount of time, especially on NAND chips exposing large OOB
areas (> 1KB). Make it optional.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
In order to support DMA operations in a clean way we need to extract some
of the logic coded in sunxi_nfc_hw_ecc_read/write_page() into their own
function.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Some NAND operations are so fast that it doesn't make any sense to use
interrupt based waits (the scheduling overhead is not worth it).
Rename sunxi_nfc_wait_int() into sunxi_nfc_wait_events() and add a
parameter to specify whether polling should be used or not.
Note that all sunxi_nfc_wait_int() are moved to the polling approach now,
but this should change as soon as we have more information about the
approximate time we are about to wait (can be extracted from the NAND
timings, and the type of operation).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
->dev_ready() is not supposed to wait for busy to ready solution (this is
the role of ->waitfunc()).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
When the NAND controller operates in DMA mode it can pipeline ECC
operations which improves the throughput.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
NFC_ECC_ERR_CNT() is not taking into account the case when the NAND chip
contains more than 4 ECC blocks (NANDs with 4kB+ pages).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
We don't need to manually toggle the CE line since the controller handles
it for us. Moreover, keeping the CE line low when interacting with a DDR
NAND can be problematic (data loss in some corner cases).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Try to pack address and command cycles into a single NAND controller
command to avoid polling the status register for each single change
on the NAND bus.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Being able to read subpages can greatly improve read performances if the
MTD user is only interested in a small section of a NAND page.
This is particularly true with large pages (>= 8k).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Allwinner's ECC engine is capable of protecting a few bytes of the OOB
area. Implement specific OOB functions to benefit from this capability.
Also, when in raw mode, the randomizer is disabled, which means you'll
only be able to retrieve randomized data, which is not really useful
for most applications.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Export the default read/write oob functions (for the standard and syndrome
scheme), so that drivers can use them for their raw implementation and
implement their own functions for the normal oob operation.
This is required if your ECC engine is capable of fixing some of the OOB
data. In this case you have to overload the ->read_oob() and ->write_oob(),
but if you don't specify the ->read/write_oob_raw() functions they are
assigned to the ->read/write_oob() implementation, which is not what you
want.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Adapt the NAND controller clk rate to the tWB, tADL, tWHR and tRHW
timings instead of returning an error when the maximum clk divisor is
not big enough to provide an appropriate timing.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The ONFI spec says that EDO should be enabled if the host drives tRC less
than 30ns, but the code just tests for the tRC_min value extracted from
the timings exposed by the NAND chip not the timings actually configured
in the NAND controller.
Fix that by first rounding down the requested clk_rate with
clk_round_rate() and then checking if tRC is actually smaller than 30ns.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Unlike what is specified in the Allwinner datasheets, the NAND clock rate
is not equal to 2/T but 1/T. Fix the clock rate selection accordingly.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
sunxi_nand_chip_set_timings() is extracting a pointer to the nfc from the
nand->controller field, but this field is initialized after
sunxi_nand_chip_set_timings() call.
Reorder the calls to avoid any problem.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Nicolas Ferre <nicolas.ferre@atmel.com>
It also contains some minor related changes:
1) Don't warn if kzalloc fails as it dumps stack on its own
2) Use %pR format for displaying whole resource to avoid invalid format
warning
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Tested-by: Franklin S Cooper Jr. <fcooper@ti.com>
Some drivers are including linux/of_mtd.h even if they don't use any of
the of_get_nand_xxx() helpers.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Harvey Hunt <harvey.hunt@imgtec.com>
If there is only one bit difference in the ECC, the function should
return 1.
The result of "diff0 & ~(1<<fls(diff0))" is equal to diff0, so the
function actually returns -1.
Signed-off-by: Zhaoxiu Zeng <zhaoxiu.zeng@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The new IFC controller version 2.0 has a different memory map page.
Upto IFC 1.4 PAGE size is 4 KB and from IFC2.0 PAGE size is 64KB.
This patch segregates the IFC global and runtime registers to appropriate
PAGE sizes.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Raghav Dogra <raghav@freescale.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Acked-by: Scott Wood <oss@buserror.net>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
There's no reason to BUG() when parameters are being
validated. Drivers can get things wrong, and it's much nicer
to just throw a noisy warn and fail gracefully, than calling
BUG() and throwing the whole system down the drain.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
fix the raw_buffer pointer double free issue found by coverify.
CID 18344 (#2 of 2): Double free (USE_AFTER_FREE)
3. double_free: Calling gpmi_alloc_dma_buffer frees pointer
this->raw_buffer which has already been freed
Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Document and match the brcm,brcmnand-v6.2 compatible string, the controller has
a register layout identical to the v6.0 version and supports prefetch. Update the
command shift logic to account for v6.2 controller which are the first ones to
use a shift of 0 (6.1 used a shift of 24).
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
bch->dev is already assigned to &pdev->dev in the probe function.
Remove the duplicate assignment done in jz4780_bch_get().
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Acked-by: Harvey Hunt <harvey.hunt@imgtec.com>
New atmel SoCs are able to fix bitflips in erased pages, but old ones
are still impacted by this problem. Use nand_check_erased_ecc_chunk() to
handle this case.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: Herve Codina <herve.CODINA@celad.com>
Reviewed-by: Herve Codina <herve.CODINA@celad.com>
Tested-by: Herve Codina <herve.CODINA@celad.com>
This follows recent work on switching to enum nand_ecc_algo and
deprecating NAND_ECC_SOFT_BCH.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Use recently added of_get_nand_ecc_algo for that.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Pull leds-trigger changes from Jacek Anaszewski.
Create a generic mtd led-trigger to replace the exisitng nand led-trigger
implementation.
* 'mtd-nand-trigger' of git://git.kernel.org/pub/scm/linux/kernel/git/j.anaszewski/linux-leds:
mtd: Hook I/O activity to the MTD LED trigger
mtd: nand: Remove the "nand-disk" LED trigger
leds: trigger: Introduce a MTD (NAND/NOR) trigger
mtd: Uninline mtd_write_oob and move it to mtdcore.c
leds: trigger: Introduce a kernel panic LED trigger
In the v4.4 cycle, we relaxed the requirement for assigning mtd->owner, but we
didn't remove this error case. It's hit only by drivers that are both:
(a) using nand_scan() directly and
(b) built as modules
We haven't seen explicit complaints about this (most use cases don't fit one or
both of the above), but we should definitely not be BUG()'ing here.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXEWZUAAoJEFySrpd9RFgtuaYQAIjfmoefoDJuIw3QQE5tLNMc
xTj07f+V/Nzhats69zvjx4LNFF6R339IBFNq7WK+q7l7VbW6/XSa8XaQkgpO+wMI
Sqzkty4YIxQGucITVvauv82JW0K421XVUBAzeNt+4oT72RvMnXhOPka1LQXf3Ezh
vGb7ZGea7ZYuu060OQAGxJlrlDA5x7yhsvs3hpOT9hjx0jXr0JZXmohvFRqSiXqz
Rx60rmhpl37WJg46OX/LYRAF34StF8btDZsQVdpY75T9QtxD3vWvvlMHfJ4cQXRI
L3qUIGGj03tD0/4nf6/p+WMjxgctDqROVxWzLHOvTa+xIFR7iU8yra09fTbylOGL
C3I0B6kW05YJrY3TegL8EhNbotciC9SeCtbeRwbndyO1Jox88xGHovwWFN5++3Q+
4ahiP57cV/py1L2BgeYdPmHES6T4GLH/4y2MaMZr4hfGVxHbKN1/JkLp9cNqCSzZ
MtnEevbHYq4eN1rYULQCzLRxawhYjeY77cMYip6Ynu24UWUJmfdaroJncfmmBOhP
7NvWjtxpsjonrCVOdb4aq9UPTc3PxlyR4kZyzg7+Vx4eOByK8hFkfjckehJ64DCs
ac+r5d2LmaLqAMIvQt4ApwwzRzj4ST6CEWBEyKrvwwF4B4nHhkbf9Pf4IrzGmaao
W4dws70o9WUwGIv0Rw3D
=wxaC
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20160415' of git://git.infradead.org/linux-mtd
Pull MTD fix from Brian Norris:
"One MTD fix for v4.6-rc4:
In the v4.4 cycle, we relaxed the requirement for assigning
mtd->owner, but we didn't remove this error case. It's hit only
by drivers that are both:
(a) using nand_scan() directly
and
(b) built as modules
We haven't seen explicit complaints about this (most use cases don't
fit one or both of the above), but we should definitely not be
BUG()'ing here"
* tag 'for-linus-20160415' of git://git.infradead.org/linux-mtd:
mtd: nand: Drop mtd.owner requirement in nand_scan
The GPMC WAIT pin status are now available over gpiolib.
Update the omap_dev_ready() function to use gpio instead of
directly accessing GPMC register space.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Copy all the platform data parameters to the driver's local data
structure 'omap_nand_info' and use it in the entire driver. This will
make it easer for device tree migration.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Instead of accessing the gpmc_status register directly start
using the gpmc_nand_ops->nand_writebuffer_empty() helper
to check write buffer empty status.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Deprecate nand register passing via platform data and use
gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
This commit removes the "nand-disk" LED trigger from the
NAND code.
A trigger with the same name is already available selecting
LEDS_TRIGGER_MTD. Note that "nand-disk" trigger is being
deprecated in favor of the "mtd" trigger.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
PAGE_CACHE_{SIZE,SHIFT,MASK,ALIGN} macros were introduced *long* time
ago with promise that one day it will be possible to implement page
cache with bigger chunks than PAGE_SIZE.
This promise never materialized. And unlikely will.
We have many places where PAGE_CACHE_SIZE assumed to be equal to
PAGE_SIZE. And it's constant source of confusion on whether
PAGE_CACHE_* or PAGE_* constant should be used in a particular case,
especially on the border between fs and mm.
Global switching to PAGE_CACHE_SIZE != PAGE_SIZE would cause to much
breakage to be doable.
Let's stop pretending that pages in page cache are special. They are
not.
The changes are pretty straight-forward:
- <foo> << (PAGE_CACHE_SHIFT - PAGE_SHIFT) -> <foo>;
- <foo> >> (PAGE_CACHE_SHIFT - PAGE_SHIFT) -> <foo>;
- PAGE_CACHE_{SIZE,SHIFT,MASK,ALIGN} -> PAGE_{SIZE,SHIFT,MASK,ALIGN};
- page_cache_get() -> get_page();
- page_cache_release() -> put_page();
This patch contains automated changes generated with coccinelle using
script below. For some reason, coccinelle doesn't patch header files.
I've called spatch for them manually.
The only adjustment after coccinelle is revert of changes to
PAGE_CAHCE_ALIGN definition: we are going to drop it later.
There are few places in the code where coccinelle didn't reach. I'll
fix them manually in a separate patch. Comments and documentation also
will be addressed with the separate patch.
virtual patch
@@
expression E;
@@
- E << (PAGE_CACHE_SHIFT - PAGE_SHIFT)
+ E
@@
expression E;
@@
- E >> (PAGE_CACHE_SHIFT - PAGE_SHIFT)
+ E
@@
@@
- PAGE_CACHE_SHIFT
+ PAGE_SHIFT
@@
@@
- PAGE_CACHE_SIZE
+ PAGE_SIZE
@@
@@
- PAGE_CACHE_MASK
+ PAGE_MASK
@@
expression E;
@@
- PAGE_CACHE_ALIGN(E)
+ PAGE_ALIGN(E)
@@
expression E;
@@
- page_cache_get(E)
+ get_page(E)
@@
expression E;
@@
- page_cache_release(E)
+ put_page(E)
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Acked-by: Michal Hocko <mhocko@suse.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Since commit 807f16d4db ("mtd: core: set some defaults
when dev.parent is set"), it's now legal for drivers
to call nand_scan and nand_scan_ident without setting
mtd.owner.
Drop the check and while at it remove the BUG() abuse.
Fixes: 807f16d4db ("mtd: core: set some defaults when dev.parent is set")
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Brian: editorial note - while commit 807f16d4db wasn't explicitly
broken, some follow-up commits in the v4.4 release broke a few
drivers, since they would hit this BUG() if they used nand_scan()
and were built as modules]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The 'getchip' parameter is gone as of commit 9f3e04297b ("mtd: nand:
don't select chip in nand_chip's block_bad op"), so kill the doc with
it.
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
MDM9x15 series.
It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
broader interface for external slow peripheral devices such as LCD and
NAND/NOR flash memory or SRAM like interfaces.
We add support for the NAND controller found within EBI2. For the SoCs
of our interest, we only use the NAND controller within EBI2. Therefore,
it's safe for us to assume that the NAND controller is a standalone block
within the SoC.
The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
and spare data. The controller contains an internal 512 byte page buffer
to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
for register read/write and data transfers. The controller performs page
reads and writes at a codeword/step level of 512 bytes. It can support up
to 2 external chips of different configurations.
The driver prepares register read and write configuration descriptors for
each codeword, followed by data descriptors to read or write data from the
controller's internal buffer. It uses a single ADM DMA channel that we get
via dmaengine API. The controller requires 2 ADM CRCIs for command and
data flow control. These are passed via DT.
The ecc layout used by the controller is syndrome like, but we can't use
the standard syndrome ecc ops because of several reasons. First, the amount
of data bytes covered by ecc isn't same in each step. Second, writing to
free oob space requires us writing to the entire step in which the oob
lies. This forces us to create our own ecc ops.
One more difference is how the controller accesses the bad block marker.
The controller ignores reading the marker when ECC is enabled. ECC needs
to be explicity disabled to read or write to the bad block marker. The
nand_bbt helpers library hence can't access BBMs for the controller.
For now, we skip the creation of BBT and populate chip->block_bad and
chip->block_markbad helpers instead.
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
One of the arguments passed to struct nand_chip's block_bad op is
'getchip', which, if true, is supposed to get and select the nand device,
and later unselect and release the device.
This op is intended to be replaceable by drivers. The drivers shouldn't
be responsible for selecting/unselecting chip. Like other ops, the chip
should already be selected before the block_bad op is called.
Remove the getchip argument from the block_bad op and
nand_block_checkbad. Move the chip selection to nand_block_isbad, since it
is the only caller to nand_block_checkbad which requires chip selection.
Modify nand_block_bad (the default function for the op) such that it
doesn't select the chip.
Remove the getchip argument from the bad_block funcs in cafe_nand,
diskonchip and docg4 drivers.
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
nand_bch_init() requires several arguments which could directly be deduced
from the mtd device. Get rid of those useless parameters.
nand_bch_init() is also requiring the caller to provide a proper eccbytes
value, while this value could be deduced from the ecc.size and
ecc.strength value. Fallback to eccbytes calculation when it is set to 0.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Currently, all MTD drivers/sublayers exposing an OOB area are
doing the same kind of test to extract the available OOB size
based on the mtd_info and mtd_oob_ops structures.
Move this common logic into an inline function and make use of it.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Suggested-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
ecclayout->oobavail is just redundant with the mtd->oobavail field.
Moreover, it prevents static const definition of ecc layouts since the
NAND framework is calculating this value based on the ecclayout->oobfree
field.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In commit b70af9bef4 ("mtd: nand: increase ready wait timeout and
report timeouts"), we increased the likelihood of scheduling during
nand_wait(). This makes us more likely to hit the time_before(...)
condition, since a lot of time may pass before we get scheduled again.
Now, the loop was already buggy, since we don't check if the NAND is
ready after exiting the loop; we simply print out a timeout warning. Fix
this by doing a final status check before printing a timeout message.
This isn't actually a critical bug, since the only effect is a false
warning print. But too many prints never hurt anyone, did they? :)
Side note: perhaps I'm not smart enough, but I'm not sure what the best
policy is for this kind of loop; do we busy loop (i.e., no
cond_resched()) to keep the lowest I/O latency (it's not great if the
resched is delaying Richard's system ~400ms)? Or do we allow
rescheduling, to play nice with the rest of the system (since some
operations can take quite a while)?
Reported-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Richard Weinberger <richard@nod.at>
Reviewed-by: Harvey Hunt <harvey.hunt@imgtec.com>
With this removal, we don't need to 'get' the second DMA resource
either, as it's also unused.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
When the driver is initialized in a pure device-tree platform, the
driver's probe fails allocating the dma channel :
[ 525.624435] pxa3xx-nand 43100000.nand: no resource defined for data DMA
[ 525.632088] pxa3xx-nand 43100000.nand: alloc nand resource failed
The reason is that the DMA IO resource is not acquired through platform
resources but by OF bindings.
Fix this by ensuring that DMA IO resources are only queried in the non
device-tree case.
Fixes: 8f5ba31aa5 ("mtd: nand: pxa3xx-nand: switch to dmaengine")
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
mtd->priv is no longer pointing to the struct nand_chip it is attached to.
Replace those accesses by mtd_to_nand() calls.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 4be4e03efc ("mtd: nand: sunxi: add randomizer support")
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The BRCMNAND controller revision 7.1 is almost 100% compatible with the
previous v6.0 register offset layout, except for the Correctable Error
Reporting Threshold registers. Fix this by adding another table with the
correct offsets for CORR_THRESHOLD and CORR_THRESHOLD_EXT.
Fixes: 27c5b17cd1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is needed to properly support the 8-bits ECC configuration
with 4KB pages.
When pages larger than 2 KB are used on platforms using the PXA3xx
NAND controller, the reading/programming operations need to be split
in chunks of 2 KBs or less because the controller FIFO is limited to
about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to
this requirement, the data layout on NAND is a bit strange, with ECC
interleaved with data, at the end of each chunk.
When a 4-bits ECC configuration is used with 4 KB pages, the physical
data layout on the NAND looks like this:
| 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC |
So the data chunks have an equal size, 2080 bytes for each chunk,
which the driver supports properly.
When a 8-bits ECC configuration is used with 4KB pages, the physical
data layout on the NAND looks like this:
| 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 64 spare | 30 ECC |
So, the spare area is stored in its own chunk, which has a different
size than the other chunks. Since OOB is not used by UBIFS, the initial
implementation of the driver has chosen to not support reading this
additional "spare" chunk of data.
Unfortunately, Marvell has chosen to store the BBT signature in the
OOB area. Therefore, if the driver doesn't read this spare area, Linux
has no way of finding the BBT. It thinks there is no BBT, and rewrites
one, which U-Boot does not recognize, causing compatibility problems
between the bootloader and the kernel in terms of NAND usage.
To fix this, this commit implements the support for reading a partial
last chunk. This support is currently only useful for the case of 8
bits ECC with 4 KB pages, but it will be useful in the future to
enable other configurations such as 12 bits and 16 bits ECC with 4 KB
pages, or 8 bits ECC with 8 KB pages, etc. All those configurations
have a "last" chunk that doesn't have the same size as the other
chunks.
In order to implement reading of the last chunk, this commit:
- Adds a number of new fields to the pxa3xx_nand_info to describe how
many full chunks and how many chunks we have, the size of full
chunks and partial chunks, both in terms of data area and spare
area.
- Fills in the step_chunk_size and step_spare_size variables to
describe how much data and spare should be read/written for the
current read/program step.
- Reworks the state machine to accommodate doing the additional read
or program step when a last partial chunk is used.
This commit has been tested on a Marvell Armada 398 DB board, with a
4KB page NAND, tested in both 4 bits ECC and 8 bits ECC
configurations. Robert Jarzmik has tested on some PXA platforms.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
As the SAMA5D2 controller supports the 32-bit ECC strength, accept it
as a valid setting when required by the device tree or the NAND
parameter page.
Then configure the controller to use this new setting.
For the binding:
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Tested-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Starting with the SAMA5D2, there is a new revision of the Atmel PMECC
controller that can correct 32 bits in each sector. This controller is
not 100% compatible with the previous revision that corrected a maximum
of 24 bits by sector, as some register addresses overlap.
Using information from the device tree, we can configure the driver to
work with both versions.
For the binding:
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The NFC controller used to accelerate the NAND transfers on SAMA5 chips
can use either RB_EDGE0 or RB_EDGE3 as its ready/busy interrupt bit.
Use the controller's compatible string to select the correct bit.
For the binding:
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Wenyou Yang <Wenyou.yang@atmel.com>
Tested-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add verbose debug for register accesses. This enables easier debugging
by following where and how hardware is stimulated, and how it answers.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Not every arch has io memory nor can this driver ever work
on UML/i386.
So, unbreak the build by fixing the dependencies.
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Not every arch has io memory.
So, unbreak the build by fixing the dependencies.
Signed-off-by: Richard Weinberger <richard@nod.at>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The NAND core layer is already taking care of ecclayout propagation. Remove
this useless assignment.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
According to the ECC layout description the actual ecc.size is 512 bytes
and not mtd->writesize.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This field is not set in any board file and can thus be dropped.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
->ecc_layout is not used by any board file. Kill this field to avoid any
confusion. New boards are encouraged to use the default ECC layout defined
in NAND core.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The s3c2410 is allowing board data to overload the default ECC layout
defined inside the driver, but this feature is not used by board
specific definitions.
Kill this field so that we can easily move to a model where ecclayout
are dynamically allocated by the NAND controller driver.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Remove the need for forward declaration and the risk for a null pointer
when accessing the private part of the compatible match table, by using
the newly introduced of_device_get_match_data function.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The error messages when the ECC controller is misconfigured through the
device tree are very precise. As a result they can (and will) get
obsolete when new revisions of the controller appear.
Simplify them before adding the support for the new revision.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
By default NAND driver will choose the highest ecc strength that oob
could contain, in this case, for some 8K+744 NAND flash, the ecc
strength will be up to 52bit, which beyonds the i.MX6QDL BCH capability
(40bit).
This patch allows the NAND driver try to use minimum required ecc
strength if it failed to use the highest ecc, even without explicitly
claiming "fsl,use-minimum-ecc" in dts.
Signed-off-by: Han Xu <b45815@freescale.com>
Acked-by: Huang Shijie <shijie.huang@arm.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
i.MX6SX supports deep sleep mode(DSM) that may turn off GPMI/BCH power
during suspend, add gpmi nand suspend/resume function to release DMA
channel in suspend function and re-init GPMI/BCH controller during
resume function.
Although it is not necessary to restore GPMI/BCH registers value for
i.MX6QDL, the code doesn't distinguish different platforms to keep the
code simple.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Han Xu <han.xu@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Since commit 17799359e7 ("mtd: nand_bbt:
make nand_scan_bbt() static"), the nand_scan_bbt() function is marked
as static but is still exported using EXPORT_SYMBOL(), which doesn't
make much sense.
This commit gets rid of the useless EXPORT_SYMBOL.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Suggested-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
When using multi-bit ECC, it is normal for the NAND Flash driver to
correct bit errors during the life of the product. Those errors will
only be cleared once a threshold has been reached, and corrections can
occur regularly before this.
Use only dev_dbg and not dev_info to report the bitflips, to keep the
system log clean when everything works correctly.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Acked-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add support for the randomizer engine available in Allwinner's NFC IP.
Randomization is useful to support modern NAND chips which are sensitive to
repeated patterns. On such NANDs you might experience an unexpectedly high
number of bitflips when you repeat the same pattern all over a given NAND
block.
Randomizing input data mitigate this problem by avoiding such repeated
patterns.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The H27UCG8T2ATR-BC requires an external data scrambler. Reflect this
constraint in the nand_flash_ids definition.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The current code is the same as 'of_machine_is_compatible'.
So use it in order to remove a few lines of code and to be more
consistent with other parts of the kernel.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The nuc900_nand driver has always passed an incorrect register
address in its nuc900_check_rb() function, which cannot possibly
work, and in some configurations gives us a build warning:
drivers/mtd/nand/nuc900_nand.c: In function 'nuc900_check_rb':
drivers/mtd/nand/nuc900_nand.c:27:23: warning: passing argument 1 of '__raw_readl' makes pointer from integer without a cast [-Wint-conversion]
#define REG_SMISR 0xac
drivers/mtd/nand/nuc900_nand.c:118:20: note: in expansion of macro 'REG_SMISR'
val = __raw_readl(REG_SMISR);
This makes sure we actually read from the register rather than
from (void *)0x000000ac in user space.
I suspect nobody noticed this before because the nuc900_nand_devready()
function never gets called, or nobody uses this driver on an upstream
kernel. Possibly even both.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Using switch/case helps make this logic more clear and more robust. With
this structure:
* it's clear that this driver only support ECC_{HW,SOFT,SOFT_BCH}; and
* we can sanely handle new ECC unsupported modes (right now, this code
makes incorrect assumptions about the possible values in the
nand_ecc_modes_t enum; e.g., what happens with NAND_ECC_HW_OOB_FIRST?)
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Alex Smith <alex@alex-smith.me.uk>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Harvey Hunt <harvey.hunt@imgtec.com>
Acked-by: Harvey Hunt <harvey.hunt@imgtec.com>
Update jz4780_bch_ecc_correct's return codes with appropriate values,
as specified in /include/linux/mtd/nand.h.
Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
Cc: Alex Smith <alex@alex-smith.me.uk>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Commit d699ed250c ("mtd: nand: make use of
nand_set/get_controller_data() helpers") overlooked some uses of
nand_chip::priv.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
As of commit 2d3b77bac3 ("mtd: nand: update mtd_to_nand()"), this
assignment isn't necessary, since struct mtd_info is embedded in struct
nand_chip.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Harvey Hunt <harvey.hunt@imgtec.com>
Cc: Alex Smith <alex@alex-smith.me.uk>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
New helpers have been added to avoid directly accessing chip->field. Use
them where appropriate.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Brian: fixed a few rebase conflicts]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as
well as the hardware BCH controller. DMA is not currently implemented.
While older 47xx SoCs also have a BCH controller, they are incompatible
with the one in the 4780 due to differing register/bit positions, which
would make implementing a common driver for them quite messy.
Signed-off-by: Alex Smith <alex.smith@imgtec.com>
Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: linux-mtd@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Brian: fixed a few small mistakes]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The jz4740 driver is manually checking for 'erased pages' while
correcting ECC bytes.
This logic can now done by the core infrastructure, and can thus be removed
from this driver.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The diskonchip driver is manually checking for 'erased pages' while
correcting ECC bytes.
This logic can now done by the core infrastructure, and can thus be removed
from this driver.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The davinci driver is manually checking for 'erased pages' while
correcting ECC bytes.
This logic can now done by the core infrastructure, and can thus be removed
from this driver.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Franklin S Cooper Jr. <fcooper@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The default NAND read functions are relying on the underlying controller
driver to correct bitflips, but some of those controllers cannot properly
fix bitflips in erased pages.
Check for bitflips in erased pages in default core functions if the driver
delegated the this check by setting the NAND_ECC_GENERIC_ERASED_CHECK flag.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Franklin S Cooper Jr. <fcooper@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The error code returned by the ecc.correct() are not consistent over the
all implementations.
Document the expected behavior in include/linux/mtd/nand.h and fix
offending implementations.
[Brian: this looks like a bugfix for the ECC reporting in the bf5xx_nand
driver, but we haven't seen any testing results for it]
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Franklin S Cooper Jr. <fcooper@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Commits such as commit 853f1c58c4 ("mtd: nand: omap2: show parent
device structure in sysfs") attempt to rely on the core MTD code to set
the MTD name based on the parent device. However, nand_base tries to set
a different default name according to the flash name (e.g., extracted
from the ONFI parameter page), which means NAND drivers will never make
use of the MTD defaults. This is not the intention of commit
853f1c58c4.
This results in problems when trying to use the cmdline partition
parser, since the MTD name is different than expected. Let's fix this by
providing a default NAND name, where possible.
Note that this is not really a great default name in the long run, since
this means that if there are multiple MTDs attached to the same
controller device, they will have the same name. But that is an existing
issue and requires future work on a better controller vs. flash chip
abstraction to fix properly.
Fixes: 853f1c58c4 ("mtd: nand: omap2: show parent device structure in sysfs")
Reported-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Heiko Schocher <hs@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Frans Klaver <fransklaver@gmail.com>
Cc: <stable@vger.kernel.org>
From Stephen:
Hi Brian,
After merging the l2-mtd tree, today's linux-next build (powerpc
ppc44x_defconfig) failed like this:
drivers/mtd/nand/ndfc.c: In function 'ndfc_chip_init':
drivers/mtd/nand/ndfc.c:177:2: error: 'ppdata' undeclared (first use in this function)
ppdata.of_node = flash_np;
^
Caused by commit
a61ae81a19 ("mtd: nand: drop unnecessary partition parser data")
The flash node is already correctly assigned using the new helper
(nand_set_flash_node()) so the correct fix is indeed to simply drop this
line.
Fixes: a61ae81a19 ("mtd: nand: drop unnecessary partition parser data")
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
By convention, the FIFO address we pass using dmaengine_slave_config
is a physical address in the form that is understood by the DMA
engine, as a dma_addr_t, phys_addr_t or resource_size_t.
The sh_flctl driver however passes a virtual __iomem address that
gets cast to dma_addr_t in the slave driver. This happens to work
on shmobile because that platform sets up an identity mapping for
its MMIO regions, but such code is not portable to other platforms,
and prevents us from ever changing the platform mapping or reusing
the driver on other architectures like ARM64 that might not have the
mapping.
We also get a warning about a type mismatch for the case that
dma_addr_t is wider than a pointer, i.e. when CONFIG_LPAE is set:
drivers/mtd/nand/sh_flctl.c: In function 'flctl_setup_dma':
drivers/mtd/nand/sh_flctl.c:163:17: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
cfg.dst_addr = (dma_addr_t)FLDTFIFO(flctl);
This changes the driver to instead pass the physical address of
the FIFO that is extracted from the MMIO resource, making the
code more portable and avoiding the warning.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The build passes even if CONFIG_OF is undefined, but it makes sense
to let it depend on OF.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Nobody uses the get_platform_nandchip() helper function which is supposed
to return a pointer to a platform_nand_chip struct from an mtd_info
pointer.
Moreover, this function is buggy since the introduction of the plat_nand
layer (chip->priv is now storing a pointer to an intermediate
plat_nand_data structure allocated in plat_nand_probe(), and we have no
way to retrieve a pointer to the provided platform_nand_chip struct from
this plat_nand_data pointer).
While we are at it, remove the useless (and buggy, since it's pointing to
something stored on the stack) data->chip.priv assignment.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 711fdf627c ("[MTD] [NAND] platform NAND driver: add driver")
Cc: Vitaly Wool <vitalywool@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Now that the nand_chip struct directly embeds an mtd_info struct we can
get rid of the ->flash_node field and forward set/get_flash_node requests
to the MTD layer.
As a side effect, we no longer need the mtd_set_of_node() call done in
nand_dt_init().
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
nand_dt_init() function requires 3 arguments where it actually needs one
(dn and mtd can both be retrieved from chip). Drop these parameters.
Testing for dn != NULL inside nand_dt_init() also helps simplifying the
caller code.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
mtd_to_nand() now uses the container_of() approach to transform an
mtd_info pointer into a nand_chip one. Drop useless mtd->priv
assignments from NAND controller drivers.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Other refactorings have left the 'fail' label much simpler, so it
shouldn't have to handle the failed allocation case.
This also fixes a -Wshadow warning.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Brian: dropped a defunct comment]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
struct nand_chip now embeds an mtd device. Make use of this mtd instance
instead of allocating our own.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Define and use mtd_to_omap() instead of container_of();
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Create and use mtd_to_nuc900() instead of direct container_of() calls.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Create and use mtd_to_fsmc() to avoid duplication of
container_of(mtd, struct fsmc_nand_data, mtd) calls.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
When CONFIG_LPAE is set on ARM, resource_size_t is 64-bit wide
and we get a warning about an incorrect format string for printing
the interrupt number in elm_probe:
drivers/mtd/nand/omap_elm.c: In function 'elm_probe':
drivers/mtd/nand/omap_elm.c:417:23: warning: format '%i' expects argument of type 'int', but argument 3 has type 'resource_size_t {aka long long unsigned int}' [-Wformat=]
This patch avoids the type mismatch by printing the interrupt as
a resource using the %pr format string.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The field bcma_nflash::mtd is never set to be non-zero anywhere, but we
test for it in the removal path. So the MTD is never unregistered.
Also, we should use nand_release(), not mtd_device_unregister().
Finally, we don't need to use the 'platdata' for stashing/retrieving our
*driver* data -- that's what *_{get,set}_drvdata() are for.
So, kill off bcm_nflash::mtd, and stash the struct bcm47xxnflash in
drvdata instead. Also move the forward declaration of mtd_info up a bit,
since struct bcma_sflash should be using it.
Caught while inspecting other changes being made to this driver. Compile
tested only.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: "Rafał Miłecki" <zajec5@gmail.com>
Cc: linux-wireless@vger.kernel.org
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Unregister the NAND device from the NAND subsystem when removing a denali
NAND controller, otherwise the MTD attached to the NAND device is still
exposed by the MTD layer, and accesses to this device will likely crash
the system.
Fixes: 2a0a288ec2 ("mtd: denali: split the generic driver and PCI layer")
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
devm_ioremap_resource() does error checking on the 'res' argument, so
drop the error check in bcm6368_nand.c.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Simon Arlott <simon@fire.lp0.eu>
The BCM6368 has a NAND interrupt register with combined status and enable
registers.
As the BCM6328, BCM6362 and BCM6368 all use v2.1 controllers, the first
variant that will work with this driver is the BCM63268 using a v4.0
controller.
Set up the device by disabling and acking all interrupts, then handle
the CTRL_READY interrupt.
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Attempt to enable a clock named "nand" as some SoCs have a clock for the
controller that needs to be enabled.
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
As of commit a521422ea4 ("ARM: shmobile: mackerel: Remove Legacy C
board code"), the Renesas SuperH FLCTL driver is no longer used on ARM
SH-Mobile SoCs. Restrict the dependencies, unless compile-testing.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
mtd_to_nand() was recently introduced to avoid direct accesses to the
mtd->priv field. Update all NAND drivers to use it.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
mtd_to_nand() was recently introduced to avoid direct access to the
mtd->priv field. Update core code to use mtd_to_nand().
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Calling synchronize_irq() right before free_irq() is quite useless. On one
hand the IRQ can easily fire again before free_irq() is entered, on the
other hand free_irq() itself calls synchronize_irq() internally (in a race
condition free way), before any state associated with the IRQ is freed.
Patch was generated using the following semantic patch:
// <smpl>
@@
expression irq;
@@
-synchronize_irq(irq);
free_irq(irq, ...);
// </smpl>
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We don't actually need to stash a copy of this device_node indefinitely;
we only need it in brcmnand_init_cs().
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: <bcm-kernel-feedback-list@broadcom.com>
Cc: Kamal Dasu <kdasu.kdev@gmail.com>
Acked-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
for_each_child_of_node performs an of_node_get on each iteration, so
a break out of the loop requires an of_node_put.
A simplified version of the semantic patch that fixes this problem is as
follows (http://coccinelle.lip6.fr):
// <smpl>
@@
expression root,e;
local idexpression child;
@@
for_each_child_of_node(root, child) {
... when != of_node_put(child)
when != e = child
(
return child;
|
+ of_node_put(child);
? return ...;
)
...
}
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch addresses two related memory management issues in the probe
function:
1. for_each_available_child_of_node performs an of_node_get on each
iteration, so a break out of the loop requires an of_node_put.
A simplified version of the semantic patch that fixes this problem is as
follows (http://coccinelle.lip6.fr):
// <smpl>
@@
expression root,e;
local idexpression child;
@@
for_each_available_child_of_node(root, child) {
... when != of_node_put(child)
when != e = child
(
return child;
|
+ of_node_put(child);
? return ...;
)
...
}
// </smpl>
2. The devm_kzalloc'd data is not used if brcmnand_init_cs fails. Free it
immediately, using devm_kfree in this case, instead of waiting for the
remove function.
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
If an error occurs in flash above 4GB in PIO mode then the EXT_ADDR
registers will be set to the location of the error and never cleared.
Reset them to 0 before reading.
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
All atmel_nand_caps are never modified, consitify them.
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The ->priv field of the mtd_info object attached to a nand_chip device
should point to the nand_chip device. The pxa and cafe drivers are
assigning this field their own private structure, which works fine as long
as the nand_chip field is the first one in the driver private struct but
seems a bit fragile.
Fix that by setting mtd->priv to point the nand_chip field and assigning
chip->priv to the private structure head.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
AFAIR this driver was never tested with subpage read support, and this
code is currently unused because we don't set the NAND_SUBPAGE_READ
flag. It can be resurrected if someone tests it properly.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Ray Jui <rjui@broadcom.com>
The read_byte() handling for accessing the flash cache has some awkward
swapping being done in the read_byte() function. Let's just make this a
byte array, and do the swapping with the word-level macros during the
initial buffer copy.
This is just a refactoring patch, with no (intended) functional change.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Clay McClure <clay@daemons.net>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: <bcm-kernel-feedback-list@broadcom.com>
Tested-by: Clay McClure <clay@daemons.net>
Doing a bit-or operation with zero is pointless.
Remove this unneeded bit-or.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The NAND clock can be disabled on suspend and enabled on resume.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This macro is not used anymore, so it's just dead code.
Remove it.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Currently, the driver is trying to detect the presence of a chip
by issuing a RESET command before nand_scan_ident. This seems completely
redundant, and is also a layering violation as nand_scan_ident is in charge
of device detection.
This commit removes the RESET command use, and moves the initial
timing configuration to pxa3xx_nand_config_ident.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit simplifies the initial configuration performed
by pxa3xx_nand_scan. No functionality change is intended.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The Data Flash Control Register (NDCR) contains two types
of parameters: those that are needed for device identification,
and those that can only be set after device identification.
Therefore, the driver can't set them all at once and instead
needs to configure the first group before nand_scan_ident()
and the second group later.
Let's split pxa3xx_nand_config in two halves, and set the
parameters that depend on the device geometry once this is known.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The chunk size represents the size of the data chunks, which
is used by the controllers that allow to split transfered data.
However, the initial chunk size is used in a non-splitted way,
during device identification. Therefore, it must be large enough
for all the NAND commands issued during device identification.
This includes NAND_CMD_PARAM which was recently changed to
transfer up to 2048 bytes (for the redundant parameter pages).
Thus, the initial chunk size should be 2048 as well.
On Armada 370/XP platforms (NFCv2) booted without the keep-config
devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM
command:
[..]
pxa3xx-nand f10d0000.nand: This platform can't do DMA on this device
pxa3xx-nand f10d0000.nand: Wait time out!!!
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38
nand: Micron MT29F8G08ABABAWP
nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
If multiple NAND chips are registered to the same controller, then when
rebooting the system, the first one will grab the controller lock, while
the second will wait forever for the first one to release it. i.e., a
classic deadlock.
This problem was solved for a similar case (suspend/resume) back in
commit 6b0d9a8412 ("mtd: nand: fix multi-chip suspend problem"), and
the shutdown state really isn't much different for us, so rather than
adding a new special case to nand_get_device(), we can just overload the
FL_PM_SUSPENDED state.
Now, multiple chips can "get" the same controller lock (preventing
further I/O), while we still allow other chips to pass through
nand_shutdown().
Original report:
http://thread.gmane.org/gmane.linux.drivers.mtd/59726http://lists.infradead.org/pipermail/linux-mtd/2015-July/059992.html
Fixes: 72ea403669 ("mtd: nand: added nand_shutdown")
Reported-by: Andrew E. Mileski <andrewm@isoar.ca>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: Andrew E. Mileski <andrewm@isoar.ca>
Acked-by: Scott Branden <sbranden@broadcom.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fallout from commit 832f5dacfa ("MIPS: Remove all the uses of custom gpio.h")
We see errors like this:
drivers/mtd/nand/jz4740_nand.c: In function 'jz_nand_detect_bank':
drivers/mtd/nand/jz4740_nand.c:340:9: error: 'JZ_GPIO_MEM_CS0' undeclared (first use in this function)
drivers/mtd/nand/jz4740_nand.c:340:9: note: each undeclared identifier is reported only once for each function it appears in
drivers/mtd/nand/jz4740_nand.c:359:2: error: implicit declaration of function 'jz_gpio_set_function' [-Werror=implicit-function-declaration]
drivers/mtd/nand/jz4740_nand.c:359:29: error: 'JZ_GPIO_FUNC_MEM_CS0' undeclared (first use in this function)
drivers/mtd/nand/jz4740_nand.c:399:29: error: 'JZ_GPIO_FUNC_NONE' undeclared (first use in this function)
drivers/mtd/nand/jz4740_nand.c: In function 'jz_nand_probe':
drivers/mtd/nand/jz4740_nand.c:528:13: error: 'JZ_GPIO_MEM_CS0' undeclared (first use in this function)
drivers/mtd/nand/jz4740_nand.c: In function 'jz_nand_remove':
drivers/mtd/nand/jz4740_nand.c:555:14: error: 'JZ_GPIO_MEM_CS0' undeclared (first use in this function)
Patched similarly to:
https://patchwork.linux-mips.org/patch/11089/
Fixes: 832f5dacfa ("MIPS: Remove all the uses of custom gpio.h")
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
All of these drivers set up a parser data struct just to communicate DT
partition data. This field has been deprecated and is instead supported
by telling nand_scan_ident() about the 'flash_node'.
This patch:
* sets chip->flash_node for those drivers that didn't already (but used
OF partitioning)
* drops the parser data
* switches to the simpler mtd_device_register() where possible, now
that we've eliminated one of the auxiliary parameters
Now that we've assigned chip->flash_node for these drivers, we can
probably rely on nand_dt_init() to do more of the DT parsing for us, but
for now, I don't want to fiddle with each of these drivers. The parsing
is done in duplicate for now on some drivers. I don't think this should
break things. (Famous last words.)
(Rolled in some changes by Boris Brezillon)
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
We should pass along our flash DT node to the MTD layer, so it can set
up ofpart for us.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
The in-band data are copied twice: before ECC correction and after the
ECC engine has fixed all the fixable bitflips.
Drop the useless memcpy_fromio operation by passing a NULL pointer when
calling sunxi_nfc_read_buf().
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The sunxi_nfc_hw_ecc_read/write_chunk() functions try to avoid changing
the column address if unnecessary, but the logic to determine whether it's
necessary or not is currently wrong: it adds the ecc->bytes value to the
current offset where it should actually add ecc->size.
Fixes: 913821bdd2 ("mtd: nand: sunxi: introduce sunxi_nfc_hw_ecc_read/write_chunk()")
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Just like other NAND controllers, the NAND READID command only works
in 8bit mode for all versions of BRCMNAND controller.
This patch forces 8bit mode for each NAND CS in brcmnand_init_cs()
before doing nand_scan_ident() to ensure that BRCMNAND controller
is in 8bit mode when NAND READID command is issued.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use enum instead of magic numbers for CFG and CFG_EXT bitfields.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Anup Patel <anup.patel@broadcom.com>
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC
strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.
To enable SW BCH4, you need to specify this in your nand controller
DT node:
nand-ecc-mode = "soft_bch";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
Tested on a custom SPEAr600 board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
[Brian: tweaked the comments a bit]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
If nand_wait_ready() times out, this is silently ignored, and its
caller will then proceed to read from/write to the chip before it is
ready. This can potentially result in corruption with no indication as
to why.
While a 20ms timeout seems like it should be plenty enough, certain
behaviour can cause it to timeout much earlier than expected. The
situation which prompted this change was that CPU 0, which is
responsible for updating jiffies, was holding interrupts disabled
for a fairly long time while writing to the console during a printk,
causing several jiffies updates to be delayed. If CPU 1 happens to
enter the timeout loop in nand_wait_ready() just before CPU 0 re-
enables interrupts and updates jiffies, CPU 1 will immediately time
out when the delayed jiffies updates are made. The result of this is
that nand_wait_ready() actually waits less time than the NAND chip
would normally take to be ready, and then read_page() proceeds to
read out bad data from the chip.
The situation described above may seem unlikely, but in fact it can be
reproduced almost every boot on the MIPS Creator Ci20.
Therefore, this patch increases the timeout to 400ms. This should be
enough to cover cases where jiffies updates get delayed. In nand_wait()
the timeout was previously chosen based on whether erasing or
programming. This is changed to be 400ms unconditionally as well to
avoid similar problems there. nand_wait() is also slightly refactored
to be consistent with nand_wait{,_status}_ready(). These changes should
have no effect during normal operation.
Debugging this was made more difficult by the misleading comment above
nand_wait_ready() stating "The timeout is caught later" - no timeout was
ever reported, leading me away from the real source of the problem.
Therefore, a pr_warn() is added when a timeout does occur so that it is
easier to pinpoint similar problems in future.
Signed-off-by: Alex Smith <alex.smith@imgtec.com>
Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
Reviewed-by: Niklas Cassel <niklas.cassel@axis.com>
Cc: Alex Smith <alex@alex-smith.me.uk>
Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
With the previous modifications, lots of pxa3xx specific definitions can
be removed.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Rework the pxa3xx_nand driver to allow using functions exported by the
nand framework to detect the flash and the timings. Then setup the
timings using the helpers previously added.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add helpers to setup the timings in the pxa3xx driver. These helpers
allow to either make use of the nand framework nand_sdr_timings or the
pxa3xx specific pxa3xx_nand_host, for compatibility reasons.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Using readsl() result in a build error on i386. Fix this by using
ioread32_rep() instead, to allow compile testing the pxa3xx nand driver
on other architectures later.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
If common clock framework is configured, the driver generates a warning,
which is fixed by this change:
WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:727 clk_core_enable+0x2c/0xa4()
Modules linked in:
CPU: 0 PID: 1 Comm: swapper Not tainted 4.3.0-rc2+ #206
Hardware name: LPC32XX SoC (Flattened Device Tree)
Backtrace:
[<>] (dump_backtrace) from [<>] (show_stack+0x18/0x1c)
[<>] (show_stack) from [<>] (dump_stack+0x20/0x28)
[<>] (dump_stack) from [<>] (warn_slowpath_common+0x90/0xb8)
[<>] (warn_slowpath_common) from [<>] (warn_slowpath_null+0x24/0x2c)
[<>] (warn_slowpath_null) from [<>] (clk_core_enable+0x2c/0xa4)
[<>] (clk_core_enable) from [<>] (clk_enable+0x24/0x38)
[<>] (clk_enable) from [<>] (lpc32xx_nand_probe+0x208/0x248)
[<>] (lpc32xx_nand_probe) from [<>] (platform_drv_probe+0x50/0xa0)
[<>] (platform_drv_probe) from [<>] (driver_probe_device+0x18c/0x408)
[<>] (driver_probe_device) from [<>] (__driver_attach+0x70/0x94)
[<>] (__driver_attach) from [<>] (bus_for_each_dev+0x74/0x98)
[<>] (bus_for_each_dev) from [<>] (driver_attach+0x20/0x28)
[<>] (driver_attach) from [<>] (bus_add_driver+0x11c/0x248)
[<>] (bus_add_driver) from [<>] (driver_register+0xa4/0xe8)
[<>] (driver_register) from [<>] (__platform_driver_register+0x50/0x64)
[<>] (__platform_driver_register) from [<>] (lpc32xx_nand_driver_init+0x18/0x20)
[<>] (lpc32xx_nand_driver_init) from [<>] (do_one_initcall+0x11c/0x1dc)
[<>] (do_one_initcall) from [<>] (kernel_init_freeable+0x10c/0x1d4)
[<>] (kernel_init_freeable) from [<>] (kernel_init+0x10/0xec)
[<>] (kernel_init) from [<>] (ret_from_fork+0x14/0x24)
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
If common clock framework is configured, the driver generates a warning,
which is fixed by this change:
WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:727 clk_core_enable+0x2c/0xa4()
Modules linked in:
CPU: 0 PID: 1 Comm: swapper Not tainted 4.3.0-rc2+ #201
Hardware name: LPC32XX SoC (Flattened Device Tree)
Backtrace:
[<>] (dump_backtrace) from [<>] (show_stack+0x18/0x1c)
[<>] (show_stack) from [<>] (dump_stack+0x20/0x28)
[<>] (dump_stack) from [<>] (warn_slowpath_common+0x90/0xb8)
[<>] (warn_slowpath_common) from [<>] (warn_slowpath_null+0x24/0x2c)
[<>] (warn_slowpath_null) from [<>] (clk_core_enable+0x2c/0xa4)
[<>] (clk_core_enable) from [<>] (clk_enable+0x24/0x38)
[<>] (clk_enable) from [<>] (lpc32xx_nand_probe+0x290/0x568)
[<>] (lpc32xx_nand_probe) from [<>] (platform_drv_probe+0x50/0xa0)
[<>] (platform_drv_probe) from [<>] (driver_probe_device+0x18c/0x408)
[<>] (driver_probe_device) from [<>] (__driver_attach+0x70/0x94)
[<>] (__driver_attach) from [<>] (bus_for_each_dev+0x74/0x98)
[<>] (bus_for_each_dev) from [<>] (driver_attach+0x20/0x28)
[<>] (driver_attach) from [<>] (bus_add_driver+0x11c/0x248)
[<>] (bus_add_driver) from [<>] (driver_register+0xa4/0xe8)
[<>] (driver_register) from [<>] (__platform_driver_register+0x50/0x64)
[<>] (__platform_driver_register) from [<>] (lpc32xx_nand_driver_init+0x18/0x20)
[<>] (lpc32xx_nand_driver_init) from [<>] (do_one_initcall+0x11c/0x1dc)
[<>] (do_one_initcall) from [<>] (kernel_init_freeable+0x10c/0x1d4)
[<>] (kernel_init_freeable) from [<>] (kernel_init+0x10/0xec)
[<>] (kernel_init) from [<>] (ret_from_fork+0x14/0x24)
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The old PM model is deprecated. This is equivalent.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
mtd_{suspend,resume}() get called from mtdcore in a class suspend/resume
callback. We don't need to call them again here. In practice, this would
actually work OK, as nand_base actually handles nesting OK -- it just
might print warnings.
Untested, but there are few (no?) users of PM for this driver AFAIK.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
The ->read_xxx() methods are all passed the page number the NAND controller
is supposed to read, but ->write_xxx() do not have such a parameter.
This is a problem if we want to properly implement data
scrambling/randomization in order to mitigate MLC sensibility to repeated
pattern: to prevent bitflips in adjacent pages in the same block we need
to avoid repeating the same pattern at the same offset in those pages,
hence the randomizer/scrambler engine need to be passed the page value
in order to adapt its seed accordingly.
Moreover, adding the page parameter to the ->write_xxx() methods add some
consistency to the current API.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Josh Wu <josh.wu@atmel.com>
CC: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: Huang Shijie <shijie.huang@arm.com>
CC: Stefan Agner <stefan@agner.ch>
CC: devel@driverdev.osuosl.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-kernel@vger.kernel.org
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Owner is automatically set by mtdcore. Make use of that.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where mtd parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Make sure the device structure is properly shown in sysfs by properly
filling in dev.parent.
While at it, make use of the default owner and name values set by
mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Owner is automatically set by mtdcore. Make use of that.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Owner is automatically set by mtdcore. Make use of that.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Owner is automatically set by mtdcore. Make use of that.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Owner is automatically set by mtdcore. Make use of that.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner and name set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Owner is automatically set by mtdcore. Make use of that.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Owner is automatically set by mtdcore. Make use of that.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Owner and name are automatically set by mtdcore. Make use of that.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Owner is automatically set by mtdcore. Make use of that.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix a bug where parent device symlinks aren't shown in sysfs.
While at it, make use of the default owner value set by mtdcore.
Signed-off-by: Frans Klaver <fransklaver@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The BRCM NAND driver can be re-used for Broadcom ARM64 SoCs hence
this patch updates Kconfig to allow selection of MTD_NAND_BRCMNAND
for ARM64.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Pramod KUMAR <pramodku@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We should always type-cast pointer to "long" or "unsigned long"
because size of pointer is same as machine word size. This will
avoid pointer type-cast issues on both 32bit and 64bit systems.
This patch fixes pointer type-cast issue in brcmnand_write()
as-per above info.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
According to LPC32xx User's Manual all values measured in clock cycles
are programmable from 1 to 16 clocks (4 bits) starting from 0 in
bitfield, the current version of calculated clock cycles is too
conservative.
Correctness of 0 bitfield value (i.e. programmed 1 clock
timing) is proven with actual NAND chip devices.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In case if quotient of controller clock rate to device clock rate does
not fit into 4 bit value, choose the maximum acceptable value 0xF, which
stands for 16 clocks.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
No functional change, move bitfield calculations to macro
definitions with added clock rate argument, which are in turn defined
by new common SLCTAC_CLOCKS(c, n, s) macro definition.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use the nand_check_erased_ecc_chunk() function to test if the ECC error
was triggered by an erased page containing a few bitflips.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
sunxi_nfc_user_data_to_buf() is exposed as an inline function, replace the
NFC_BUF_TO_USER_DATA() macro by an inline function to be consistent.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The ECC engine is protecting a few OOB bytes. Retrieve them from the
USER_DATA register instead of reading them in raw mode (ie without the ECC
protection).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add helper functions to factorize the code dealing extra OOB bytes in the
normal and syndrome ECC implementations.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The sunxi_nfc_hw_ecc_read/write_chunk() functions have been created to
factorize the code in the normal and syndrome ECC implementation.
Make use of them where appropriate.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The logic behind normal and syndrome ECC handling is pretty much the same,
the only difference is the ECC bytes placement.
Create two functions to read/write ECC chunks. Those functions will later
be used by the sunxi_nfc_hw_ecc_read/write_page() and
sunxi_nfc_hw_syndrome_ecc_read/write_page() functions.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The code used to enable/disable the hardware ECC engine is repeated in a
lot of places. Create two functions to avoid code duplication.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The ->init_size() hook was introduced to let NAND controller drivers
support NAND devices that could not be described in the nand_ids table.
Since then, the core has added support for extended-id parsing and
full-id description, thus allowing to describe pretty much all existing
NANDs.
Moreover, this hook is not used by any mainline driver, and should not be
used by new drivers, because detecting the NAND chip is not something
controller specific.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
These really aren't needed, especially now that we embed the soc struct
in our private struct, so we can stash things there if needed.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Suffix mask macros with _MSK and add new helper macros to avoid manually
shifting values.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This must have been implicitly included on the builds I tested. Reported
by numerous test bots:
drivers/mtd/nand/vf610_nfc.c: In function 'vf610_nfc_resume':
drivers/mtd/nand/vf610_nfc.c:660:2: error: implicit declaration of function 'pinctrl_pm_select_default_state' [-Werror=implicit-function-declaration]
pinctrl_pm_select_default_state(dev);
^
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Stefan Agner <stefan@agner.ch>
This adds hardware ECC support using the BCH encoder in the NFC IP.
The ECC encoder supports up to 32-bit correction by using 60 error
correction bytes. There is no sub-page ECC step, ECC is calculated
always across the whole page (up to 2k pages).
Limitations:
- HW ECC: Only 2K page with 64+ OOB.
- HW ECC: Only 24 and 32-bit error correction implemented.
Raw writes have been tested using the generic nand_write_page_raw
implementation. However, raw reads are currently not possible
because the controller need to know whether we are going to use
the ECC mode already at NAND_CMD_READ0 command time. At this point
we do not have the information whether it is a raw read or a
regular read at driver level...
Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This driver supports Freescale NFC (NAND flash controller) found on
Vybrid (VF610), MPC5125, MCF54418 and Kinetis K70. The driver has
been tested using 8-bit and 16-bit NAND interface on the ARM based
Vybrid SoC VF500 and VF610 platform.
parameter page reading.
Limitations:
- Untested on MPC5125 and M54418.
- DMA and pipelining not used.
- 2K pages or less.
- No chip select, one NAND chip per controller.
- No hardware ECC.
Some paths have been hand-optimized and evaluated by measurements
made using mtd_speedtest.ko on a 100MB MTD partition.
Colibri VF50
eb write % eb read % page write % page read %
rel/opt 5175 11537 4560 11039
opt 5164 -0.21 11420 -1.01 4737 +3.88 10918 -1.10
none 5113 -1.20 11352 -1.60 4490 -1.54 10865 -1.58
Colibri VF61
eb write % eb read % page write % page read %
rel/opt 5766 13096 5459 12846
opt 5883 +2.03 13064 -0.24 5561 +1.87 12802 -0.34
none 5701 -1.13 12980 -0.89 5488 +0.53 12735 -0.86
rel = using readl_relaxed/writel_relaxed in optimized paths
opt = hand-optimized by combining multiple accesses into one read/write
The measurements have not been statistically verfied, hence use them
with care. The author came to the conclusion that using the relaxed
variants of readl/writel are not worth the additional code.
Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Tested-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Alexey Klimov <klimov.linux@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Read Denali hardware revision number and use it to
calculate max_banks, The encoding of max_banks changed
in Denali revision 5.1.
Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
[Brian: parentheses around macro arg]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
A read id operation followed by 0x00 reads the device ID while
a read id operation followed by 0x20 reads the possible ONFI identifier.
As the READID function did not propagate the second id parameter but had
a hard-coded call for 0x90 0x00, reading the ONFI identifier was not
possible and thus chips werde not detected (tested with
MT29F8G08ABABAWP)
Signed-off-by: Enrico Jorns <ejo@pengutronix.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
After the conversion of pxa architecture to common clock framework, the
NAND clock can be disabled on driver exit.
In this case, it happens that if the driver used the NAND and set the
DFI arbitration bit, the next access to a static memory controller area,
such as an ethernet card, will stall the system bus, and the core will
be stalled forever.
This is especially true on pxa31x SoCs, where the NDCR was augmented
with a new bit to prevent this lockups by giving full ownership of the
DFI arbiter to the SMC, in change SCr#6.
Fix this by clearing the DFI arbritration bit in driver exit. This
effectively prevents a lockup on zylonite when removing pxa3xx-nand
module, and using ethernet afterwards.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.
Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.
Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.
Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.
Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.
Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Now pxa architecture has a dmaengine driver, remove the access to direct
dma registers in favor of the more generic dmaengine code.
This should be also applicable for mmp and orion, provided they work in
device-tree environment.
This patch also removes the previous hack which was necessary to make
the driver work in a devicetree environment.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
[Brian: fixup use of 'enum dma_transfer_direction']
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The sunxi_nand_chips_cleanup() function is missing a call to list_del()
which generates a double free error.
Reported-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: <stable@vger.kernel.org> # 3.19+
Fixes: 1fef62c142 ("mtd: nand: add sunxi NAND flash controller support")
Tested-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Remove unneeded NULL test.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@@ expression x; @@
-if (x != NULL)
\(kmem_cache_destroy\|mempool_destroy\|dma_pool_destroy\)(x);
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add two helper functions to help NAND controller drivers test whether a
specific NAND region is erased or not.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The USER_DATA register cannot be accessed using byte accessors on A13
SoCs, thus triggering a bug when using memcpy_toio on this register.
Declare an helper macros to convert an OOB buffer into a suitable
USER_DATA value and vice-versa.
This patch also fixes an error in the oob_required logic (some OOB data
are not written even if the user required it) by removing the
oob_required condition, which is perfectly valid since the core already
fill ->oob_poi with FFs when oob_required is false.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: <stable@vger.kernel.org> # 3.19+
Fixes: 1fef62c142 ("mtd: nand: add sunxi NAND flash controller support")
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
nand_dt_init(), called from nand_scan_ident(), is already parsing the
generic MTD/NAND DT properties, and initializing the nand_chip struct
accordingly.
Rely on this initialization instead of manually parsing those properties.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Brian: rename 'np' -> 'flash_node' to accomodate for prior rename patch]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use a more descriptive name for the device_node element in struct nand_chip .
This name matches the element name used for device_node property of a flash
in the spi-nor framework.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
nand_scan_ident() leaves the chip deselected. So just issuing some commands
from the sunxi driver does not work. We need to select the chip before
writing the commands to the NAND device. This patch takes care of this.
Set the new timing on all dies implemented as suggested by Boris.
This was detected on the in-circuit ICnova-A20 SoM equipped with the
Micron MT29F32G08CBACAWP (4GiB) ONFI NAND device.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Roy Spliet <r.spliet@ultimaker.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Brian: fixup whitespace]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* SPI NOR: bug fix for a "end of table" check that resulted in a NULL
dereference in some cases
* SPI NOR: a few new IDs / feature flags
* OMAP2 NAND: rename module so it doesn't conflict with onenand omap2.ko
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJV8HKLAAoJEFySrpd9RFgtltcP/A3QdKLyGCxTEDBTB6Zd+Nqg
AcJa5R+ZSpDW/ZxOYEVrz2mTs9Js0sGC2aAEs4Phul9RLmnU4BLSr8LgTOWdx7en
TPY5KdgNSzf2IBYjmDXrFrkEwEPoYpodGShAmpBeNjGURgRGgMMsYn9DzTt5A+nc
98Qp+Zc7bEIONVKr3dqs3E/zmXKA43qZtC6MIvAd3qrrq2GHttN8ySER3qzVhUFF
e3N0TABuzGzESoJwZE0Z64PJz3SgGpH4KeFXC25/O69FjeCRg1RzcR1kkeMr8ZtL
qUCuphEQZ9yJorE7cRbsRT8liji6Sk9NaCsPcIXQpMxxTRJTd5TylWGI4ubJegNx
0EYToMz0DsxH0uTjWPEFF7ppJy1skwlkrdgjXzHfNNwV0LpT8tyBuD/RfXxoZgvH
X5VVDTh0eqVAweFMCSYSbtGUNxlH9YfnFvIaDItqkO+lawDbadj4XP1YfT8pHGwe
ASG0XMXiVGfkY6xW+nX6IhduMFUO+fuYbjp10rDzPg+BytCeiwh5kx9GVjpTZf92
VoZgeIXAfROUx3f20jHfouIHCSoidrAK09reJ7pU0hcIwpJEfhg/TCno2zZkfcCZ
MNpRjIZc73cqc+c4j3RnV74/hBBnwZqoAHr/RL6oiIYVWrUxJ+pNUPKJifxMGAyo
MOXGXCV1jcHBg1hrgTC6
=aXrv
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20150909' of git://git.infradead.org/linux-mtd
Pull more MTD updates from Brian Norris:
"There was one significant bug in my first pull request, fixed here. I
also threw in a few trivial ID additions and a small module rename.
Details:
- SPI NOR: bug fix for a "end of table" check that resulted in a NULL
dereference in some cases
- SPI NOR: a few new IDs / feature flags
- OMAP2 NAND: rename module so it doesn't conflict with onenand
omap2.ko"
* tag 'for-linus-20150909' of git://git.infradead.org/linux-mtd:
mtd: spi-nor: fix NULL dereference when no match found in spi_nor_ids[]
mtd: spi-nor: s25sl064p supports both dual and quad I/O
mtd: spi-nor: allow dual/quad reads on S25FL129P
mtd: nand: omap2: Rename shippable module to omap2_nand
mtd: spi-nor: Add support for sst25wf020a
mtd: spi-nor: Add support for Micron n25q064a serial flash
1/ Introduce ZONE_DEVICE and devm_memremap_pages() as a generic
mechanism for adding device-driver-discovered memory regions to the
kernel's direct map. This facility is used by the pmem driver to
enable pfn_to_page() operations on the page frames returned by DAX
('direct_access' in 'struct block_device_operations'). For now, the
'memmap' allocation for these "device" pages comes from "System
RAM". Support for allocating the memmap from device memory will
arrive in a later kernel.
2/ Introduce memremap() to replace usages of ioremap_cache() and
ioremap_wt(). memremap() drops the __iomem annotation for these
mappings to memory that do not have i/o side effects. The
replacement of ioremap_cache() with memremap() is limited to the
pmem driver to ease merging the api change in v4.3. Completion of
the conversion is targeted for v4.4.
3/ Similar to the usage of memcpy_to_pmem() + wmb_pmem() in the pmem
driver, update the VFS DAX implementation and PMEM api to provide
persistence guarantees for kernel operations on a DAX mapping.
4/ Convert the ACPI NFIT 'BLK' driver to map the block apertures as
cacheable to improve performance.
5/ Miscellaneous updates and fixes to libnvdimm including support
for issuing "address range scrub" commands, clarifying the optimal
'sector size' of pmem devices, a clarification of the usage of the
ACPI '_STA' (status) property for DIMM devices, and other minor
fixes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJV6Nx7AAoJEB7SkWpmfYgCWyYQAI5ju6Gvw27RNFtPovHcZUf5
JGnxXejI6/AqeTQ+IulgprxtEUCrXOHjCDA5dkjr1qvsoqK1qxug+vJHOZLgeW0R
OwDtmdW4Qrgeqm+CPoxETkorJ8wDOc8mol81kTiMgeV3UqbYeeHIiTAmwe7VzZ0C
nNdCRDm5g8dHCjTKcvK3rvozgyoNoWeBiHkPe76EbnxDICxCB5dak7XsVKNMIVFQ
NuYlnw6IYN7+rMHgpgpRux38NtIW8VlYPWTmHExejc2mlioWMNBG/bmtwLyJ6M3e
zliz4/cnonTMUaizZaVozyinTa65m7wcnpjK+vlyGV2deDZPJpDRvSOtB0lH30bR
1gy+qrKzuGKpaN6thOISxFLLjmEeYwzYd7SvC9n118r32qShz+opN9XX0WmWSFlA
sajE1ehm4M7s5pkMoa/dRnAyR8RUPu4RNINdQ/Z9jFfAOx+Q26rLdQXwf9+uqbEb
bIeSQwOteK5vYYCstvpAcHSMlJAglzIX5UfZBvtEIJN7rlb0VhmGWfxAnTu+ktG1
o9cqAt+J4146xHaFwj5duTsyKhWb8BL9+xqbKPNpXEp+PbLsrnE/+WkDLFD67jxz
dgIoK60mGnVXp+16I2uMqYYDgAyO5zUdmM4OygOMnZNa1mxesjbDJC6Wat1Wsndn
slsw6DkrWT60CRE42nbK
=o57/
-----END PGP SIGNATURE-----
Merge tag 'libnvdimm-for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm
Pull libnvdimm updates from Dan Williams:
"This update has successfully completed a 0day-kbuild run and has
appeared in a linux-next release. The changes outside of the typical
drivers/nvdimm/ and drivers/acpi/nfit.[ch] paths are related to the
removal of IORESOURCE_CACHEABLE, the introduction of memremap(), and
the introduction of ZONE_DEVICE + devm_memremap_pages().
Summary:
- Introduce ZONE_DEVICE and devm_memremap_pages() as a generic
mechanism for adding device-driver-discovered memory regions to the
kernel's direct map.
This facility is used by the pmem driver to enable pfn_to_page()
operations on the page frames returned by DAX ('direct_access' in
'struct block_device_operations').
For now, the 'memmap' allocation for these "device" pages comes
from "System RAM". Support for allocating the memmap from device
memory will arrive in a later kernel.
- Introduce memremap() to replace usages of ioremap_cache() and
ioremap_wt(). memremap() drops the __iomem annotation for these
mappings to memory that do not have i/o side effects. The
replacement of ioremap_cache() with memremap() is limited to the
pmem driver to ease merging the api change in v4.3.
Completion of the conversion is targeted for v4.4.
- Similar to the usage of memcpy_to_pmem() + wmb_pmem() in the pmem
driver, update the VFS DAX implementation and PMEM api to provide
persistence guarantees for kernel operations on a DAX mapping.
- Convert the ACPI NFIT 'BLK' driver to map the block apertures as
cacheable to improve performance.
- Miscellaneous updates and fixes to libnvdimm including support for
issuing "address range scrub" commands, clarifying the optimal
'sector size' of pmem devices, a clarification of the usage of the
ACPI '_STA' (status) property for DIMM devices, and other minor
fixes"
* tag 'libnvdimm-for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm: (34 commits)
libnvdimm, pmem: direct map legacy pmem by default
libnvdimm, pmem: 'struct page' for pmem
libnvdimm, pfn: 'struct page' provider infrastructure
x86, pmem: clarify that ARCH_HAS_PMEM_API implies PMEM mapped WB
add devm_memremap_pages
mm: ZONE_DEVICE for "device memory"
mm: move __phys_to_pfn and __pfn_to_phys to asm/generic/memory_model.h
dax: drop size parameter to ->direct_access()
nd_blk: change aperture mapping from WC to WB
nvdimm: change to use generic kvfree()
pmem, dax: have direct_access use __pmem annotation
dax: update I/O path to do proper PMEM flushing
pmem: add copy_from_iter_pmem() and clear_pmem()
pmem, x86: clean up conditional pmem includes
pmem: remove layer when calling arch_has_wmb_pmem()
pmem, x86: move x86 PMEM API to new pmem.h header
libnvdimm, e820: make CONFIG_X86_PMEM_LEGACY a tristate option
pmem: switch to devm_ allocations
devres: add devm_memremap
libnvdimm, btt: write and validate parent_uuid
...
- Support "hybrid" iommu/direct DMA ops for coherent_mask < dma_mask from Benjamin Herrenschmidt
- EEH fixes for SRIOV from Gavin
- Introduce rtas_get_sensor_fast() for IRQ handlers from Thomas Huth
- Use hardware RNG for arch_get_random_seed_* not arch_get_random_* from Paul Mackerras
- Seccomp filter support from Michael Ellerman
- opal_cec_reboot2() handling for HMIs & machine checks from Mahesh Salgaonkar
- Add powerpc timebase as a trace clock source from Naveen N. Rao
- Misc cleanups in the xmon, signal & SLB code from Anshuman Khandual
- Add an inline function to update POWER8 HID0 from Gautham R. Shenoy
- Fix pte_pagesize_index() crash on 4K w/64K hash from Michael Ellerman
- Drop support for 64K local store on 4K kernels from Michael Ellerman
- move dma_get_required_mask() from pnv_phb to pci_controller_ops from Andrew Donnellan
- Initialize distance lookup table from drconf path from Nikunj A Dadhania
- Enable RTC class support from Vaibhav Jain
- Disable automatically blocked PCI config from Gavin Shan
- Add LEDs driver for PowerNV platform from Vasant Hegde
- Fix endianness issues in the HVSI driver from Laurent Dufour
- Kexec endian fixes from Samuel Mendoza-Jonas
- Fix corrupted pdn list from Gavin Shan
- Fix fenced PHB caused by eeh_slot_error_detail() from Gavin Shan
- Freescale updates from Scott: Highlights include 32-bit memcpy/memset
optimizations, checksum optimizations, 85xx config fragments and updates,
device tree updates, e6500 fixes for non-SMP, and misc cleanup and minor
fixes.
- A ton of cxl updates & fixes:
- Add explicit precision specifiers from Rasmus Villemoes
- use more common format specifier from Rasmus Villemoes
- Destroy cxl_adapter_idr on module_exit from Johannes Thumshirn
- Destroy afu->contexts_idr on release of an afu from Johannes Thumshirn
- Compile with -Werror from Daniel Axtens
- EEH support from Daniel Axtens
- Plug irq_bitmap getting leaked in cxl_context from Vaibhav Jain
- Add alternate MMIO error handling from Ian Munsie
- Allow release of contexts which have been OPENED but not STARTED from Andrew Donnellan
- Remove use of macro DEFINE_PCI_DEVICE_TABLE from Vaishali Thakkar
- Release irqs if memory allocation fails from Vaibhav Jain
- Remove racy attempt to force EEH invocation in reset from Daniel Axtens
- Fix + cleanup error paths in cxl_dev_context_init from Ian Munsie
- Fix force unmapping mmaps of contexts allocated through the kernel api from Ian Munsie
- Set up and enable PSL Timebase from Philippe Bergheaud
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJV5+GzAAoJEFHr6jzI4aWA0iAP/jcd0kNaNBzLgcDKKygKdgz4
xn4EWu81vfMfZYWesb0ATrjlH0hLsRxSXoFUqUMhtJTa5kNAoCIaz/M8WBALS50h
aT+i7br4WEU2j2FcaMyP3iAZx/2hl+2utODJSHPRWPkec1fUDBfEyBf++e520RWM
HUQGIGZXh8yq7KMA96Pwhsvls9vOB8hS2UdU/NS8ff3J5jFvXC1/WmF2qfzJBS1V
8iHyz26Jl8+dJ+et7iC2oD5XQAjIH1oJgOyPVPBzAQttfi8RjuVzRA30TfPBAUwI
lC9nlmPy6bCe4kiQYWVB1z7GegHyW/9vkeuMj/u8mZbqpaayMEMZmd2C3iNDXNHx
i2NSvdln539t4qWYsV2v6lVCfa/ayDHD73Wackj5Dk394tzXnpCPhxNzc2yKEd5v
h7vwYc9jBhsbfSCSogaM+gSHJ1APgCidggHJMYYNA2nN2u6V62RpsMB7zp/1+Q2v
yqYdD8oYF4Dm21x/ujaNFrlizROD46WS0UqdJ3yP6HAqRYIpRXtibmpECJgt1n5h
HjADEci4hQ2UQxdMdp/Q5KZnPTJebBtrZrmkW5r6cZBUaTB5TVkFaEWN44CT/Loh
tMNeA3qOBN06CaQS2WL3UUUWpbZq9fSbWuUZ5lWZDb5AOyRxe5eWVYNLkiyIXozY
L24l1bYdBhXahnjoS/kc
=n9+X
-----END PGP SIGNATURE-----
Merge tag 'powerpc-4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc updates from Michael Ellerman:
- support "hybrid" iommu/direct DMA ops for coherent_mask < dma_mask
from Benjamin Herrenschmidt
- EEH fixes for SRIOV from Gavin
- introduce rtas_get_sensor_fast() for IRQ handlers from Thomas Huth
- use hardware RNG for arch_get_random_seed_* not arch_get_random_*
from Paul Mackerras
- seccomp filter support from Michael Ellerman
- opal_cec_reboot2() handling for HMIs & machine checks from Mahesh
Salgaonkar
- add powerpc timebase as a trace clock source from Naveen N. Rao
- misc cleanups in the xmon, signal & SLB code from Anshuman Khandual
- add an inline function to update POWER8 HID0 from Gautham R. Shenoy
- fix pte_pagesize_index() crash on 4K w/64K hash from Michael Ellerman
- drop support for 64K local store on 4K kernels from Michael Ellerman
- move dma_get_required_mask() from pnv_phb to pci_controller_ops from
Andrew Donnellan
- initialize distance lookup table from drconf path from Nikunj A
Dadhania
- enable RTC class support from Vaibhav Jain
- disable automatically blocked PCI config from Gavin Shan
- add LEDs driver for PowerNV platform from Vasant Hegde
- fix endianness issues in the HVSI driver from Laurent Dufour
- kexec endian fixes from Samuel Mendoza-Jonas
- fix corrupted pdn list from Gavin Shan
- fix fenced PHB caused by eeh_slot_error_detail() from Gavin Shan
- Freescale updates from Scott: Highlights include 32-bit memcpy/memset
optimizations, checksum optimizations, 85xx config fragments and
updates, device tree updates, e6500 fixes for non-SMP, and misc
cleanup and minor fixes.
- a ton of cxl updates & fixes:
- add explicit precision specifiers from Rasmus Villemoes
- use more common format specifier from Rasmus Villemoes
- destroy cxl_adapter_idr on module_exit from Johannes Thumshirn
- destroy afu->contexts_idr on release of an afu from Johannes
Thumshirn
- compile with -Werror from Daniel Axtens
- EEH support from Daniel Axtens
- plug irq_bitmap getting leaked in cxl_context from Vaibhav Jain
- add alternate MMIO error handling from Ian Munsie
- allow release of contexts which have been OPENED but not STARTED
from Andrew Donnellan
- remove use of macro DEFINE_PCI_DEVICE_TABLE from Vaishali Thakkar
- release irqs if memory allocation fails from Vaibhav Jain
- remove racy attempt to force EEH invocation in reset from Daniel
Axtens
- fix + cleanup error paths in cxl_dev_context_init from Ian Munsie
- fix force unmapping mmaps of contexts allocated through the kernel
api from Ian Munsie
- set up and enable PSL Timebase from Philippe Bergheaud
* tag 'powerpc-4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (140 commits)
cxl: Set up and enable PSL Timebase
cxl: Fix force unmapping mmaps of contexts allocated through the kernel api
cxl: Fix + cleanup error paths in cxl_dev_context_init
powerpc/eeh: Fix fenced PHB caused by eeh_slot_error_detail()
powerpc/pseries: Cleanup on pci_dn_reconfig_notifier()
powerpc/pseries: Fix corrupted pdn list
powerpc/powernv: Enable LEDS support
powerpc/iommu: Set default DMA offset in dma_dev_setup
cxl: Remove racy attempt to force EEH invocation in reset
cxl: Release irqs if memory allocation fails
cxl: Remove use of macro DEFINE_PCI_DEVICE_TABLE
powerpc/powernv: Fix mis-merge of OPAL support for LEDS driver
powerpc/powernv: Reset HILE before kexec_sequence()
powerpc/kexec: Reset secondary cpu endianness before kexec
powerpc/hvsi: Fix endianness issues in the HVSI driver
leds/powernv: Add driver for PowerNV platform
powerpc/powernv: Create LED platform device
powerpc/powernv: Add OPAL interfaces for accessing and modifying system LED states
powerpc/powernv: Fix the log message when disabling VF
cxl: Allow release of contexts which have been OPENED but not STARTED
...
The driver supports board files specificating the flash
device, by passing a pxa3xx_nand_flash struct (with
flash parameters) in the platform data struct.
Currently this support is not being used by any board file.
Moreover, we'd like to deprecate such usage in favor of
using the device table in nand_ids.c.
So let's remove the ad-hoc flash specification.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
As both omap2 onenand and omap2 nand driver modules are
named the same i.e. "omap2.ko", only one of them gets shipped
during MODPOST if both are configured as loadable modules.
To avoid this ambiguity let's ship the omap2 nand
driver as "omap2_nand.ko"
Reported by Pierre Neyron via github
https://github.com/beagleboard/linux/issues/40
Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add the full description of the Toshiba TC58NVG0S3E NAND chip in the
nand_ids table so that we can later use the NAND ECC info and ONFI timing
mode in controller drivers.
Tested with asm9260_nand driver. [Brian: driver still under review]
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The read ID count should be made as large as the maximum READ_ID size,
so there's no need to have dynamic size. This commit sets the hardware
maximum read ID count, which should be more than enough on all cases.
Also, we get rid of the read_id_bytes, and use a macro instead.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read after
an erase.
The issue is that in the interrupt handler, the status bits are cleared
after the new command is issued. There is a small temporal window where
this happens :
- the previous command has set the command done bit
- the ready for a command bit is set
- the handler submits the next command
- just then, the command completes, and the command done bit is still
set
- the handler clears the "previous" command done bit
- the handler exits
In this flow, the "command done" of the next command will never trigger
a new interrupt to finish the status command, as it was cleared for both
commands.
Fix this by clearing the status bit before submitting a new command.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
When the nand is first probe, and upon the first command start, the
status bits should be cleared before the interrupts are unmasked.
The bug is tricky : if the bootloader left a status bit set, the
unmasking of interrupts does trigger the interrupt handler before the
first command is issued, blocking the good behavior of the nand.
The same would happen if in pxa3xx_nand code flow a status bit is left,
and then a command is started.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
When keeping the configuration set by the bootloader (by using
the marvell,nand-keep-config property), the pxa3xx_nand_detect_config()
function is called and set the chunk size to 512 as a default value if
NDCR_PAGE_SZ is not set.
In the other case, when not keeping the bootloader configuration, no
chunk size is set. Fix this by adding a default chunk size of 512.
Fixes: 70ed85232a ("mtd: nand: pxa3xx: Introduce multiple page I/O
support")
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Remove extra space after the "platform:" prefix and make the alias matches
driver name.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
It is better to have device name prefixed the actual error message.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In recent kernels we have a lot of helper functions, including
devres API, to make life of device driver developer easy.
Convert the driver using devm_kzalloc() and pcim_enable_device().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Let's use module_pci_driver() macro to reduce code base of the driver.
There is no functional change.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
There is no need to user to see the core part of the driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The initial buffer is used for the initial commands used to detect
a flash device (STATUS, READID and PARAM).
ONFI param page is 256 bytes, and there are three redundant copies
to be read. JEDEC param page is 512 bytes, and there are also three
redundant copies to be read. Hence this buffer should be at least
512 x 3. This commits rounds the buffer size to 2048.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Preparation for uniform definition of ioremap, ioremap_wc, ioremap_wt,
and ioremap_cache, tree-wide.
Acked-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
IFC IO accressor are set at run time based
on IFC IP registers endianness.IFC node in
DTS file contains information about
endianness.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
While IS_ENABLED() is perfectly fine for CONFIG_* symbols, it is not
for other symbols such as __BIG_ENDIAN that is provided directly by
the compiler.
Switch to use CONFIG_CPU_BIG_ENDIAN instead of __BIG_ENDIAN.
Fixes: 27c5b17cd1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller")
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Replaces the hard coded "always use EDO" policy with that prescribed
by the ONFI 3.1 specification that EDO mode should always be used if tRC
is below 30ns.
Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The TIMING_CFG register was previously statically set to a magic value
(extracted from Allwinner's BSP) when initializing the NAND controller.
Now that we have more details about the TIMING_CFG register layout
(extracted from the A83 user manual) we can dynamically calculate the
appropriate value for each NAND chip and set it when selecting the
chip.
Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
r852_ecc_correct() reads a 32-bit register into a 16-bit variable,
ecc_reg, but this variable is later used as if it was larger. This is
reported by clang when building the kernel with many warnings:
drivers/mtd/nand/r852.c:512:11: error: shift count >= width of type
[-Werror,-Wshift-count-overflow]
ecc_reg >>= 16;
^ ~~
Fix this by making ecc_reg 32-bit, like the return type of
r852_read_reg_dword().
Signed-off-by: Nicolas Iooss <nicolas.iooss_linux@m4x.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
It is needed for k2l keystone2 EVM which uses NAND flash with 4K page
size, hence add support for 4K page size nand devices.
[Brian: similar work submitted by Murali Karicheri <m-karicheri2@ti.com>
and Hao Zhang <hzhang@ti.com>]
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Do not call free_device() in init_nandsim, the caller - ns_init_module -
will take care of that if something goes wrong.
Signed-off-by: Sheng Yong <shengyong1@huawei.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
If allocating ns->nand_pages_slab fails, do not try to destroy it when
cleaning up nandsim resources.
Signed-off-by: Sheng Yong <shengyong1@huawei.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
kasprintf() used in get_partition_name() does a dynamic
memory allocation and can fail. We have to handle that case.
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
kasprintf() does a dynamic memory allocation and can fail.
We have to handle that case.
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
device_create_file() can fail, therefore we have to
handle this case and abort.
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
It is a Bad Idea (TM) to call mtd_device_register() or
mtd_device_parse_register() twice on the same master MTD. Among other
things, it makes partition overrides (e.g., cmdlinepart) much more
difficult.
Since commit 727dc612c4 ("mtd: part: Create the master device node
when partitioned"), we now have a config option that accomplishes the
same purpose as the double-registration done in diskonchip.c -- it
forces the master MTD to *always* be registered, while partitions may
optionally show up in addition. Eventually, we might like to make
CONFIG_MTD_PARTITIONED_MASTER into the default, but this could be
disruptive to user-space expectations of MTD numbering, so we'll take
that slowly.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: Alexander Shiyan <shc_work@mail.ru>
It's harmless to add 'ofpart' (the only different parser supported in
default mtdpart.c) to plat_nand. That let's us kill off one more custom
partition prober listing.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This is an example of why it doesn't make much sense to put this
information here in the first place. I don't really know what purpose it
serves.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Hardware 8 bit ECC requires a different nand_ecclayout. Instead of adding yet
another static struct nand_ecclayout, generate it in code.
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The GPIO subsystem provides dummy GPIO consumer functions if GPIOLIB is
not enabled. Hence drivers that depend on GPIOLIB, but use GPIO consumer
functionality only, can still be compiled if GPIOLIB is not enabled.
Relax the dependency on GPIOLIB if COMPILE_TEST is enabled, where
appropriate.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Copy to/from oob io area might not be aligned to 4 bytes. When 8 bit ECC is
used, the buffer size is 26. Add memcpy16_{to,from}io, and use them to avoid
truncating the buffer. Prefer memcpy32_{to,from}io when the buffer is properly
aligned for better performance.
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
For 4k pages the i.MX NFC hardware uses no more than 218 bytes for 8bit ECC
data. Larger oobsize confuses the logic of copy_spare(). Limit the size of used
oob size to avoid that.
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
To give people without the reference manual at hand a chance to
understand how spare area is handled in the i.MX nand controller,
improve commenting, naming of variables and coding style.
No functional change intended.
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
[baruch: declare oob_chunk_size; update comments; reword commit log]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Remove static in front of ctrl. This variable should not be shared
between different instances of brcmnand_probe(), it should be local to
this function and stored on the stack.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The caller already adds a new line and in the other cases there is no
new line added.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
There are a few small hooks required for chips like BCM63138 and the
iProc family. Let's introduce those now.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
BCM7xxx chips are supported entirely by the library code, since they use
generic irqchip interfaces and don't need any extra SoC-specific
configuration.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This core originated in Set-Top Box chips (BCM7xxx) but is used in a
variety of other Broadcom chips, including some BCM63xxx, BCM33xx, and
iProc/Cygnus. It's been used only on ARM and MIPS SoCs, so restrict it
to those architectures.
There are multiple revisions of this core throughout the years, and
almost every version broke register compatibility in some small way, but
with some effort, this driver is able to support v4.0, v5.0, v6.x, v7.0,
and v7.1. It's been tested on v5.0, v6.0, v6.1, v7.0, and v7.1 recently,
so there hopefully are no more lurking inconsistencies.
This patch adds just some library support, on which platform drivers can
be built.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
These are already-documented common bindings for NAND chips. Let's
handle them in nand_base.
If NAND controller drivers need to act on this data before bringing up
the NAND chip (e.g., fill out ECC callback functions, change HW modes,
etc.), then they can do so between calling nand_scan_ident() and
nand_scan_tail().
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The platform_device_id is not modified by the driver and core uses it as
const.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The platform_device_id is not modified by the driver and core uses it as
const.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In preparation to enable ARCH_MMP on ARM64, a couple of fixes are needed
to build the pxa3xx_nand driver:
Legacy DMA will only used on ARM, so also make it condtional on
CONFIG_ARM.
__raw_{read,write}sl are not available on ARM64 or generically, so use
the readsl/writesl variants instead. Somewhat inconsistently,
{read,write}sl are inherently non-swapping with the generic version
using __raw_{read,write}l.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: linux-mtd@lists.infradead.org
[Brian: added one more __raw_readsl -> readsl]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Now that the driver handles the FIFO draining in a threaded interrupt, we can
base our timeout on jiffies and sleeping, instead of using mdelay.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
return type of wait_for_completion_timeout is unsigned long not int. An
appropriately named unsigned long is added and the assignment fixed up.
This not only should help readability but also handles corner cases
properly.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
wait_for_completion_timeout does not return negative values so
result handling here does not need to check for negative return.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
As all four bytes are written in any case the memset() is in vain.
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)
Signed-off-by: Fabian Frederick <fabf@skynet.be>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This statement was written with a cast-to-loff_t to be sure to have a
full 64-bit mask. However, we don't account for the fact that
'1 << this->bbt_erase_shift' might already overflow.
This will not be a problem in practice, since eraseblocks should never
be anywhere near 4GiB. But we can do this for completeness, and quiet
Coverity in the meantime. CID #1226806.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Don't leak this->bbt, and return early if check_create() fails. It helps
to have a single error path to avoid these problems.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The diskonchip driver almost uses the default nand_base hooks as-is,
except that it provides custom on-flash BBT descriptors and avoids using
factory-marked bad blockers.
So let's refactor the BBT initialization code into a private 'late_init'
hook which handles all the private details. Note the usage of
NAND_SKIP_BBTSCAN, which allows us to defer the BBT scan until we've
prepared everything.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* Add Kconfig option for keeping both the 'master' and 'partition' MTDs
registered as devices. This would really make a better default if we could
do it over, as it allows a lot more flexibility in (1) determining the flash
topology of the system from user-space and (2) adding temporary partitions
at runtime (ioctl(BLKPG)). Unfortunately, this would possibly cause
user-space breakage, as it will cause renumbering of the /dev/mtdX devices.
We'll see if we can change this in the future, as there have already been a
few people looking for this feature, and I know others have just been
working around our current limitations instead of fixing them this way.
* Along with the previous change, add some additional information to sysfs, so
user-space can read the offset of each partition within its master device
SPI NOR:
* add new device tree compatible binding to represent the mostly-compatible
class of SPI NOR flash which can be detected by their extended JEDEC ID
bytes, cutting down the duplication of our ID tables
* misc. new IDs
Various other miscellaneous fixes and changes
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVN9ypAAoJEFySrpd9RFgtaUQQAKmlCVMrxAKtF6U5jpzf07hA
7ZrcMdUTSwS++dBIAgDl6JSuSGT5KRLrS1FOp60p+VAjbD9VFcRLUUQxahXW1tAh
Dr8a3Akwd+lgIp77bZhWBY35dXmjIJ1GSzo7jdbJMDwAeDd3gBeSFTDoePsrCt6K
0/NPOsQzCFDDr1lwuQh1LzkLLQfVAC3ImNCBm5smvyEfhxXqzC02HOLf8Z9VMGnY
OxM9i0T6Ik3xeaaP/vH91sApmdn598gP5DB5cNr61YrZeVZmEoI4EWlOmagcYVC2
Tef9Ng4YmHGXo65k7XcKRykAVWECYAGr4HKCDZ8tsbvpfdbQMS5wHEgxMsAdvb01
aChcBNxf4w/Mh49fzjZppTlPN25FERRMnXt7CkUqQkqet9uDkD/5RNPl65ermeC7
EKx2MoxnpXrfZ0EkSxqrfdzP0oQx0AqAkbCyLIN42Vbxl7ckFMN3WAPQ2NR2Aaoh
SUiKwwaFFiK+C9qEytj0s+cmKPzsTzeQVYgp9NX64EfVQumqpsfbu6XIPV+FGy2i
DvHvmTEvm4SpqMPSnhkmZ6DFSjuzvQdqzKtDyZmRppxHKgWUsXYdftGPMG0+ZbaG
t4zysWfJG897TMVYLKY9pGqvouMuAVJ4kX1+iZbJc8dr4bwIzXIYuEGPLVv58gUO
KjjlYk91/jFNmBW5anxC
=aIsV
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20150422' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris:
"Common MTD:
- Add Kconfig option for keeping both the 'master' and 'partition'
MTDs registered as devices. This would really make a better
default if we could do it over, as it allows a lot more flexibility
in (1) determining the flash topology of the system from user-space
and (2) adding temporary partitions at runtime (ioctl(BLKPG)).
Unfortunately, this would possibly cause user-space breakage, as it
will cause renumbering of the /dev/mtdX devices. We'll see if we
can change this in the future, as there have already been a few
people looking for this feature, and I know others have just been
working around our current limitations instead of fixing them this
way.
- Along with the previous change, add some additional information to
sysfs, so user-space can read the offset of each partition within
its master device
SPI NOR:
- add new device tree compatible binding to represent the
mostly-compatible class of SPI NOR flash which can be detected by
their extended JEDEC ID bytes, cutting down the duplication of our
ID tables
- misc. new IDs
Various other miscellaneous fixes and changes"
* tag 'for-linus-20150422' of git://git.infradead.org/linux-mtd: (53 commits)
mtd: spi-nor: Add support for Macronix mx25u6435f serial flash
mtd: spi-nor: Add support for Winbond w25q64dw serial flash
mtd: spi-nor: add support for the Winbond W25X05 flash
mtd: spi-nor: support en25s64 device
mtd: m25p80: bind to "nor-jedec" ID, for auto-detection
Documentation: devicetree: m25p80: add "nor-jedec" binding
mtd: Make MTD tests cancelable
mtd: mtd_oobtest: Fix bitflip_limit usage in test case 3
mtd: docg3: remove invalid __exit annotations
mtd: fsl_ifc_nand: use msecs_to_jiffies for time conversion
mtd: atmel_nand: don't map the ROM table if no pmecc table offset in DT
mtd: atmel_nand: add a definition for the oob reserved bytes
mtd: part: Remove partition overlap checks
mtd: part: Add sysfs variable for offset of partition
mtd: part: Create the master device node when partitioned
mtd: ts5500_flash: Fix typo in MODULE_DESCRIPTION in ts5500_flash.c
mtd: denali: Disable sub-page writes in Denali NAND driver
mtd: pxa3xx_nand: cleanup wait_for_completion handling
mtd: nand: gpmi: Check for scan_bbt() error
mtd: nand: gpmi: fixup return type of wait_for_completion_timeout
...
Pull trivial tree from Jiri Kosina:
"Usual trivial tree updates. Nothing outstanding -- mostly printk()
and comment fixes and unused identifier removals"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial:
goldfish: goldfish_tty_probe() is not using 'i' any more
powerpc: Fix comment in smu.h
qla2xxx: Fix printks in ql_log message
lib: correct link to the original source for div64_u64
si2168, tda10071, m88ds3103: Fix firmware wording
usb: storage: Fix printk in isd200_log_config()
qla2xxx: Fix printk in qla25xx_setup_mode
init/main: fix reset_device comment
ipwireless: missing assignment
goldfish: remove unreachable line of code
coredump: Fix do_coredump() comment
stacktrace.h: remove duplicate declaration task_struct
smpboot.h: Remove unused function prototype
treewide: Fix typo in printk messages
treewide: Fix typo in printk messages
mod_devicetable: fix comment for match_flags
This is only an API consolidation and should make things more readable
it replaces var * HZ / 1000 by msecs_to_jiffies(var) which helps readability
and also handles all corner-cases properly.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
if atmel,pmecc-lookup-table-offset is not found in DT node, we don't
need to map the ROM table as we will build a runtime gf table anyway.
Reported-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
It's better to use a macro instead of just a number.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The Denali Controller IP does not support sub-page writes.
Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
return type of wait_for_completion_timeout is unsigned long not int, this
patch uses the return value of wait_for_completion_timeout in the condition
directly rather than assigning it to an incorrect type variable.
The variable used for handling the return of wait_for_cmpletion_timeout
was int but should be unsigned long, where it was not in use for
anything else and the return value in case of completion (>0) is not
used it was removed and wait_for_completion_timeout() used directly in
the if condition.
To make the timeout values a bit simpler to read and also handle all of
the corner cases correctly the declarations are moved to
msecs_to_jiffies().
The timeout declaration cleanup is just for readability
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In case of scan_bbt() failure, we should better propagate it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Huang Shijie <shijie.huang@intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
return type of wait_for_completion_timeout is unsigned long not int. The
return variable is renamed to reflect its use and the type adjusted to
unsigned long.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Huang Shijie <shijie.huang@intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Without this patch the timings are all set to 0 if not specified in the dts.
With this patch the driver falls back to use the defaults that are already
present in the driver and are known to work okay for some (older) boards.
Tested on a custom SPEAr600 based board.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
If a NAND device is not really present or pin muxes are not correctly
configured we can lock up the kernel waiting infinitely for NAND_STATUS
to be ready.
This can be easily reproduced on TI's DRA7-evm board by booting it
without NAND support in u-boot and disabling NAND pin muxes in the kernel.
Add timeout when waiting for NAND_CMD_RESET completion. As per ONFi v4.0
tRST can be upto 250ms for EZ-NAND and 5ms for raw NAND.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We're not initializing the ooblen field. Our users don't care, since
they check that oobbuf == NULL first, but it's good practice to zero
unused fields out.
We can drop the NULL initializations since we're memset()ing the whole
thing.
Noticed by Coverity, CID #200821, #200822
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Coverity noticed that these 'ret' assignments weren't being used. Let's
use them.
Note that nand_lock() and nand_unlock() are still not officially used by
any drivers.
Coverity CIDs #1227054 and #1227037
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The PARAM command was long unimplemented and it probably wasn't
noticed because chip probing using only the few bytes returned by the
READID command are good enough in most cases to determine the chip in
use.
Still to notice such a shortcoming earlier in the future would be nice
in case it's something more vital.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The mxc-nand driver never supported the PARAM command to read out the
ONFI parameter page and so always relied on probing my manufacturer and
device id (as provided by the READID command).
This patch implements reading out the first parameter page copy at least
which should be good enough in practise.
This makes the boot log change from
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xb1
nand: Micron NAND 128MiB 1,8V 16-bit
to
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xb1
nand: Micron MT29F1G16ABBDAH4
on my machine.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The mxc-nand controller works pagewise and so usually only sends
commands to the flash chip with column == 0. A request with column != 0
from the upper layer is then fulfilled by indexing appropriately into the
device's RAM buffer.
To be able to access the ONFI marker at offset 0x20 in reply to the
READID command however it's invalid to read 32 bytes starting from
column 0.
So let the function used to send the address cycles send the column
address actually passed instead of 0 and fix all callers to pass 0
instead appropriately. Also add some warnings in case this patch changes
the drivers semantics.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
When the hardware operates in 16 bit mode it always reads 16 bits even
for operations that only have the lower 8 bits defined. So the upper
bits must be discarded. Do this in the read_byte callback instead of
when reading the NAND id to support reading byte wise more than 5 bytes
and at other occations (like reading the ONFI parameter page).
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
At least on i.MX25 (i.e. NFCv2) preset_v2 is called with mtd->writesize
== 0 that is before the connect flash chip is detected. It then
configures for 8 bit ECC mode which needs 26 bytes of OOB per 512 bytes
main section. For flashes with a smaller OOB area issuing a read page
command makes the controller stuck with this config.
Note that this currently doesn't hurt because the first read page
command is issued only after detection is complete and preset is called
once more.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
While extending the mxc-nand driver it happend to me a few times that
the device was stuck and this made the machine hang during boot. So
implement a timeout and print a stack trace the first time this happens
to make it debuggable. The return type of the waiting function is also
changed to int to be able to handle the timeout in the caller.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Currently the driver read NFC command registers to get NFC busy flag.
Actually this flag also can be get by reading HSMC_SR register.
Use the read NFC command registers need mapping a huge memory region.
To save the mapped memory region, we change to check NFC busy flag by
reading HSMC_SR register.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The IRQF_DISABLED flag is a NOOP and has been scheduled for removal
since Linux v2.6.36 by commit 6932bf37be ("genirq: Remove
IRQF_DISABLED from core code").
According to commit e58aa3d2d0 ("genirq: Run irq handlers with
interrupts disabled"), running IRQ handlers with interrupts
enabled can cause stack overflows when the interrupt line of the
issuing device is still active.
This patch ends the grace period for IRQF_DISABLED (i.e.,
SA_INTERRUPT in older versions of Linux) and removes the
definition and all remaining usages of this flag.
There's still a few non-functional references left in the kernel
source:
- The bigger hunk in Documentation/scsi/ncr53c8xx.txt is removed entirely
as IRQF_DISABLED is gone now; the usage in older kernel versions
(including the old SA_INTERRUPT flag) should be discouraged. The
trouble of using IRQF_SHARED is a general problem and not specific to
any driver.
- I left the reference in Documentation/PCI/MSI-HOWTO.txt untouched since
it has already been removed in linux-next.
- All remaining references are changelogs that I suggest to keep.
Signed-off-by: Valentin Rothberg <valentinrothberg@gmail.com>
Cc: Afzal Mohammed <afzal@ti.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Ewan Milne <emilne@redhat.com>
Cc: Eyal Perry <eyalpe@mellanox.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Hannes Reinecke <hare@suse.de>
Cc: Hongliang Tao <taohl@lemote.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Bolle <pebolle@tiscali.nl>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Quentin Lambert <lambert.quentin@gmail.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Sricharan R <r.sricharan@ti.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Zhou Wang <wangzhou1@hisilicon.com>
Cc: iss_storagedev@hp.com
Cc: linux-mips@linux-mips.org
Cc: linux-mtd@lists.infradead.org
Link: http://lkml.kernel.org/r/1425565425-12604-1-git-send-email-valentinrothberg@gmail.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Fix typo, "Unkown" -> "Unknown"
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
If NO_DMA=y:
drivers/built-in.o: In function `hisi_nfc_probe':
hisi504_nand.c:(.text+0x23e646): undefined reference to `dmam_alloc_coherent'
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
s3c2410_nand_probe is not the name of the function.
These prints have little utility, so let's just kill them.
Reported-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
pxa3xx_flash_ids wasn't initialized to 0, which in certain cases could
end up containing corrupted values in its members. Fix this to avoid
possible issues.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
As the devicetree binding doesn't require num_cs to exist or be strictly
positive, and neither does the platform data case, a bug appear when
num_cs is set to 0 and panics the kernel.
The issue is that in alloc_nand_resource(), chip is dereferenced without
having a value assigned when num_cs == 0.
Fix this by returning ENODEV is num_cs == 0.
The panic seen is :
Unable to handle kernel NULL pointer dereference at virtual address 000002b8
pgd = c0004000
[000002b8] *pgd=00000000
Internal error: Oops: 5 [#1] PREEMPT ARM
Modules linked in:
Hardware name: Marvell PXA3xx (Device Tree Support)
task: c3822aa0 ti: c3826000 task.ti: c3826000
PC is at alloc_nand_resource+0x180/0x4a8
LR is at alloc_nand_resource+0xa0/0x4a8
pc : [<c0275b90>] lr : [<c0275ab0>] psr: 68000013
sp : c3827d90 ip : 00000000 fp : 00000000
r10: c3862200 r9 : 0000005e r8 : 00000000
r7 : c3865610 r6 : c3862210 r5 : c3924210 r4 : c3862200
r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : 00000000
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 0000397f Table: 80004018 DAC: 00000035
Process swapper (pid: 1, stack limit = 0xc3826198)
Stack: (0xc3827d90 to 0xc3828000)
...zip...
[<c0275b90>] (alloc_nand_resource) from [<c0275ff8>] (pxa3xx_nand_probe+0x140/0x978)
[<c0275ff8>] (pxa3xx_nand_probe) from [<c0258c40>] (platform_drv_probe+0x48/0xa4)
[<c0258c40>] (platform_drv_probe) from [<c0257650>] (driver_probe_device+0x80/0x21c)
[<c0257650>] (driver_probe_device) from [<c0257878>] (__driver_attach+0x8c/0x90)
[<c0257878>] (__driver_attach) from [<c0255ec4>] (bus_for_each_dev+0x58/0x88)
[<c0255ec4>] (bus_for_each_dev) from [<c0256ec8>] (bus_add_driver+0xd8/0x1d4)
[<c0256ec8>] (bus_add_driver) from [<c0257f14>] (driver_register+0x78/0xf4)
[<c0257f14>] (driver_register) from [<c00088a8>] (do_one_initcall+0x80/0x1e4)
[<c00088a8>] (do_one_initcall) from [<c048ed08>] (kernel_init_freeable+0xec/0x1b4)
[<c048ed08>] (kernel_init_freeable) from [<c0377d8c>] (kernel_init+0x8/0xe4)
[<c0377d8c>] (kernel_init) from [<c00095f8>] (ret_from_fork+0x14/0x3c)
Code: e503b234 e5953008 e1530001 caffffd1 (e59002b8)
---[ end trace a5770060c8441895 ]---
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change the handling of the data stage in the driver : don't pump data in
the top-half interrupt, but rather schedule a thread for non dma cases.
This will enable latencies in the data pumping, especially if delays are
required. Moreover platform shall be more reactive as other interrupts
can be served while pumping data.
No throughput degradation was observed, at least on the zylonite
platform, while a slight degradation was being expected.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The NDDB register holds the data that are needed by the read and write
commands.
However, during a read PIO access, the datasheet specifies that after each 32
bytes read in that register, when BCH is enabled, we have to make sure that the
RDDREQ bit is set in the NDSR register.
This fixes an issue that was seen on the Armada 385, and presumably other mvebu
SoCs, when a read on a newly erased page would end up in the driver reporting a
timeout from the NAND.
Cc: <stable@vger.kernel.org> # v3.14
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Current sh_flctl sets dma_slave_config :: slave_id field for DMAEngine,
but it is no longer needed. Let's remove it.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
The intent was to mask away some bits here, not to test true or false.
Fix: 54f531f6e3 ('mtd: hisilicon: add a new NAND controller driver for hisilicon hip04 Soc')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch adds the support for hisilicon 504 NAND controller which is now used
by Hisilicon Soc Hip04.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The PPC_OF is a ppc specific option which is used to mean that the
firmware device tree access functions are available. Since all the
ppc platforms have a device tree, it is aways set to 'y' for ppc.
So it makes no sense to keep a such option in the current kernel.
Replace it with PPC.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This driver uses NAND_ECC_HW_SYNDROME mode. The nand_scan_tail()
function would not complain about missing ecc->calculate,
ecc->correct, ecc->hwctl handlers.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The if and the else branch code are identical - so the condition has no
effect on the effective code. This patch removes the condition and the
duplicated code and updates the documentation as suggested by
Roger Quadros <rogerq@ti.com>.
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Reviewed-by: Pekon Gupta <pekon@pek-sem.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use the GPIO descriptor API instead of the deprecated legacy GPIO API to
manage the busy GPIO.
The patch updates both the jz4740 nand driver and the only user of the driver
the qi-lb60 board driver.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Previously, we requested that drivers pass ecc.size and ecc.bytes when
using NAND_ECC_SOFT_BCH. However, a driver is likely to only know the ECC
strength required for its NAND, so each driver would need to perform a
strength-to-bytes calculation.
Avoid duplicating this calculation in each driver by asking drivers to
pass ecc.size and ecc.strength so that the strength-to-bytes calculation
need only be implemented once.
This reverts/generalizes this commit:
mtd: nand: Base BCH ECC bytes on required strength
Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The MTD API reports -EUCLEAN only if the maximum number of bitflips
found in any ECC block exceeds a certain threshold. This is done to
avoid excessive -EUCLEAN reports to MTD users, which may induce
additional scrubbing of data, even when the ECC algorithm in use is
perfectly capable of handling the bitflips.
This threshold can be controlled by user-space (via sysfs), to allow
users to determine what they are willing to tolerate in their
application. But it still helps to have sane defaults.
In recent discussion [1], it was pointed out that our default threshold
is equal to the correction strength. That means that we won't actually
report any -EUCLEAN (i.e., "bitflips were corrected") errors until there
are almost too many to handle. It was determined that 3/4 of the
correction strength is probably a better default.
[1] http://lists.infradead.org/pipermail/linux-mtd/2015-January/057259.html
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <shijie.huang@intel.com>
Since in SAMA5D4 chip, the PMECC can correct bit flips in erased page.
So we add a DT property to indicate this hardware character.
If the PMECC support correct bitflip erased page (all data are 0xff).
Then we can use the PMECC correct the page and skip the erased page
check.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
atmel_nand_pmecc_read_page() will return the total bitflips in this
page. This is incorrect.
As one nand page includes multiple ecc sectors, that will cause the
returned total bitflips exceed ecc capablity.
So this patch will make pmecc_correct() return the max bitflips of all
sectors in the page. That also makes atmel_nand_pmecc_read_page() return
the max bitflips.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
There is no path to switch to STATE_DATAOUT_STATUS_M state, and
OPT_SMARTMEDIA is unused.
This is leftover from commit 0be718e552
("mtd: nand: remove a bunch of unused commands").
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In initialization routine, mtd_info->owner is overwritten by memset()
just after being initialized. This can be fixed by moving memset() calls
to just before setting mtd_info->owner. But the memory region is allocated
by kmalloc, so we can fix it by using kzalloc instead of kmalloc.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Jonathan McDowell <noodles@earth.li>
Cc: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
commit 3157d1ed23 ("mtd: denali: remove unnecessary casts") introduced
an error by using a wrong bitmask.
A uint16_t cast was replaced with & 0xff, should be & 0xffff.
Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Commit 7854d3f749 ("mtd: spelling, capitalization, uniformity") added
a correctly spelled line, but failed to remove the wrongly spelled one.
Commit 064a7694b5 ("mtd: Fix typo mtd/tests") then fixed the spelling
again, but left the duplication.
Fixes: 7854d3f749 ("mtd: spelling, capitalization, uniformity")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add nand_shutdown to wait for current nand operations to finish and prevent
further operations by changing the nand flash state to FL_SHUTDOWN.
This is addressing a problem observed during reboot tests using UBIFS
root file system: NAND erase operations that are in progress during
system reboot/shutdown are causing partial erased blocks. Although UBI should
be able to detect and recover from this error, this change will avoid
the creation of partial erased blocks on reboot in the middle of a NAND erase
operation.
Signed-off-by: Scott Branden <sbranden@broadcom.com>
Tested-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Now that we have raw functions properly implemented we can remove this
FIXME.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Huang Shijie <shijie.huang@intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
mx28evk board has a socket for NAND flash that comes with no NAND flash
populated, and then we get this message on every boot:
[ 1.657603] gpmi-nand 8000c000.gpmi-nand: driver registration failed: -19
which is not very helpful, so get rid of this error message.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* Add device tree support for DoC3
* SPI NOR:
Refactoring, for better layering between spi-nor.c and its driver users
(e.g., m25p80.c)
New flash device support
Support 6-byte ID strings
* NAND
New NAND driver for Allwinner SoC's (sunxi)
GPMI NAND: add support for raw (no ECC) access, for testing purposes
Add ATO manufacturer ID
A few odd driver fixes
* MTD tests:
Allow testers to compensate for OOB bitflips in oobtest
Fix a torturetest regression
* nandsim: Support longer ID byte strings
And more.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUj6PbAAoJEFySrpd9RFgtahcP/RGvknk9lnitaZI7+aZPP8Zs
AopfiuisLNv3v87EEBAWGYjRYm6vuuhO1z3K55iOIlemBVzoMIP0jf68XGy9uXnL
Ox6AHqxm55wwmc+CHry5/GssaqE6GzdPm8TBP+AGGNhHrhc+raJL55R0QJaoYVwX
pUxkhWaa4lZ6CrOIMQ3n+MEnduilHZoFIcXSc1UtI0y9IXsf1m0Qs8M5jGN8BQ16
HOVNJN9wOXF89swoi7bKsyAn+QFUYgdksAisncb6b9r5Ks5KHmcOuS1LM5X9YoUr
KfeogHfDM68fcaHsSvMU1xmxjXGtE+HFJE52eYNPB1fNbT3JAC13FFj92GeSsZtE
ekpCQh4OPLazT/2wCUHTQwC7T1dCilwyW7VJB9MSl7fSBo9P7jIiUHxVUdM43kez
Di02/XWi4IULTwrgzZiTT8yplFrVdvkmKHAAFEIoaVWiF/l4DeSodLGUw7owmNYn
rJPBPQulpPHRwKZY7gThJuOUXpgbT715GSbvmPYXimHBqmViiPkrhqQ/b/v4PRRs
Nlfhwbswr7WBq6vmPkd6eOyfdFANmWcZQMp/++BCdI/7mhfaik72GWMTBSuJ7hN5
PB+z95soHaKBWlbiDGGGPvuqJmPkOVq1R8itQdIYBWEh7eNSHecwVxyUJJ+V3oPv
QkD7mEP2ZozZe3Ys2EJQ
=gDW8
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20141215' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris:
"Summary:
- Add device tree support for DoC3
- SPI NOR:
Refactoring, for better layering between spi-nor.c and its
driver users (e.g., m25p80.c)
New flash device support
Support 6-byte ID strings
- NAND:
New NAND driver for Allwinner SoC's (sunxi)
GPMI NAND: add support for raw (no ECC) access, for testing
purposes
Add ATO manufacturer ID
A few odd driver fixes
- MTD tests:
Allow testers to compensate for OOB bitflips in oobtest
Fix a torturetest regression
- nandsim: Support longer ID byte strings
And more"
* tag 'for-linus-20141215' of git://git.infradead.org/linux-mtd: (63 commits)
mtd: tests: abort torturetest on erase errors
mtd: physmap_of: fix potential NULL dereference
mtd: spi-nor: allow NULL as chip name and try to auto detect it
mtd: nand: gpmi: add raw oob access functions
mtd: nand: gpmi: add proper raw access support
mtd: nand: gpmi: add gpmi_copy_bits function
mtd: spi-nor: factor out write_enable() for erase commands
mtd: spi-nor: add support for s25fl128s
mtd: spi-nor: remove the jedec_id/ext_id
mtd: spi-nor: add id/id_len for flash_info{}
mtd: nand: correct the comment of function nand_block_isreserved()
jffs2: Drop bogus if in comment
mtd: atmel_nand: replace memcpy32_toio/memcpy32_fromio with memcpy
mtd: cafe_nand: drop duplicate .write_page implementation
mtd: m25p80: Add support for serial flash Spansion S25FL132K
MTD: m25p80: fix inconsistency in m25p_ids compared to spi_nor_ids
mtd: spi-nor: improve wait-till-ready timeout loop
mtd: delete unnecessary checks before two function calls
mtd: nand: omap: Fix NAND enumeration on 3430 LDP
mtd: nand: add ATO manufacturer info
...
Implement raw OOB access functions to retrieve OOB bytes when accessing the
NAND in raw mode.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Several MTD users (either in user or kernel space) expect a valid raw
access support to NAND chip devices.
This is particularly true for testing tools which are often touching the
data stored in a NAND chip in raw mode to artificially generate errors.
The GPMI drivers do not implemenent raw access functions, and thus rely on
default HW_ECC scheme implementation.
The default implementation consider the data and OOB area as properly
separated in their respective NAND section, which is not true for the GPMI
controller.
In this driver/controller some OOB data are stored at the beginning of the
NAND data area (these data are called metadata in the driver), then ECC
bytes are interleaved with data chunk (which is similar to the
HW_ECC_SYNDROME scheme), and eventually the remaining bytes are used as
OOB data.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add a new function to copy bits (not bytes) from a memory region to
another one.
This function is similar to memcpy except it acts at bit level.
It is needed to implement GPMI raw access functions and adapt to the
hardware ECC engine which does not pad ECC bits to the next byte boundary.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
There is no need to use memcpy32_toio/memcpy32_fromio to transfer data
between memory and NFC sram. As the NFC sram is a also a memory space
not an I/O space, we can just use memcpy().
We remove the __iomem prefix for NFC sram to avoid sparse warnings.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This write_page() function is functionally equivalent to the default in
nand_base.c. Its only difference is in subpage programming support,
which cafe_nand.c does not advertise, so the difference is negligible.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
3430LDP has NAND flash with 32 bytes OOB size which is sufficient to hold
BCH8 codes but the small page check introduced in
commit b491da7233 ("mtd: nand: omap: clean-up ecc layout for BCH ecc schemes")
considers anything below 64 bytes unsuitable for BCH4/8/16. There is another
bug in that code where it doesn't skip the check for OMAP_ECC_HAM1_CODE_SW.
Get rid of that small page check code as it is insufficient and redundant
because we are checking for OOB available bytes vs ecc layout before calling
nand_scan_tail().
Fixes: b491da7233 ("mtd: nand: omap: clean-up ecc layout for BCH ecc schemes")
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
It may be useful info, e.g. if someone wants to use ubinize.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Freescale's QorIQ T Series processors support 8 IFC chip selects
within a memory map backward compatible with previous P Series
processors which supported only 4 chip selects.
Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
If there is no PMECC lookup table stored in ROM, or lookup table offset is
not specified, PMECC driver should build it in DDR by itself.
That make the PMECC driver work for some board which doesn't have PMECC
lookup table in ROM.
The PMECC use the BCH algorithm, so based on the build_gf_tables()
function in lib/bch.c, we can build the Galois Field lookup table.
For more information can refer to section 5.4 of PMECC controller
application note:
http://www.atmel.com/images/doc11127.pdf
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The driver was also using own method to do 32bit copy, turns out
we have a kernel API so use that instead
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The AM335x Technical Reference Manual (spruh73j.pdf) says
"Because the ECC engine includes only one accumulation context,
it can be allocated to only one chip-select at a time ... "
(7.1.3.3.12.3). Since the commit 97a288ba2c ("ARM: omap2+:
gpmc-nand: Use dynamic platform_device_alloc()") gpmc-nand
driver supports multiple NAND flash devices connected to
the single controller.
Use global 'struct nand_hw_control' among multiple NAND
instances to synchronize the access to the single ECC Engine.
Tested with custom AM335x board using 2x NAND flash chips.
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
update a comment in nand_command_lp() about specific requirements of
individual commands, the DEPLETE1 command was removed in the past and
the comment no longer applied
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
NAND devices with page sizes over 4 KiB require more than 4-bits of ECC
coverage. This patch calculates the value of ecc_bytes based on a still
assumed 512-byte step size (13-bits) and the ecc_strength.
Example:
Micron M73A devices (8 KiB page) require 8-bit ECC per 512-byte
Signed-off-by: Jordan Friendshuh <jfriendshuh@xes-inc.com>
Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The drivers/mtd/nand/gpio.c driver does not GPIO bitbang the complete
NAND protocol, but instead is GPIO _assisted_ -- a memory mapped interface
communicates commands and data, and only few control signals are connected
to GPIO pins.
Expand comments in the driver source and in the Kconfig description to
better reflect the very nature of the driver. The previous text could be
mistaken for complete GPIO bitbanging.
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* A regression from 3.16 which was noticed in 3.17. With the restructuring of
the m25p80.c driver and the SPI NOR library framework, we omitted proper
listing of the SPI device IDs. This means m25p80.c wouldn't auto-load
(modprobe) properly when built as a module. For now, we duplicate the device
IDs into both modules.
* The OMAP / ELM modules were depending on an implicit link ordering. Use
deferred probing so that the new link order (in 3.18-rc) can still allow for
successful probing.
* Fix suspend/resume support for LH28F640BF NOR flash
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJUVq20AAoJEFySrpd9RFgt8XQQAI4oIygz4zGQ6n0y4HOqwOBy
F4ZPtOuzuCYA86x2zORFgj4A9JGVjDQwTfnMQnn1NG+XEEmZMJfG2IwqlUxsZd5A
KkAS5XUoi/Fvq95Qi95KQYXqm1dniXEGKsRFsHKXIsnnDmbqRK5fBn6Ve5PAwcau
uru5FwrZ2Ve0EwF9/Z/bxAatRirdAhwgMGlaXdXLmL7S13NQGmXP9QI7CbxSZ38R
GJ+A6PhiYs6Sml6Ou5bovNXyFGfx4J35pk6nTWoWe5MfZHRQk447OQwBPbsrM119
Boq8F/6diXyJfuXdxvF6JiDmDzaw/fBY+Xuq1O6p+JzLONN16x93KlpAPhzy4a15
PwFHCBzg5khY49if/dmrPJ+kLkU+9wIHUib8m6HSImCKBT5Bv/VJXoQ1g4s1IJ8/
Di3mz/8pWm/cscABIkuEqb9TwwUrSHzVXgGH/p4CY0eUo8DbQQA1zDsig8aRIX36
FlAReaHH8QivdnghkMX9Px7SIo7XoMZZEi+55k8FrIVqjqEHNGx+w+BKhxgtFggN
nAg0l7NrLdQHpigK1SZjLFGIYi7MmarvbatUjVPGagiRqoQ0mCSS7eKX1DEs4EAo
P2g64BSJickGAhUiAV9ZO1EBoaOU6olIPpc33J+uG/8qBU1cNClx3FJ1UPWX27JQ
+FBsD1mec4FuoZ2SoE7r
=IxjM
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20141102' of git://git.infradead.org/linux-mtd
Pull MTD fixes from Brian Norris:
"Three main MTD fixes for 3.18:
- A regression from 3.16 which was noticed in 3.17. With the
restructuring of the m25p80.c driver and the SPI NOR library
framework, we omitted proper listing of the SPI device IDs. This
means m25p80.c wouldn't auto-load (modprobe) properly when built as
a module. For now, we duplicate the device IDs into both modules.
- The OMAP / ELM modules were depending on an implicit link ordering.
Use deferred probing so that the new link order (in 3.18-rc) can
still allow for successful probing.
- Fix suspend/resume support for LH28F640BF NOR flash"
* tag 'for-linus-20141102' of git://git.infradead.org/linux-mtd:
mtd: cfi_cmdset_0001.c: fix resume for LH28F640BF chips
mtd: omap: fix mtd devices not showing up
mtd: m25p80,spi-nor: Fix module aliases for m25p80
mtd: spi-nor: make spi_nor_scan() take a chip type name, not spi_device_id
mtd: m25p80: get rid of spi_get_device_id
Since commit 6d178ef2fd ("mtd: nand: Move ELM driver and rename as
omap_elm"), I don't have any mtd devices present on my am335x. This
changes the link order of the omap_elm and omap2 objects, causing them
to probe in the wrong order.
To fix this, make elm_config defer probing until the omap_elm driver is
actually loaded.
Signed-off-by: Frans Klaver <frans.klaver@xsens.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add support for the sunxi NAND Flash Controller (NFC).
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Brian: tweaked to fix ecc->steps issue]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
nandsim can simulate NAND Flash which returns the ID bytes specified
by first_id_byte, ..., fourth_id_byte module parameters.
In order to simulate NAND flash which returns more than four ID bytes,
this adds id_bytes module parameter which is specified by the array of
byte like this:
# modprobe nandsim id_bytes=0x98,0xdc,0x90,0x26,0x76,0x15,0x01,0x08 bch=1
This doesn't add fifth_id_byte, ..., seventh_id_byte module parameters,
because they are redundant. But the existing first_id_byte, ...,
fourth_id_byte module parameters are preserved and add "(obsolete)" to
the description.
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This replaces kzalloc() and ioremap() calls by devm_ functions
in the probe() routine, which automatically release the corresponding
resources when probe() fails or when the device is removed.
This simplifies simplifies the error management code, and brings
the below improvements or changes:
A. Fixing a bug reported by "make coccicheck":
If "board = devm_kzalloc()" fails, the probe() function jumps
incorrectly to label "no_res" and therefore returns without
running iounmap().
B. Requesting the memory region
Using devm_ioremap_resource() makes the probe() function request
the corresponding memory region before running ioremap(), as
it is supposed to do.
C. Standardizing the error codes:
The use of devm_ioremap_resource() changes the return value:
* -ENOMEM instead of -EIO in case of ioremap() failure,
* -EINVAL instead of -ENODEV in case of platform_get_resource()
failure.
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Since the commit 97a288ba2c ("ARM: omap2+: gpmc-nand: Use
dynamic platform_device_alloc()") gpmc-nand driver supports
multiple NAND flash devices connected to the single controller.
Remove global variable to make the code thread-safe.
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Pull slave-dmaengine updates from Vinod Koul:
"For dmaengine contributions we have:
- designware cleanup by Andy
- my series moving device_control users to dmanegine_xxx APIs for
later removal of device_control API
- minor fixes spread over drivers mainly mv_xor, pl330, mmp, imx-sdma
etc"
* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (60 commits)
serial: atmel: add missing dmaengine header
dmaengine: remove FSLDMA_EXTERNAL_START
dmaengine: freescale: remove FSLDMA_EXTERNAL_START control method
carma-fpga: move to fsl_dma_external_start()
carma-fpga: use dmaengine_xxx() API
dmaengine: freescale: add and export fsl_dma_external_start()
dmaengine: add dmaengine_prep_dma_sg() helper
video: mx3fb: use dmaengine_terminate_all() API
serial: sh-sci: use dmaengine_terminate_all() API
net: ks8842: use dmaengine_terminate_all() API
mtd: sh_flctl: use dmaengine_terminate_all() API
mtd: fsmc_nand: use dmaengine_terminate_all() API
V4L2: mx3_camer: use dmaengine_pause() API
dmaengine: coh901318: use dmaengine_terminate_all() API
pata_arasan_cf: use dmaengine_terminate_all() API
dmaengine: edma: check for echan->edesc => NULL in edma_dma_pause()
dmaengine: dw: export probe()/remove() and Co to users
dmaengine: dw: enable and disable controller when needed
dmaengine: dw: always export dw_dma_{en,dis}able
dmaengine: dw: introduce dw_dma_on() helper
...
The drivers should use dmaengine_terminate_all() API instead of
accessing the device_control which will be deprecated soon
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
The drivers should use dmaengine_terminate_all() API instead of
accessing the device_control which will be deprecated soon
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
The MTD_NAND_OMAP_BCH doesn't harm on legacy OMAP platforms
so don't state that it should be disabled for them.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit adds a hidden option to build the omap_elm as a module, if
omap2_nand is a module (and similarly in the built-in case).
This fixes the following build error when omap2_nand is chosen built-in,
and omap_elm is chosen as a module:
drivers/built-in.o: In function `omap_nand_probe':
drivers/mtd/nand/omap2.c:2010: undefined reference to `elm_config'
drivers/mtd/nand/omap2.c:1980: undefined reference to `elm_config'
drivers/mtd/nand/omap2.c:1927: undefined reference to `elm_config'
drivers/built-in.o: In function `omap_elm_correct_data':
drivers/mtd/nand/omap2.c:1444: undefined reference to `elm_decode_bch_error_page'
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The ELM driver is only used by the OMAP NAND driver, so let's move it
to the nand/ directory. Additionally, let's rename it to a less confusing
name, so the module is built with a meaningful name, instead of the previous
'elm.ko'.
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Usage of pr_err is frowned upon, so replace it with dev_err.
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The current code abuses ifdefs to determine if the selected ECC scheme
is supported by the running kernel. As a result the code is hard to read,
and it also fails to load as a module.
This commit removes all the ifdefs and instead introduces a function
omap2_nand_ecc_check() to check if the ECC is supported by using
IS_ENABLED(CONFIG_xxx).
Since IS_ENABLED() is true when a config is =y or =m, this change fixes the
module so it can be loaded with no issues.
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add the full description of the Hynix H27UCG8T2ATR-BC NAND chip in the
nand_ids table so that we can later use the NAND ECC infos and ONFI timings
mode in controller drivers.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add an onfi_timing_mode_default field to nand_chip and nand_flash_dev in
order to support NAND timings definition for non-ONFI NAND.
NAND that support better timings mode than the default one have to define
a new entry in the nand_ids table.
The default timing mode should be deduced from timings description from
the datasheet and the ONFI specification
(www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf, chapter 4.15
"Timing Parameters").
You should choose the closest mode that fit the timings requirements of
your NAND chip.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
- Fix indents
- Do not break a line unless it is longer than 80 columns
- Do not insert a whitespace before ';'
- Use whitespaces around operators
- Use braces for a "else" block where the "if" block uses ones.
Besides, eliminate all the warnings reported by checkpatch.pl:
- WARNING: quoted string split across lines
- WARNING: else is not generally useful after a break or return
- WARNING: Missing a blank line after declarations
- WARNING: Avoid line continuations in quoted strings
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We should use parentheses only when they are necessary
or they really improve the readability.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The variable "irq_status" in denali_read_page_raw() is set, but not used.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
It looks like this header file is a concatenation of two headers.
Anyway, the include guard should be renamed and placed at the correct
postion and the license block in the middle should be deleted.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This follows Chapter 2 of Linux's CodingStyle:
> However, never break user-visible strings such as printk messages,
> because that breaks the ability to grep for them.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This won't be used by NAND subsystem as we implement cmdfunc on our
own, but will allow us to write a bit cleaner code.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We are supposed to mask value, not multiply it. Add some comments btw.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
For PMECC, the pmecc_bytes_per_sector has same meaning as ecc.bytes.
So remove pmecc_bytes_per_sector and use ecc.bytes instead.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
For PMECC, the pmecc_sector_number has same meaning as ecc.steps.
So use ecc.steps to replace the pmecc_sector_number.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit adds a new platform-data boolean property that enables use
of a flash-based bad block table. This can also be enabled by setting
the 'nand-on-flash-bbt' devicetree property.
If the flash BBT is not enabled, the driver falls back to use OOB
bad block markers only, as before. If the flash BBT is enabled the
kernel will keep track of bad blocks using a BBT, in addition to
the OOB markers.
As explained by Brian Norris the reasons for using a BBT are:
""
The primary reason would be that NAND datasheets specify it these days.
A better argument is that nobody guarantees that you can write a
bad block marker to a worn out block; you may just get program failures.
This has been acknowledged by several developers over the last several
years.
Additionally, you get a boot-time performance improvement if you only
have to read a few pages, instead of a page or two from every block on
the flash.
""
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Retrieve the NFC clock to make sure it is enabled. Make that optional to ensure
compatibility with previous device trees but document it as mandatory so newer
device trees will include it.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The variable "retry" in wait_for_irq() is set, but not used.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We should rathar use "int" type for loop iterators.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Useless casts result in unreadable source code.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
All of these variables are initialized to zero and then
set to a different value below.
Zero-initializing is redundant.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We should use
/*
* Blah Blah ...
* ...
*/
for multi-line comment blocks.
In addition, refactor some comments where it seems reasonable and
remove some comments where the code is clear enough such as:
/* clear interrupts */
clear_interrupts(denali);
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
commit 65b97cf6b8 introduced in v3.7 caused a regression
by using a reversed CS_MASK thus causing omap_calculate_ecc to
always fail. As the NAND base driver never checks for .calculate()'s
return value, the zeroed ECC values are used as is without showing
any error to the user. However, this won't work and the NAND device
won't be guarded by any error code.
Fix the issue by using the correct mask.
Code was tested on omap3beagle using the following procedure
- flash the primary bootloader (MLO) from the kernel to the first
NAND partition using nandwrite.
- boot the board from NAND. This utilizes OMAP ROM loader that
relies on 1-bit Hamming code ECC.
Fixes: 65b97cf6b8 (mtd: nand: omap2: handle nand on gpmc)
Cc: <stable@vger.kernel.org> [3.7+]
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
For v3.12 and prior, 1-bit Hamming code ECC via software was the
default choice. Commit c66d039197 in v3.13 changed the behaviour
to use 1-bit Hamming code via Hardware using a different ECC layout
i.e. (ROM code layout) than what is used by software ECC.
This ECC layout change causes NAND filesystems created in v3.12
and prior to be unusable in v3.13 and later. So revert back to
using software ECC by default if an ECC scheme is not explicitely
specified.
This defect can be observed on the following boards during legacy boot
-omap3beagle
-omap3touchbook
-overo
-am3517crane
-devkit8000
-ldp
-3430sdp
Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
drivers/mtd/nand/nand_timings.c:45: warning: integer constant is too large for ‘long’ type
[ Editorial note: This is a false warning. Looking at ISO draft N1124
(this is approximately C11, the first PDF I had lying around),
section 6.4.4.1 (statement 5):
"The type of an integer constant is the first of the
corresponding list in which its value can be represented."
So this should not be an overflow, and any toolchain that says so
(e.g., GCC 4.4) is buggy.
-Brian ]
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
When enable NFC sram write, it will failed the mtd_nandbiterrs.ko test.
As in driver's nfc_sram_write_page(), if ops->mode equal to MTD_OSP_RAW,
driver assumes the data buffer contains one page data and one oob data
followed. And driver will write the page data and oob data to nand.
But this is wrong implementation. Since the data buffer don't contains the
oob data to write. We should write the chip->oob_poi to nand's oob.
So this patch fix it by writing the oob data from chip->oob_poi.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
chip->pagebuf is a 32-bit type (int), so the shift will only be applied
as 32-bit. Fix this for 64-bit safety.
Caught by Coverity.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The condition "if (irq_status == 0)" already ensures that one half of
the ternary ?: is dead. I think this should probably actually be a FAIL,
not a PASS.
Caught by Coverity.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Jamie Iles <jamie@jamieiles.com>
Do nand reset before write protect check.
If we want to check the WP# low or high through STATUS READ and check bit 7,
we must reset the device, other operation (eg.erase/program a locked block) can
also clear the bit 7 of status register.
As we know the status register can be refreshed, if we do some operation to trigger it,
for example if we do erase/program operation to one block that is locked, then READ STATUS,
the bit 7 of READ STATUS will be 0 indicate the device in write protect, then if we do
erase/program operation to another block that is unlocked, the bit 7 of READ STATUS will
be 1 indicate the device is not write protect.
Suppose we checked the bit 7 of READ STATUS is 0 then judge the WP# is low (write protect),
but in this case the WP# maybe high if we do erase/program operation to a locked block,
so we must reset the device if we want to check the WP# low or high through STATUS READ and
check bit 7.
Signed-off-by: White Ding <bpqw@micron.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
MAP10 command with '0x2000' data sets up a read-ahead/write access.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
PMECC can support 512, 1k, 2k, 4k, 8k page size.
The driver currently only support 2k page size nand flash. So this patch
add support to 512, 1k, 4k and 8k page size nand flash.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Some nand with 8k page size like Micron MT29F32G08ABAAAWP need more than 20us.
Signed-off-by: Raphaël Poggi <poggi.raph@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We check "cs" for array overflows but we don't check for underflows and
it upsets the static checkers.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
AMD-compatible CFI driver:
- Support OTP programming for Micron M29EW family
- Increase buffer write timeout, according to detected flash parameter info
NAND
- Add helpers for retrieving ONFI timing modes
- GPMI: provide option to disable bad block marker swapping (required for
Ka-On electronics platforms)
SPI NOR
- EON EN25QH128 support
- Support new Flag Status Register (FSR) on a few Micron flash
Common
- New sysfs entries for bad block and ECC stats
And a few miscellaneous refactorings, cleanups, and driver improvements
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJT5WCXAAoJEFySrpd9RFgt0rwP/1anAulAcve/QzVF9LDFPec8
jSvK8WWFcHLVb9EvTHtUjRz2RSRNhe0eeyEld3WpdKZZ73VVVaHnGdJv8J8Ys8jn
kfNBDfgDLFrVzycYCqjQ2gdvidCyrjQgtPP0E/Q/RN6FBur0/rp2WKoJ2FvuT6SS
kOz5f3TOe+iNtxQoJwkFvs/IjfFMThGs+YMJ8Z9s4LcJHD65T6hF+zDwl8xF2xfG
b104PsG3I58kJdYjKhRQ2/ol+YCPoVhQorhhuaqeouZum/Hb/2g3rKHVZpAv2n6m
JWnTpbdJDqGoPFVPyJr5Vm/UYOwxEBSWimuNp+2WN7EsXux1x9JZZl5+ZNUMmb4q
vxYhIDul2+Sg1lN+ruBe+xi6d8DI8Y5WIc9xJgn3YHLC8YSkiZ11bhQyyeHA9i5h
jZYKSkN/ERl8iAA4ULD6tsZv4ds8LVI/XOxrcSM7myQ4p8oY5QBxEWEuGPgyH6A6
qCVkc0TAriSPfcCBvs4o8s2uNUocq7x6ZT1xfdlJ0KVstCmeEJBJnBYwWIXR3tu7
3+I/bI41Q29ZGV8x5PEGDSgLVDNAJZnfGPuCwdMWuVD7UQuEEOJkCvy8o7C2Fold
hRXh3SlUICCGDzd0JdNmdt5hPuB0tzsG0YkRoRj2sS30TlHi77nN/m3HYi/JQ4UW
gA21laizfJ+z7g/5Kabb
=Wkmz
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20140808' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris:
"AMD-compatible CFI driver:
- Support OTP programming for Micron M29EW family
- Increase buffer write timeout, according to detected flash
parameter info
NAND
- Add helpers for retrieving ONFI timing modes
- GPMI: provide option to disable bad block marker swapping (required
for Ka-On electronics platforms)
SPI NOR
- EON EN25QH128 support
- Support new Flag Status Register (FSR) on a few Micron flash
Common
- New sysfs entries for bad block and ECC stats
And a few miscellaneous refactorings, cleanups, and driver
improvements"
* tag 'for-linus-20140808' of git://git.infradead.org/linux-mtd: (31 commits)
mtd: gpmi: make blockmark swapping optional
mtd: gpmi: remove line breaks from error messages and improve wording
mtd: gpmi: remove useless (void *) type casts and spaces between type casts and variables
mtd: atmel_nand: NFC: support multiple interrupt handling
mtd: atmel_nand: implement the nfc_device_ready() by checking the R/B bit
mtd: atmel_nand: add NFC status error check
mtd: atmel_nand: make ecc parameters same as definition
mtd: nand: add ONFI timing mode to nand_timings converter
mtd: nand: define struct nand_timings
mtd: cfi_cmdset_0002: fix do_write_buffer() timeout error
mtd: denali: use 8 bytes for READID command
mtd/ftl: fix the double free of the buffers allocated in build_maps()
mtd: phram: Fix whitespace issues
mtd: spi-nor: add support for EON EN25QH128
mtd: cfi_cmdset_0002: Add support for locking OTP memory
mtd: cfi_cmdset_0002: Add support for writing OTP memory
mtd: cfi_cmdset_0002: Invalidate cache after entering/exiting OTP memory
mtd: cfi_cmdset_0002: Add support for reading OTP
mtd: spi-nor: add support for flag status register on Micron chips
mtd: Account for BBT blocks when a partition is being allocated
...
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for 3.17. It contains:
- misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy updates
- MIPS ptrace updates and cleanups
- various fixes that will also go to -stable
- a number of cleanups and small non-critical fixes.
- NUMA support for the Loongson 3.
- more support for MSA
- support for MAAR
- various FP enhancements and fixes"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
MIPS: jz4740: remove unnecessary null test before debugfs_remove
MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive
MIPS: ZBOOT: implement stack protector in compressed boot phase
MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT
MIPS: Bonito64: remove a duplicate define
MIPS: Malta: initialise MAARs
MIPS: Initialise MAARs
MIPS: detect presence of MAARs
MIPS: define MAAR register accessors & bits
MIPS: mark MSA experimental
MIPS: Don't build MSA support unless it can be used
MIPS: consistently clear MSA flags when starting & copying threads
MIPS: 16 byte align MSA vector context
MIPS: disable preemption whilst initialising MSA
MIPS: ensure MSA gets disabled during boot
MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains
MIPS: fix MSA context for tasks which don't use FP first
MIPS: init upper 64b of vector registers when MSA is first used
MIPS: save/disable MSA in lose_fpu
MIPS: preserve scalar FP CSR when switching vector context
...
This patch changes the static memory controller registers to offsets
from base, prefixes them with AU1000_ to avoid silent failures due to
changed addresses and introduces helpers to access them.
No functional changes, comparing assembly of a few select functions shows
no differences.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7463/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
With a flash-based BBT there is no reason to move the Factory Bad
Block Marker from the data area buffer (to where it is mapped by the
GPMI NAND controller) to the OOB buffer. Thus, make this feature
configurable via DT. This is required for the Ka-Ro electronics
platforms.
In the original code 'this->swap_block_mark' was synonymous with
'!GPMI_IS_MX23()', so use the latter at the relevant places.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix the following error, which sometimes happens during the NFC data
transfer:
atmel_nand 80000000.nand: Time out to wait for interrupt: 0x00010000
atmel_nand 80000000.nand: something wrong, No XFR_DONE interrupt comes.
The root cause is that in the interrupt handler, we read the ISR but
only handle one interrupt. If more than one interrupt arrive at the same
time, then the second one will be lost.
During the NFC data transfer. Two NFC interrupts (NFC_CMD_DONE and
NFC_XFR_DONE) may come at the same time.
NFC_CMD_DONE means NFC command is sent, and NFC_XFR_DONE means NFC data
is transferred.
This patch can handle multiple NFC interrupts at the same time. During
the NFC data transfer, we need to wait for two NFC interrupts:
NFC_CMD_DONE and NFC_XFR_DONE.
Also we separate the completion initialization code to a
nfc_prepare_interrupt(), which is paired with nfc_wait_interrupt().
We call nfc_prepare_interrupt() before sending out nfc commands, to make
sure no interrupt lost.
Reported-by: Matthieu CRAPET <Matthieu.CRAPET@ingenico.com>
Tested-by: Matthieu Crapet <Matthieu.Crapet@ingenico.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In nfc_device_ready(), it's more reasonable to check R/B bit in NFC_SR
than waiting for the R/B interrupt. It cost less time.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Tested-by: Matthieu Crapet <Matthieu.Crapet@ingenico.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add a new function to read the NFC status. Meantime, this function will
check if there is any errors in NFC.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Tested-by: Matthieu Crapet <Matthieu.Crapet@ingenico.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
If the ecc parameter is not the same as definition, when the
mtd core check these parameters, it will give the error result.
Take the following as an example:
Calculate how many bits can be corrected in one page.
According to the ecc parameters definition,
one page correct bits = (mtd->writesize * ecc->strength) / ecc->size
take the following use case as an example:
mtd->writesize = 2048 bytes
ecc->strength = 4 bytes (for 512 bytes)
before this patch, the ecc->size = 2048, so the result is 4 bytes.
after this patch, the ecc->size = 512, so the result is 16 bytes.
So, align the ecc parameters the same as definition to correct
this kind of error.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add a converter to retrieve NAND timings from an ONFI NAND timing mode.
At the moment, only SDR NAND timings are supported.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The Denali NAND driver reads only 5 bytes of ID, but some Hynix and Samsung
have size parameters in the 6th byte. As a result, the page and oob size
for a Hynix H27UAG8T2B were calculated incorrectly and the driver failed to
load.
The solution is to read 8 bytes of ID, as expected by the NAND framework.
Signed-off-by: Graham Moore <grmoore@altera.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In commit 67a9ad9b8a ("mtd: nand: Warn the user if the selected ECC
strength is too weak"), a check was added to inform the user when the
ECC used for a NAND device is weaker than the recommended ECC
advertised by the NAND chip. However, the warning uses WARN_ON(),
which has two undesirable side-effects:
- It just prints to the kernel log the fact that there is a warning
in this file, at this line, but it doesn't explain anything about
the warning itself.
- It dumps a stack trace which is very noisy, for something that the
user is most likely not able to fix. If a certain ECC used by the
kernel is weaker than the advertised one, it's most likely to make
sure the kernel uses an ECC that is compatible with the one used by
the bootloader, and changing the bootloader may not necessarily be
easy. Therefore, normal users would not be able to do anything to
fix this very noisy warning, and will have to suffer from it at
every kernel boot. At least every time I see this stack trace in my
kernel boot log, I wonder what new thing is broken, just to realize
that it's once again this NAND ECC warning.
Therefore, this commit turns:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1 at /home/thomas/projets/linux-2.6/drivers/mtd/nand/nand_base.c:4051 nand_scan_tail+0x538/0x780()
Modules linked in:
CPU: 0 PID: 1 Comm: swapper Not tainted 3.16.0-rc3-dirty #4
[<c000e3dc>] (unwind_backtrace) from [<c000bee4>] (show_stack+0x10/0x14)
[<c000bee4>] (show_stack) from [<c0018180>] (warn_slowpath_common+0x6c/0x8c)
[<c0018180>] (warn_slowpath_common) from [<c001823c>] (warn_slowpath_null+0x1c/0x24)
[<c001823c>] (warn_slowpath_null) from [<c02c50cc>] (nand_scan_tail+0x538/0x780)
[<c02c50cc>] (nand_scan_tail) from [<c0639f78>] (orion_nand_probe+0x224/0x2e4)
[<c0639f78>] (orion_nand_probe) from [<c026da00>] (platform_drv_probe+0x18/0x4c)
[<c026da00>] (platform_drv_probe) from [<c026c1f4>] (really_probe+0x80/0x218)
[<c026c1f4>] (really_probe) from [<c026c47c>] (__driver_attach+0x98/0x9c)
[<c026c47c>] (__driver_attach) from [<c026a8f0>] (bus_for_each_dev+0x64/0x94)
[<c026a8f0>] (bus_for_each_dev) from [<c026bae4>] (bus_add_driver+0x144/0x1ec)
[<c026bae4>] (bus_add_driver) from [<c026cb00>] (driver_register+0x78/0xf8)
[<c026cb00>] (driver_register) from [<c026da5c>] (platform_driver_probe+0x20/0xb8)
[<c026da5c>] (platform_driver_probe) from [<c00088b8>] (do_one_initcall+0x80/0x1d8)
[<c00088b8>] (do_one_initcall) from [<c0620c9c>] (kernel_init_freeable+0xf4/0x1b4)
[<c0620c9c>] (kernel_init_freeable) from [<c049a098>] (kernel_init+0x8/0xec)
[<c049a098>] (kernel_init) from [<c00095f0>] (ret_from_fork+0x14/0x24)
---[ end trace 62f87d875aceccb4 ]---
Into the much shorter, and much more useful:
nand: WARNING: MT29F2G08ABAEAWP: the ECC used on your system is too weak compared to the one required by the NAND chip
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In addition to mtd_block_isbad(), which checks if a block is bad or
reserved, it's needed to check if a block is reserved only (but not
bad). This commit adds an MTD interface for it, in a similar fashion to
mtd_block_isbad().
While here, fix mtd_block_isbad() so the out-of-bounds checking is done
before the callback check.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This driver's suspend/resume hooks are no-ops, so just remove them.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Mike Frysinger <vapier.adi@gmail.com>
Use clk_prepare_enable/clk_disable_unprepare to make the driver
work properly with common clock framework.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
These drivers don't need to explicitly initialize their bitflip
thresholds. The comment is no longer correct, since nand_scan_tail()
performs this initialization as of the following commit:
commit ea3b2ea24e
Author: Shmulik Ladkani <shmulik@jungo.com>
Date: Fri Jun 8 18:29:06 2012 +0300
mtd: nand: initialize bitflip_threshold prior to BBT scanning
(It seems there were some parallel efforts on writing/submitting these
drivers, and Shmulik's bug fix.)
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Roland Stigge <stigge@antcom.de>
Pull vfs updates from Al Viro:
"This the bunch that sat in -next + lock_parent() fix. This is the
minimal set; there's more pending stuff.
In particular, I really hope to get acct.c fixes merged this cycle -
we need that to deal sanely with delayed-mntput stuff. In the next
pile, hopefully - that series is fairly short and localized
(kernel/acct.c, fs/super.c and fs/namespace.c). In this pile: more
iov_iter work. Most of prereqs for ->splice_write with sane locking
order are there and Kent's dio rewrite would also fit nicely on top of
this pile"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: (70 commits)
lock_parent: don't step on stale ->d_parent of all-but-freed one
kill generic_file_splice_write()
ceph: switch to iter_file_splice_write()
shmem: switch to iter_file_splice_write()
nfs: switch to iter_splice_write_file()
fs/splice.c: remove unneeded exports
ocfs2: switch to iter_file_splice_write()
->splice_write() via ->write_iter()
bio_vec-backed iov_iter
optimize copy_page_{to,from}_iter()
bury generic_file_aio_{read,write}
lustre: get rid of messing with iovecs
ceph: switch to ->write_iter()
ceph_sync_direct_write: stop poking into iov_iter guts
ceph_sync_read: stop poking into iov_iter guts
new helper: copy_page_from_iter()
fuse: switch to ->write_iter()
btrfs: switch to ->write_iter()
ocfs2: switch to ->write_iter()
xfs: switch to ->write_iter()
...
The gpmi's IP for imx6sx is nearly the same as the gpmi's IP for imx6q,
except the following two new features:
(1) the new BCH contoller has 62-BIT correcting ECC strength
(The BCH for imx6q only has 40-BIT ECC strength).
(2) add the hardware Randomizer support.
This patch does the follow changes:
(1) add a new macro GPMI_IS_MX6SX to represent the imx6sx's gpmi.
(2) add a new macro GPMI_IS_MX6.
We use this macro to initialize the same registers for both
imx6sx and imx6q, and so on.
(3) add a new gpmi_devdata instance, the gpmi_devdata_imx6sx, for
imx6sx.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch moves data allocated using kzalloc to managed data allocated
using devm_kzalloc and cleans now unnecessary kfrees in probe and remove
functions. Also, the now unnecessary label out_err_hw_init is done away
with and the label out_err_kzalloc is renamed to out_err.
The following Coccinelle semantic patch was used for making the change:
@platform@
identifier p, probefn, removefn;
@@
struct platform_driver p = {
.probe = probefn,
.remove = removefn,
};
@prb@
identifier platform.probefn, pdev;
expression e, e1, e2;
@@
probefn(struct platform_device *pdev, ...) {
<+...
- e = kzalloc(e1, e2)
+ e = devm_kzalloc(&pdev->dev, e1, e2)
...
?-kfree(e);
...+>
}
@rem depends on prb@
identifier platform.removefn;
expression e;
@@
removefn(...) {
<...
- kfree(e);
...>
}
Signed-off-by: Himangi Saraogi <himangi774@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The pxa3xx_nand driver currently uses __raw_writel() and __raw_readl()
to access I/O registers. However, those functions do not do any
endianness swapping, which means that they won't work when the CPU
runs in big-endian but the I/O registers are little endian, which is
the common situation for ARM systems running big endian.
Since __raw_writel() and __raw_readl() do not include any memory
barriers and the pxa3xx_nand driver can only be compiled for ARM
platforms, the closest I/o accessors functions that do endianess
swapping are writel_relaxed() and readl_relaxed().
This patch has been verified to work on Armada XP GP: without the
patch, the NAND is not detected when the kernel runs big endian while
it is properly detected when the kernel runs little endian. With the
patch applied, the NAND is properly detected in both situations
(little and big endian).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.13+
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The two loops in r852_write_buf() are designed to handle 4-byte-aligned
and then 1-byte-aligned portions, respectively. However, there are two
issues:
(1) The first loop will only terminate if 'len' is a multiple of 4
(2) The second loop will never terminate if it runs at least once
Rewrite these loops as they were probably intended. Compile tested only.
Issues pointed out by Coverity Scan.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Maxim Levitsky <maximlevitsky@gmail.com>
This commit adds support for the user to specify the ECC strength
and step size through the devicetree. We keep the previous behavior,
when there is no DT parameter provided.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Let's make pxa_ecc_init() return a negative errno on error or zero
if succesful, which is standard kernel practice. Also, report the
selected ECC strength and step size, which is important information.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit makes use of the chip->ecc_strength_ds and chip->ecc_step_ds which
contain the datasheet minimum requested ECC strength to produce a noisy warning
if the configured ECC strength is weaker.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch add support for BCH16 ecc-scheme in OMAP NAND driver, by extending
following functions:
- omap_enable_hwecc (nand_chip->ecc.hwctl): configure GPMC controller
- omap_calculate_ecc_bch (nand_chip->ecc.calculate): fetch ECC signature from GPMC controller
- omap_elm_correct_data (nand_chip->ecc.correct): detect and correct ECC errors using ELM
(a) BCH16 ecc-scheme can detect and correct 16 bit-flips per 512Bytes of data.
(b) BCH16 ecc-scheme generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy the relation: "OOBsize per page >= 26 * (page-size / 512)"
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
A workaround was already in place that set the WP bit in the
IFC_CSPR0 register after a STATUS command, however it used an 8-bit
write method. As a result, the WP bit was never set on 16-bit devices,
and these devices would eventually be incorrectly marked as
write-protected.
This patch checks the chip options for a 16-bit device and uses the
appropriate write method to set the WP bit after a STATUS command.
Signed-off-by: Joe Schultz <jschultz@xes-inc.com>
Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The IFC buffer is accessed via 8-bit and 16-bit accessors. Changing
the 'addr' member of 'struct fsl_ifc_nand_ctrl' from 'u8 __iomem *' to
'void __iomem *' eliminates the need for explicit casts when the
16-bit accessors are used.
Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
nand_base can be passed a kmap()'d buffers from highmem by
filesystems like jffs2. This results in failure to map the
physical address of the DMA buffer on various contoller
driver on different platforms. This change adds a chip option
to use preallocated databuf as bounce buffers used in
nand_do_read_ops() and nand_do_write_ops().
This allows for specific nand controller driver to set this
option as needed.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
As subpage write is enabled by default for all drivers, nand_write_subpage_hwecc
causes a crash if the driver did not register ecc->hwctl or ecc->calculate.
This behavior was introduced in
commit 837a6ba4f3
"mtd: nand: subpage write support for hardware based ECC schemes".
This fixes a crash by emulating subpage write support by padding sub-page data
with 0xff on either sides to make it full page compatible.
Reported-by: Helmut Schaa <helmut.schaa@googlemail.com>
Tested-by: Helmut Schaa <helmut.schaa@googlemail.com>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Scott Wood <scottwood@freescale.com>
Cc: <stable@vger.kernel.org> # 3.10.x+
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Make of_device_id array const, because all OF functions
handle it as const.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Make of_device_id array const, because all OF functions
handle it as const.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
fixes: commit 62116e5171
mtd: nand: omap2: Support for hardware BCH error correction.
In omap_elm_correct_data(), if bitflip_count in an erased-page is within the
correctable limit (< ecc.strength), then it is not indicated back to the caller
ecc->read_page().
This mis-guides upper layers like MTD and UBIFS layer to assume erased-page as
perfectly clean and use it for writing even if actual bitflip_count was
dangerously high (bitflip_count > mtd->bitflip_threshold).
This patch fixes this above issue, by returning 'stats' to caller
ecc->read_page() under all scenarios.
Reported-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Cc: <stable@vger.kernel.org> # 3.9.x+
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The nand_chip::erase_cmd callback previously served a dual purpose; for
one, it allowed a per-flash-chip override, so that AG-AND devices could
use a different erase command than other NAND. These AND devices were
dropped in commit 14c6578683 (mtd: nand:
remove AG-AND support). On the other hand, some drivers (denali and
doc-g4) need to use this sort of callback to implement
controller-specific erase operations.
To make the latter operation easier for some drivers (e.g., ST's new BCH
NAND driver), it helps if the command dispatch and wait functions can be
lumped together, rather than called separately.
This patch does two things:
1. Pull the call to chip->waitfunc() into chip->erase_cmd(), and return
the status from this callback
2. Rename erase_cmd() to just erase(), since this callback does a
little more than just send a command
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Lee Jones <lee.jones@linaro.org>
Since we are about to introduce new methods (read_iter/write_iter), the
tests in a bunch of places would have to grow inconveniently. Check
once (at open() time) and store results in ->f_mode as FMODE_CAN_READ
and FMODE_CAN_WRITE resp. It might end up being a temporary measure -
once everything switches from ->aio_{read,write} to ->{read,write}_iter
it might make sense to return to open-coded checks. We'll see...
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Sub page write doesn't work because of hw issue in controller found on
Keystone SOCs. AEMIF controller is also used on DaVinci SOCs which
don't seems to have any issue. So add "ti,keysone-nand" compatible
to nand driver in order to set NAND_NO_SUBPAGE_WRITE option.
Cc: Warner Losh <imp@bsdimp.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
More and more chips use the GPMI controller, but these chips may use different
version of the IPs for GPMI and BCH. Different IPs have
different features, such as the BCH's maximum ECC strength:
imx23/imx28 -- the BCH's maximum ECC strength is 20
imx6q -- the BCH's maximum ECC strength is 40
imx6sx -- the BCH's maximum ECC strength is 62
This patch does the following things:
[1] add a new data structure, gpmi_devdata{}, to store the information for
each IP. Besides the IP version, we store the following information:
<1> BCH's maximum ECC strength.
<2> the maximum chain delay in ns used by the EDO mode.
but we may add more information in future.
[2] add the gpmi_devdata_imx{23|28|6q} to replace the gpmi_ids.
[3] simplify the code by using the ECC strength from gpmi_devdata, such as
gpmi_check_ecc() and legacy_set_geometry();
[4] use the maximum chain delay to initialize the EDO mode,
see gpmi_compute_edo_timing().
[5] rewrite the macros, such GPMI_IS_MX{23|28|6Q}.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Sub page write doesn't work because of hw issue in controller found on
Keystone SOCs. AEMIF controller is also used on DaVinci SOCs which
don't seems to have any issue. So add "ti,keysone-nand" compatible
to nand driver in order to set NAND_NO_SUBPAGE_WRITE option.
Cc: Warner Losh <imp@bsdimp.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Now that the index variable is correctly set earlier in this function
we can use it in other places that compute the same thing too.
Signed-off-by: Ron Lee <ron@debian.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Commit 2c9f2365 (mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch4
in omap_calculate_ecc_bch) introduced minor compile warning
"‘erased_sector_bitflips’ defined but not used [-Wunused-function]" when
compiling without CONFIG_MTD_NAND_OMAP_BCH. Move function
erased_sector_bitflips() into the same ifdef section as the only caller.
Signed-off-by: Christian Engelmayer <cengelma@gmx.at>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
- A few SPI NOR ID definitions
- Kill the NAND "max pagesize" restriction
- Fix some x16 bus-width NAND support
- Add NAND JEDEC parameter page support
- DT bindings for NAND ECC
- GPMI NAND updates (subpage reads)
- More OMAP NAND refactoring
- New STMicro SPI NOR driver (now in 40 patches!)
- A few other random bugfixes
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJTP6x+AAoJEFySrpd9RFgtit0P/jLWsjMK8G2ldPC4bMZsXmDF
n3c71GcCRlUq4Qzb4rtZx9DANLAh+JyRrMOKCPg6dAMegFdmUqDOpZpNp0vF57KG
myFjqTk+n5y0tfSkWLMUFt0tQ8ArDp3IBkQCUWkD5LgG50EWmjveIQGH0kFnkE39
Kytqvw17RV7f81tIs+WvKt8++YWD2X1VTpTi0S4fx2bJ99bJDBf/GgdoQpj2oirt
igXmloUFEsob9JHZ3qumcUm9vaHwv2TiouZTvRyGdJCCoPdpJEZO4Ka6e4uAVarT
6kMKXBk3lj2GsilOSFFCNetXfy5Bf0TkJkv4rDjh3R1Y4J/hSgraVCbWXdKhb6tj
RmwesdFMjsyS4f/Rhk5PXwJgGL9uK2mi6bk/SmXU0AMgCDSa5zjshY8Wq6C6uXwk
LqlnK8l3h8Txotbc/XJIL+QGMbMkYQI8gxWTHFaqzDtkMe36mnGs9Zec3oso/s2d
CNRpq5+dMZ6qF0z3zpOQHmFbaOekivMy7kCKMXer6ONsrQBNwTdmkwy+SdqnWsLF
YdJttwV/RRcE0SRvK6GrhvzkGlV83Z8RPny6hC1kbrgQ0ffoy2CmIqyWNObK1RXf
sYqoF8TCtR6Y8rHHi5dzZ1lria+nm8pb4+UfQLRI0mK8og7YW+fIfHXxqRrZZIrt
No8NCPBKWzyew2UE0AiQ
=CKih
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20140405' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris:
- A few SPI NOR ID definitions
- Kill the NAND "max pagesize" restriction
- Fix some x16 bus-width NAND support
- Add NAND JEDEC parameter page support
- DT bindings for NAND ECC
- GPMI NAND updates (subpage reads)
- More OMAP NAND refactoring
- New STMicro SPI NOR driver (now in 40 patches!)
- A few other random bugfixes
* tag 'for-linus-20140405' of git://git.infradead.org/linux-mtd: (120 commits)
Fix index regression in nand_read_subpage
mtd: diskonchip: mem resource name is not optional
mtd: nand: fix mention to CONFIG_MTD_NAND_ECC_BCH
mtd: nand: fix GET/SET_FEATURES address on 16-bit devices
mtd: omap2: Use devm_ioremap_resource()
mtd: denali_dt: Use devm_ioremap_resource()
mtd: devices: elm: update DRIVER_NAME as "omap-elm"
mtd: devices: elm: configure parallel channels based on ecc_steps
mtd: devices: elm: clean elm_load_syndrome
mtd: devices: elm: check for hardware engine's design constraints
mtd: st_spi_fsm: Succinctly reorganise .remove()
mtd: st_spi_fsm: Allow loop to run at least once before giving up CPU
mtd: st_spi_fsm: Correct vendor name spelling issue - missing "M"
mtd: st_spi_fsm: Avoid duplicating MTD core code
mtd: st_spi_fsm: Remove useless consts from function arguments
mtd: st_spi_fsm: Convert ST SPI FSM (NOR) Flash driver to new DT partitions
mtd: st_spi_fsm: Move runtime configurable msg sequences into device's struct
mtd: st_spi_fsm: Supply the W25Qxxx chip specific configuration call-back
mtd: st_spi_fsm: Supply the S25FLxxx chip specific configuration call-back
mtd: st_spi_fsm: Supply the MX25xxx chip specific configuration call-back
...
These changes are mostly for ARM specific device drivers that either
don't have an upstream maintainer, or that had the maintainer ask
us to pick up the changes to avoid conflicts. A large chunk of this
are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from
that, reset controllers for STi as well as a large rework of the
Marvell Orion/EBU watchdog driver are notable.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAUz/1+GCrR//JCVInAQJmfg/9GyqHatDjjUPUBjUQRIEtKgGdmQwdbDqF
x+OrS/q5B5zYbpIWkbkt1IUYJfU+89Z5ev9jxI4rV824Nu9Y92mHPDnv+N/ptkIh
q2OVP3bQDpWs3aEVV2B1HBNcWrNUuwco9BJu05eegEePii/cto0/wKwWIgUmrmjy
xOLthsnp2YmeplGs7ctC6Dz8XbmELebpawejTGylARXei/SwmzB/YYDgJbYjRL2I
WSCVa8Vo+MZaGC/yxdKVTtvsKVQenxGoMO3ojikJeRdvuVRJds48Cw+UBdzWYNeJ
3Ssvbdx6Xltf9jy/7H0btOUgxPetZuUV+2XpbWfGu0Zr9FcGDv3q9hrxA+UYKnkY
GIGU0otSsmpHnX5Ms3E2xnHiV/fihxA3qohqts5kYRBDr5uc+IpW6SbDymQliCGG
OO4XmIVM3pmsqAqP3Zuseemt9CeSW2yC0XlfXkzjO74yY39c+WLBbtGI40Z5W6i0
mM1C8RD3QSNijYCEC8eqz06BQfRImsPs+jllsnJTZaHfbOsib718uvandjfG26lN
616YMcqq0Sp51HIQ4qW7f2dQr7vOyNqbukdkrwF5JgkY/nVki5kdciRg/yeipRy6
Ey80a+OTq0GQljM0F2dcH/A1eHH9KsuI1L6NdSMJsl0h6guIBORPTwTw3qJ13OkR
wpJyM+Gm+Fk=
=u/FI
-----END PGP SIGNATURE-----
Merge tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Arnd Bergmann:
"These changes are mostly for ARM specific device drivers that either
don't have an upstream maintainer, or that had the maintainer ask us
to pick up the changes to avoid conflicts.
A large chunk of this are clock drivers (bcm281xx, exynos, versatile,
shmobile), aside from that, reset controllers for STi as well as a
large rework of the Marvell Orion/EBU watchdog driver are notable"
* tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac."
Revert "net: stmmac: Add SOCFPGA glue driver"
ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks
ARM: STi: Add reset controller support to mach-sti Kconfig
drivers: reset: stih416: add softreset controller
drivers: reset: stih415: add softreset controller
drivers: reset: Reset controller driver for STiH416
drivers: reset: Reset controller driver for STiH415
drivers: reset: STi SoC system configuration reset controller support
dts: socfpga: Add sysmgr node so the gmac can use to reference
dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
reset: Add optional resets and stubs
ARM: shmobile: r7s72100: fix bus clock calculation
Power: Reset: Generalize qnap-poweroff to work on Synology devices.
dts: socfpga: Update clock entry to support multiple parents
ARM: socfpga: Update socfpga_defconfig
dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
net: stmmac: Add SOCFPGA glue driver
watchdog: orion_wdt: Use %pa to print 'phys_addr_t'
drivers: cci: Export CCI PMU revision
...
Commit 7351d3a5db added an index variable
as part of fixing checkpatch warnings, presumably as a tool to make some
long lines shorter, however it only set that index in the case of there
being no gaps in eccpos for the fragment being read. Which means the
later step of filling ecccode from oob_poi will use the wrong indexing
into eccpos in that case.
This patch restores the behaviour that existed prior to that change.
Signed-off-by: Ron Lee <ron@debian.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Here's the big char/misc driver updates for 3.15-rc1.
Lots of various things here, including the new mcb driver subsystem.
All of these have been in linux-next for a while.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iEYEABECAAYFAlM7ArIACgkQMUfUDdst+ylS+gCfcJr0Zo2v5aWnqD7rFtFETmFI
LhcAoNTQ4cvlVdxnI0driWCWFYxLj6at
=aj+L
-----END PGP SIGNATURE-----
Merge tag 'char-misc-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver patches from Greg KH:
"Here's the big char/misc driver updates for 3.15-rc1.
Lots of various things here, including the new mcb driver subsystem.
All of these have been in linux-next for a while"
* tag 'char-misc-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (118 commits)
extcon: Move OF helper function to extcon core and change function name
extcon: of: Remove unnecessary function call by using the name of device_node
extcon: gpio: Use SIMPLE_DEV_PM_OPS macro
extcon: palmas: Use SIMPLE_DEV_PM_OPS macro
mei: don't use deprecated DEFINE_PCI_DEVICE_TABLE macro
mei: amthif: fix checkpatch error
mei: client.h fix checkpatch errors
mei: use cl_dbg where appropriate
mei: fix Unnecessary space after function pointer name
mei: report consistently copy_from/to_user failures
mei: drop pr_fmt macros
mei: make me hw headers private to me hw.
mei: fix memory leak of pending write cb objects
mei: me: do not reset when less than expected data is received
drivers: mcb: Fix build error discovered by 0-day bot
cs5535-mfgpt: Simplify dependencies
spmi: pm: drop bus-level PM suspend/resume routines
spmi: pmic_arb: make selectable on ARCH_QCOM
Drivers: hv: vmbus: Increase the limit on the number of pfns we can handle
pch_phub: Report error writing MAC back to user
...
Passing a name to request_mem_region() isn't optional and can't just
be NULL. Passing NULL causes a NULL ptr deref later in the boot
process.
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
Tested-by: Alexander Shiyan <shc_work@mail.ru>
Cc: <stable@vger.kernel.org> # 3.14
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Mention to CONFIG_MTD_ECC_BCH in the warning message can be confusing as this
doesn't match the exact name of the configuration option.
This warning showed up once to me when I was starting to set up BCH. After
checking my .config file, it took a moment before realizing it is
CONFIG_MTD_NAND_ECC_BCH instead of CONFIG_MTD_ECC_BCH.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use devm_ioremap_resource() in order to make the code simpler,
and remove redundant return value check of platform_get_resource()
because the value is checked by devm_ioremap_resource(). Also,
'unsigned long mem_size' is removed from 'struct omap_nand_info',
because the 'mem_size' variable is not necessary anymore.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use devm_ioremap_resource() in order to make the code
simpler, and remove redundant return value check of
platform_get_resource_byname() because the value is
checked by devm_ioremap_resource().
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Tested-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
ELM hardware engine is used by BCH ecc-schemes for detecting and locating ECC
errors. This patch adds the following checks for ELM hardware engine:
- ELM internal buffers are of 1K,
so it cannot process data with ecc-step-size > 1K.
- ELM engine can execute upto maximum of 8 threads in parallel,
so in *page-mode* (when complete page is processed in single iteration),
ELM cannot support ecc-steps > 8.
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
'is_elm_present' flag is not used anywhere. This check is implicitely
taken care while selecting appropriate ecc-scheme via DT or board-file.
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch
- refactors GPMC configurations based on ecc-scheme
- removed dependency on is_elm_present() flag, which is implicitely
taken care by selecting appropriate ecc-scheme
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Lots of if..then..else conditions in omap_enable_hwecc_bch() can be avoided if
code is refactored based on ecc-scheme.
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch
- renames omap3_enable_hwecc_bch -> omap_enable_hwecc_bch to keep
nomenclature independent of any device family.
- using '__maybe_unused' instead of `ifdef based conditional compilation
to suppress warning for un-used functions
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
merge omap3_calculate_ecc_bch8() into omap_calculate_ecc_bch() so that
common callback can be used for both OMAP_ECC_BCH8_CODE_HW and
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+---------------------+-------------------------------------------------------+
|ecc-scheme | nand_chip->calculate() after this patch |
+---------------------+-------------------------------------------------------+
|HAM1_ECC | omap_calculate_ecc() |
+---------------------+-------------------------------------------------------+
|BCH4_HW_DETECTION_SW | omap_calculate_ecc_bch() |
|BCH4_HW | omap_calculate_ecc_bch() |
|BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8() -> omap_calculate_ecc_bch()|
|BCH8_HW | omap_calculate_ecc_bch() |
+---------------------+-------------------------------------------------------+
Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
merges omap3_calculate_ecc_bch4() into omap_calculate_ecc_bch() so that
common callback can be used for both OMAP_ECC_BCH4_CODE_HW and
OMAP_ECC_BCH4_CODE_HW_DETECTION_SW ecc-schemes
+---------------------+-------------------------------------------------------+
|ecc-scheme | nand_chip->calculate() after this patch |
+---------------------+-------------------------------------------------------+
|HAM1_ECC | omap_calculate_ecc() |
+---------------------+-------------------------------------------------------+
|BCH4_HW_DETECTION_SW | omap3_calculate_ecc_bch4() -> omap_calculate_ecc_bch()|
|BCH4_HW | omap_calculate_ecc_bch() |
|BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8() |
|BCH8_HW | omap_calculate_ecc_bch() |
+---------------------+-------------------------------------------------------+
Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
OMAP NAND driver supports multiple flavours of BCH4 and BCH8 ECC algorithms.
+------+------------------------------------+---------------+---------------+
| Algo | ECC scheme |ECC calculation|Error detection|
+------+------------------------------------+---------------+---------------+
| |OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W |
| BCH4 |OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) |
+------+------------------------------------+---------------+---------------+
| |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W |
| BCH8 |OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
+------+------------------------------------+---------------+---------------+
This patch refactors omap_calculate_ecc_bch() so that
- separate out ecc-scheme specific code so that common-code can be reused
between different implementations of same ECC algorithm.
- new ecc-schemes can be added with ease in future.
Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
rename omap3_calculate_ecc_bch -> omap_calculate_ecc_bch to
keep nomenclature independent of any device family.
Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch updates following checks when bit-flips are detected by ELM:
- Do not evaluate bit-flips when un-correctable bit-flips is reported by ELM,
because as per [1] when ELM reports an un-correctable bit-flips,
'number of error' field in its ELM_LOCATION_STATUS register is also invalid.
- Return with error-code '-EBADMSG' on detection of un-correctable bit-flip.
- Return with error-code '-EBADMSG' when bit-flips position is outside current
Sector and OOB area.
[1] ELM IP spec Table-25 ELM_LOCATION_STATUS Register.
ELM_LOCATION_STATUS[8] = ECC_CORRECTABLE: Error location process exit status
0x0: ECC error location process failed.
Number of errors and error locations are invalid.
0x1: all errors were successfully located.
Number of errors and error locations are valid.
Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Current omap_elm_correct_data() code is not scalable for future ecc-schemes
due to presence of tweaks and hard-coded macros for BCH4_ECC and BCH8_ECC
ecc-schemes at multiple places.
This patch:
- replaces 'ecc_opt' with '(info->nand.ecc.strength == BCH8_MAX_ERROR)
used to differentiate between BCH8_HW and BCH4_SW
- replaces macros (defining magic number for specific ecc-scheme) with
generic variables
- removes dependency on macros defined in elm.h (like BCHx_ECC_OOB_BYTES)
Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
As erased-pages do not have ECC stored in their OOB area, so they need to be
seperated out from programmed-pages, before doing BCH ECC correction.
In current implementation of omap_elm_correct_data() which does ECC correction
for BCHx ECC schemes, this erased-pages are detected based on specific marker
byte (reserved as 0x00) in ecc-layout.
However, this approach has some limitation like;
1) All ecc-scheme layouts do not have such Reserved byte marker to
differentiate between erased-page v/s programmed-page. Thus this is a
customized solution.
2) Reserved marker byte can itself be subjected to bit-flips causing
erased-page to be misunderstood as programmed-page.
This patch removes dependency on any marker byte in ecc-layout, instead it
compares calc_ecc[] with pattern of ECC-of-all(0xff). This implicitely
means that both 'data + oob == all(0xff).
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
renaming following variables as they cause confusion due to resemblence to
another similar field in 'struct nand_ecc_ctrl' (nand_chip->ecc.size).
renaming: ecc_vector_size --> ecc->bytes (info->nand.ecc.bytes)
renaming: eccsize --> actual_eccbytes (info->nand.ecc.bytes - 1) for BCH4 and BCH8
Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Information of currently selected ECC scheme 'enum omap_ecc ecc_opt' should
available outside platform-data, so that single nand_chip->ecc callback can
support multiple ecc-scheme configurations.
Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Crash detected on sam5d35 and its pmecc nand ecc controller.
The problem was a call to chip->ecc.hwctl from nand_write_subpage_hwecc
(nand_base.c) when we write a sub page.
chip->ecc.hwctl function is not set when we are using PMECC controller.
As a workaround, set NAND_NO_SUBPAGE_WRITE for PMECC controller in
order to disable sub page access in nand_write_page.
Signed-off-by: Herve Codina <Herve.CODINA@celad.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
1) Why add the subpage read support?
The page size of the nand chip becomes larger and larger, the imx6 has to
supports the 16K page or even bigger page. But sometimes, the upper layer only
needs a small part of the page, such as 512 bytes or less.
For example, ubiattach may only read 64 bytes per page.
2) We only enable the subpage read support when it meets the conditions:
<1> the chip is imx6 (or later chips) which can supports large nand page.
<2> the size of ECC parity is byte aligned.
If the size of ECC parity is not byte aligned, the calling of NAND_CMD_RNDOUT
will fail.
3) What does this patch do?
This patch will fake a virtual small page for the subpage read, and call the
gpmi_ecc_read_page() to do the real work.
In order to fake a virtual small page, the patch changes the BCH registers and
the bch_geometry{}. After the subpage read finished, we will restore them back.
4) Performace:
4.1) Tested with Toshiba TC58NVG2S0F(4096 + 224) with the following command:
#ubiattach /dev/ubi_ctrl -m 4
The detail information of /dev/mtd4 shows below:
--------------------------------------------------------------
#mtdinfo /dev/mtd4
mtd4
Name: test
Type: nand
Eraseblock size: 262144 bytes, 256.0 KiB
Amount of eraseblocks: 1856 (486539264 bytes, 464.0 MiB)
Minimum input/output unit size: 4096 bytes
Sub-page size: 4096 bytes
OOB size: 224 bytes
Character device major/minor: 90:8
Bad blocks are allowed: true
Device is writable: true
--------------------------------------------------------------
4.2) Before this patch:
--------------------------------------------------------------
[ 94.530495] UBI: attaching mtd4 to ubi0
[ 98.928850] UBI: scanning is finished
[ 98.953594] UBI: attached mtd4 (name "test", size 464 MiB) to ubi0
[ 98.958562] UBI: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes
[ 98.964076] UBI: min./max. I/O unit sizes: 4096/4096, sub-page size 4096
[ 98.969518] UBI: VID header offset: 4096 (aligned 4096), data offset: 8192
[ 98.975128] UBI: good PEBs: 1856, bad PEBs: 0, corrupted PEBs: 0
[ 98.979843] UBI: user volume: 1, internal volumes: 1, max. volumes count: 128
[ 98.985878] UBI: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 2024916145
[ 98.993635] UBI: available PEBs: 0, total reserved PEBs: 1856, PEBs reserved for bad PEB handling: 40
[ 99.001807] UBI: background thread "ubi_bgt0d" started, PID 831
--------------------------------------------------------------
The attach time is about 98.9 - 94.5 = 4.4s
4.3) After this patch:
--------------------------------------------------------------
[ 286.464906] UBI: attaching mtd4 to ubi0
[ 289.186129] UBI: scanning is finished
[ 289.211416] UBI: attached mtd4 (name "test", size 464 MiB) to ubi0
[ 289.216360] UBI: PEB size: 262144 bytes (256 KiB), LEB size: 253952 bytes
[ 289.221858] UBI: min./max. I/O unit sizes: 4096/4096, sub-page size 4096
[ 289.227293] UBI: VID header offset: 4096 (aligned 4096), data offset: 8192
[ 289.232878] UBI: good PEBs: 1856, bad PEBs: 0, corrupted PEBs: 0
[ 289.237628] UBI: user volume: 0, internal volumes: 1, max. volumes count: 128
[ 289.243553] UBI: max/mean erase counter: 1/1, WL threshold: 4096, image sequence number: 2024916145
[ 289.251348] UBI: available PEBs: 1812, total reserved PEBs: 44, PEBs reserved for bad PEB handling: 40
[ 289.259417] UBI: background thread "ubi_bgt0d" started, PID 847
--------------------------------------------------------------
The attach time is about 289.18 - 286.46 = 2.7s
4.4) The conclusion:
We achieve (4.4 - 2.7) / 4.4 = 38.6% faster in the ubiattach.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The nfc_geo->payload_size is equal to the mtd->writesize now,
use the nfc_geo->payload_size to replace the mtd->writesize.
This patch makes preparation for the gpmi's subpage read support.
In the subpage support, the nfc_geo->payload_size maybe smaller then
the mtd->writesize.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add the "page" argument for the read_subpage hook. With this argument,
the implementation of this hook could prints out more accurate information
for debugging.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The nand_get_flash_type parameter "busw" input value is not used by any
branch, and it is updated before use it in the function, so remove it,
define the "busw" as an internal variable.
Signed-off-by: Cai Zhiyong <caizhiyong@huawei.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The actual ECC strength used to select the ECC scheme is 'ecc_strength'.
Use it in the error message.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This macro is not used so it's safe to remove it.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Instead of writing to "nand->reg + REG_FMICSR" we write to "REG_FMICSR"
which is NULL and not a valid register.
Fixes: 8bff82cbc3 ('mtd: add nand support for w90p910 (v2)')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Check the chip->jedec_version, and print out the right information
for JEDEC compliant NAND.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch adds the parsing code for the JEDEC compliant NAND.
Since we need the 0x40 as the column address, this patch also
makes the NAND_CMD_PARAM to use the 8-bit address only.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Check the return value from platform_get_irq() and propagate it in the case of
error.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
PIO fall back is not an issue, so don't make this much noise.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
read_buf is called in place of write_buf in the
nand_write_page_raw_syndrome function.
Signed-off-by: Boris BREZILLON <b.brezillon.dev@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
On archs like S390 or um this driver cannot build nor work.
Make it depend on HAS_IOMEM and HAS_DMA to bypass build failures.
drivers/built-in.o: In function `flctl_probe':
drivers/mtd/nand/sh_flctl.c:1097: undefined reference to `devm_ioremap_resource'
drivers/built-in.o: In function `flctl_dma_fifo0_transfer':
drivers/mtd/nand/sh_flctl.c:368: undefined reference to `dma_map_single'
drivers/mtd/nand/sh_flctl.c:407: undefined reference to `dma_unmap_single'
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use a repeated read_byte() instead of read_buf(), since for x16 buswidth
devices, we need to avoid the upper I/O[16:9] bits. See the following
commit for reference:
commit 05f7835975
Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Date: Thu Dec 5 22:22:04 2013 +0100
mtd: nand: don't use {read,write}_buf for 8-bit transfers
Now, I think that all barriers to probing ONFI on x16 devices are
removed, so remove the check from nand_flash_detect_onfi().
Tested on 8-bit ONFI NAND (Micron MT29F32G08CBADAWP).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-By: Pekon Gupta <pekon@ti.com>
The NAND command helpers tend to automatically shift the column address
for x16 bus devices, since most commands expect a word address, not a
byte address. The Read ID command, however, expects an 8-bit address
(i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
0x20).
This fixes the column address for a few drivers which imitate the
nand_base defaults. Note that I don't touch sh_flctl.c, since it already
handles this problem slightly differently (note its comment "READID is
always performed using an 8-bit bus").
I have not tested this patch, as I only have x8 parts up for testing at
this point. Hopefully that can change soon...
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-By: Pekon Gupta <pekon@ti.com>
The datasheet does not tell us how to parse out the ID data,
so handle it as a full ID nand.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The patch converts the arrays to buffer pointers for nand_buffers{}.
The cafe_nand.c is the only NAND_OWN_BUFFERS user which allocates
nand_buffers{} itself.
This patch disables the DMA for nand_scan_ident, and restores the DMA
status after we finish the nand_scan_ident. This way, we can get page
size and OOB size and use them to allocate cafe->dmabuf.
Since the cafe_nand.c uses the NAND_ECC_HW_SYNDROME ECC mode, we do not
allocate the buffers for @ecccalc and @ecccode.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
None of these files are actually using any __init type directives
and hence don't need to include <linux/init.h>. Most are just a
left over from __devinit and __cpuinit removal, or simply due to
code getting copied from one driver to the next.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
[Brian: dropped one incorrect hunk]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
commit d2ae2e20fb ("driver/memory:Move
Freescale IFC driver to a common driver") introduces this build
regression into the mpc85xx_defconfig:
drivers/built-in.o: In function `fsl_ifc_nand_remove':
drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev'
drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev'
drivers/built-in.o: In function `fsl_ifc_nand_probe':
drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev'
drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev'
drivers/built-in.o: In function `match_bank':
drivers/mtd/nand/fsl_ifc_nand.c:1013: undefined reference to `convert_ifc_address'
drivers/built-in.o: In function `fsl_ifc_nand_probe':
drivers/mtd/nand/fsl_ifc_nand.c:1059: undefined reference to `fsl_ifc_ctrl_dev'
drivers/mtd/nand/fsl_ifc_nand.c:1080: undefined reference to `fsl_ifc_ctrl_dev'
drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev'
drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev'
make: *** [vmlinux] Error 1
This happens because there is nothing to descend us into the
drivers/memory directory in the mpc85xx_defconfig. It wasn't
selecting CONFIG_MEMORY. So we never built drivers/memory/fsl_ifc.o
and so we have nothing to link the above symbols against.
Since the goal of the original commit was to relocate the driver to
an arch independent location, it only makes sense to relocate the
Kconfig setting there as well. But that alone won't fix the build
failure; for that we ensure whoever selects FSL_IFC also selects MEMORY.
Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch excludes reserved-marker byte-position from oobfree->length
calculation. Thus all bytes from oobfree->offset till end of OOB are free.
CC: <stable@vger.kernel.org> # 3.13.x+
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
1) In current implementation, ecclayout->oobfree->offset is calculated with
respect to ecclayout->eccpos[0] which is incorrect because ECC bytes may not
be stored contiguously in OOB.
So, this patch calculates ecclayout->oobfree->offset with respect to last
ECC byte-position 'eccpos[ecclayout->eccbytes-1]'.
2) ECC layout of some ecc-schemes expects reserved-markers at specific eccpos[]
which should not be over-written by any file-system metadata.
So this patch aligns oobfree->offset taking into account of such markers.
CC: <stable@vger.kernel.org> # 3.13.x+
Tested-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The problem that the set timings code contains the call of Davinci
platform function davinci_aemif_setup_timing() which is not
accessible if kernel is built for another platform like Keystone.
The Keysone platform is going to use TI AEMIF driver.
If TI AEMIF is used we don't need to set timings and bus width.
It is done by AEMIF driver.
To get rid of davinci-nand driver dependency on aemif platform code
we moved aemif code to davinci platform.
The platform AEMIF code (aemif.c) has to be removed once Davinci
will be converted to DT and use ti-aemif.c driver.
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
[nsekhar@ti.com: fixed checkpatch error and a build breakage due to
missing include, rebased onto l2-mtd/master]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/memory
and fix the header file includes.
Also remove module_platform_driver() and instead call
platform_driver_register() from subsys_initcall() to make sure this module
has been loaded before MTD partition parsing starts.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Rename symbols, variables, functions and structure fields related do
the resume latency device PM QoS type so that it is clear where they
belong (in particular, to avoid confusion with the latency tolerance
device PM QoS type introduced by a subsequent changeset).
Update the PM QoS documentation to better reflect its current state.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Pull more powerpc bits from Ben Herrenschmidt:
"Here are a few more powerpc bits for this merge window. The bulk is
made of two pull requests from Scott and Anatolij that I had missed
previously (they arrived while I was away). Since both their branches
are in -next independently, and the content has been around for a
little while, they can still go in.
The rest is mostly bug and regression fixes, a small series of
cleanups to our pseries cpuidle code (including moving it to the right
place), and one new cpuidle bakend for the powernv platform. I also
wired up the new sched_attr syscalls"
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (37 commits)
powerpc: Wire up sched_setattr and sched_getattr syscalls
powerpc/hugetlb: Replace __get_cpu_var with get_cpu_var
powerpc: Make sure "cache" directory is removed when offlining cpu
powerpc/mm: Fix mmap errno when MAP_FIXED is set and mapping exceeds the allowed address space
powerpc/powernv/cpuidle: Back-end cpuidle driver for powernv platform.
powerpc/pseries/cpuidle: smt-snooze-delay cleanup.
powerpc/pseries/cpuidle: Remove MAX_IDLE_STATE macro.
powerpc/pseries/cpuidle: Make cpuidle-pseries backend driver a non-module.
powerpc/pseries/cpuidle: Use cpuidle_register() for initialisation.
powerpc/pseries/cpuidle: Move processor_idle.c to drivers/cpuidle.
powerpc: Fix 32-bit frames for signals delivered when transactional
powerpc/iommu: Fix initialisation of DART iommu table
powerpc/numa: Fix decimal permissions
powerpc/mm: Fix compile error of pgtable-ppc64.h
powerpc: Fix hw breakpoints on !HAVE_HW_BREAKPOINT configurations
clk: corenet: Adds the clock binding
powerpc/booke64: Guard e6500 tlb handler with CONFIG_PPC_FSL_BOOK3E
powerpc/512x: dts: add MPC5125 clock specs
powerpc/512x: clk: support MPC5121/5123/5125 SoC variants
powerpc/512x: clk: enforce even SDHC divider values
...
<<
Switch mpc512x to the common clock framework and adapt mpc512x
drivers to use the new clock driver. Old PPC_CLOCK code is
removed entirely since there are no users any more.
>>
The buffer pointer passed from the upper layer may points to
a buffer in the stack or a buffer allocated by vmalloc, and etc..
This patch adds more sanity check to this buffer.
After this patch, if we meet a buffer which is allocated by vmalloc or
a buffer in the stack, we will use our own DMA buffer @data_buffer_dma
to do the DMA operations. If the buffer is not the cases above, we will
map it for DMA operations directly.
Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The @data_buffer_dma buffer is used for non ECC read/write.
Currently, the length of the buffer is PAGE_SIZE, but the NAND chip may
has 8K page or 16K page. So we have to extend it for the large page NAND
chips.
The gpmi_alloc_dma_buffer will be called twice. The first time is to
allocate a temporary buffer for scanning the NAND chip; The second time
is to allocate a buffer to store the real page content.
This patch allocates a buffer of PAGE_SIZE size for scanning the NAND
chip when gpmi_alloc_dma_buffer is called the first time, and allocates a
buffer of the real NAND page size for the second time gpmi_alloc_dma_buffer
is called.
Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
plat/regs-nand.h is used only by S3C2410 nand driver. Since there
are no other users, merge this file into the driver code to remove
platform dependency. While at it also remove unused macros.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Remove unneeded error handling on the result of a call
to platform_get_resource() when the value is passed to
devm_ioremap_resource().
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Remove unneeded error handling on the result of a call
to platform_get_resource() when the value is passed to
devm_ioremap_resource(). And move those two call together
to make the connection between them more clear.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add the Intel manufacturer Id.
Tested with Intel JS29F32G08ACMD1(4096 + 224) which is ONFI 2.0 compliant
nand.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add the manufactor ID for SanDisk.
Make preparation for SanDisk SDTNRGAMA-008G.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Assume that:
tmp = ((extid >> 2) & 0x04) | (extid & 0x03));
From the K9LCG08U0B's datasheet, we know that:
the oob size is 640 when tmp is 6;
the oob size is 1024 when tmp is 7;
Signed-off-by: Huang Shijie <b32955@freescale.com>
[Brian: fixed compile issue]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit adds support for devices with 2048B page sizes and
4-bit ECC strength requirements. This is achieved by enabling the BCH
ECC engine, which provides a higher strength: 16-bit over 2048 bytes.
Additionally, add a proper ECC layout to model the controller's view
of the device (where 'U' means unused and 'B' is the bad block marker):
----------------------------------------------------
| 2048B data | B | B | 30B spare | 30B ECC | U | U |
----------------------------------------------------
Signed-off-by: Rodolfo Giometti <giometti@linux.it>
[Brian: updated with Ezequiel's patch description]
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
According to the Open NAND Flash Interface Specification (ONFI) Revision
3.1 "Parameters are always transferred on the lower 8-bits of the data
bus." for the Get Features and Set Features commands.
So using read_buf and write_buf is wrong for 16-bit wide nand chips as
they use I/O[15:0]. The Get Features command is easily fixed using 4
times the read_byte callback. For Set Features implement a new
overwritable callback "write_byte". Still I expect the default to work
just fine for all controllers and making it overwriteable was just done
for symmetry.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
[Brian: fixed warning]
Tested-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Micron provides READ RETRY support via the ONFI vendor-specific
parameter block (to indicate how many read-retry modes are available)
and the ONFI {GET,SET}_FEATURES commands with a vendor-specific feature
address (to support reading/switching the current read-retry mode).
The recommended sequence is as follows:
1. Perform PAGE_READ operation
2. If no ECC error, we are done
3. Run SET_FEATURES with feature address 89h, mode 1
4. Retry PAGE_READ operation
5. If ECC error and there are remaining supported modes, increment the
mode and return to step 3. Otherwise, this is a true ECC error.
6. Run SET_FEATURES with feature address 89h, mode 0, to return to the
default state.
This patch implements the chip->setup_read_retry() callback for
Micron and fills in the chip->read_retries.
Tested on Micron MT29F32G08CBADA, which supports 8 read-retry modes.
The Micron vendor-specific table was checked against the datasheets for
the following Micron NAND:
Needs retry Cell-type Part number Vendor revision Byte 180
----------- --------- ---------------- --------------- ------------
No SLC MT29F16G08ABABA 1 Reserved (0)
No MLC MT29F32G08CBABA 1 Reserved (0)
No SLC MT29F1G08AACWP 1 0
Yes MLC MT29F32G08CBADA 1 08h
Yes MLC MT29F64G08CBABA 2 08h
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com>
Modern MLC (and even SLC?) NAND can experience a large number of
bitflips (beyond the recommended correctability capacity) due to drifts
in the voltage threshold (Vt). These bitflips can cause ECC errors to
occur well within the expected lifetime of the flash. To account for
this, some manufacturers provide a mechanism for shifting the Vt
threshold after a corrupted read.
The generic pattern seems to be that a particular flash has N read retry
modes (where N = 0, traditionally), and after an ECC failure, the host
should reconfigure the flash to use the next available mode, then retry
the read operation. This process repeats until all bitfips can be
corrected or until the host has tried all available retry modes.
This patch adds the infrastructure support for a
vendor-specific/flash-specific callback, used for setting the read-retry
mode (i.e., voltage threshold).
For now, this patch always returns the flash to mode 0 (the default
mode) after a successful read-retry, according to the flowchart found in
Micron's datasheets. This may need to change in the future if it is
determined that eventually, mode 0 is insufficient for the majority of
the flash cells (and so for performance reasons, we should leave the
flash in mode 1, 2, etc.).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com>
ECC failures can be tracked at the page level, not the do_read_ops level
(i.e., a potentially multi-page transaction).
This helps prepare for READ RETRY support.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com>
Now that the driver can support the Armada 370/XP SoC NAND controller,
add the devicetree compatible string, enabling its use.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
after device tree based clock lookup became available, the NAND
flash driver need no longer use the previous global "nfc_clk" name,
but should use the "ipg" clock name specific to the OF node
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This patch kills the NAND_MAX_PAGESIZE/NAND_MAX_OOBSIZE by the following
way:
1.) change the @buf field of nand_buf{} from an array to a pointer.
also remove the DENALI_BUF_SIZE macro.
2.) Before we call the nand_scan_ident, we allocate a temporary buffer
whose size is PAGE_SIZE.
3.) After we finish the nand_scan_ident, we have already getten the
page size and oob size. We will allocate the right buffer size
again.
Signed-off-by: Huang Shijie <shijie8@gmail.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We kill the NAND_MAX_PAGESIZE/NAND_MAX_OOBSIZE by the following way:
1.) Before we call the nand_scan_ident, we allocate a temporary buffer
whose size is PAGE_SIZE.
2.) After we finish the nand_scan_ident, we have already getten the
page size and oob size. We will allocate the right buffer size
again.
Signed-off-by: Huang Shijie <shijie8@gmail.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
mtd.name is assigned to IFC NAND physical address. Assignment type is u32.
It is not providing correct physical address of IFC NAND.
Update assignment type to u64.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch assigned the type->name to mtd->name when mtd->name is
NULL in function "find_full_id_nand".
mtd->name is NULL may cause some problem.
Signed-off-by: Cai Zhiyong <caizhiyong@huawei.com>
Acked-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The kernel already has this information, and individual drivers
shouldn't duplicate that. This also eliminates the use of __DATE__ and
__TIME__, which make the build non-deterministic.
Signed-off-by: Josh Triplett <josh@joshtriplett.org>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The omap_{read,write}_buf{8,16}() functions are identical to the default
nand_base versions. Just let nand_base assign them in the
NAND_OMAP_POLLED case.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Pekon Gupta <pekon@ti.com>
We shouldn't try to allocate a resource until we're sure the
of_property_read_u64() call didn't fail. This is especially important if
we use this code for both CONFIG_OF and !CONFIG_OF builds, since
of_property_read_u64() will always return -ENOSYS for !CONFIG_OF.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use devm_*() functions to make cleanup paths simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use dev_err() instead of printk() to provide a better message
to userspace.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use dev_err() instead of printk() to provide a better message
to userspace.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use dev_warn() instead of printk() to provide a better message
to userspace.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use dev_err() instead of printk() to provide a better message
to userspace.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Roland Stigge <stigge@antcom.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Roland Stigge <stigge@antcom.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use devm_*() functions to make cleanup paths simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use devm_*() functions to make cleanup paths simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use devm_*() functions to make cleanup paths simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Roland Stigge <stigge@antcom.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use devm_clk_get() to make cleanup paths simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In order to avoid code duplication, let's consolidate the ECC setting
for all SoC variants. Such decision is based on page size and ECC
strength requirements.
Also, provide a default value for the case where such ECC information
is not provided (non-ONFI devices).
Tested-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Currently, we have two different cmdfunc's implementations:
one for PXA3xx SoC variant and one for Armada 370/XP SoC variant.
The former is the legacy one, typically constrained to devices
with page sizes smaller or equal to the controller's FIFO buffer.
On the other side, the latter _only_ supports the so-called extended
command semantics, which allow to handle devices with larger
page sizes (4 KiB, 8 KiB, ...).
This means we currently don't support devices with smaller pages on the
A370/XP SoC. Fix it by first renaming the cmdfuncs variants, and then
make the choice based on device page size (and SoC variant), rather than
SoC variant alone.
While at it, add a check for page size, to make sure we don't allow larger
pages sizes on the PXA3xx variant.
Tested-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Currently the driver assumes all commands will eventually trigger a RnB
transition, and thus a "device is ready" IRQ.
This assumption means that on every issued command, the dev_ready completion
handler is init'ed and the need_wait flag is set.
However this is incorrect: some commands (such as NAND_CMD_STATUS) don't
make the device 'busy' and thus a RnB transition never occurs.
Given, the NAND core never calls waitfunc() after such commands, this
is not a problem.
Therefore, it's possible to only clear the need_wait flag on every command
that is started.
This fixes a current bug that can be reproduced on PXA boards by writing
blank (all 0xff'ed) to a page:
1. The kernel issues NAND_CMD_STATUS and sets need_wait=1. The flag
won't be cleared for this command since no RnB transition is
involved.
2. NAND_CMD_PAGEPROG is issued but since the data is blank, the driver
decides not to execute the command (and no IRQ activity is
involved).
3. The NAND core calls waitfunc() and waits for the dev_ready
completion, which will never end since the device _is_ already ready.
Tested-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch marks the function is_erased() as static in denali.c because
it is not used outside this file.
This patch elimiates the following warning in nand/denali.c:
drivers/mtd/nand/denali.c:900:6: warning: no previous prototype for ‘is_erased’ [-Wmissing-prototypes]
Signed-off-by: Rashika Kheria <rashika.kheria@gmail.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This driver doesn't need its own custom chip->write_page callback; the
only "custom" requirement is that this driver does not support subpage
writes, which we can avoid using the NAND_NO_SUBPAGE_WRITE flag. With
NAND_NO_SUBPAGE_WRITE, the default routine (nand_write_page()) should
perform the equivalent operations.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Roland Stigge <stigge@antcom.de>
Tested-by: Roland Stigge <stigge@antcom.de>
The TI AEMIF driver registers are used to setup timings for each chip
select. The same registers range is used to setup NAND settings.
The AEMIF and NAND drivers not use the same registers in this range.
In case with TI AEMIF driver, the memory address range is requested
already by AEMIF, so we cannot request it twice, just ioremap.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The Keystone arch has compatible nand device, so reuse it.
In case with Keystone it depends on TI_AEMIF because AEMIF
driver is responsible to set timings.
See http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The properties davinci-ecc-mode, davinci-nand-use-bbt, davinci-nand-buswidth
are MTD generic. Correct names for them are: nand-ecc-mode, nand-on-flash-bbt,
nand-bus-width accordingly. So rename them in dts and documentation.
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
There is not needed to use a lot of names for err handling.
It complicates code support and reading.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The property "ti,davinci-chipselect" is required. So we have to check
if it is set.
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In case when memory allocation is failed the driver should return
ENOMEM instead of ENODEV.
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
When kernel is booted using DT, there is no guarantee that Davinci
NAND device has been created already at the time when driver init
function is executed. Therefore, platform_driver_probe() can't be used
because this may result the Davinci NAND driver will never be probed.
The driver probing has to be made with core mechanism.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
clock source is prepared and enabled by clk_prepare_enable() in
mxcnd_probe() function, but no disable/unprepare in mxcnd_remove().
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Since the of_mtd header provides dummy stubs for !CONFIG_OF, it's safe
to remove the #ifdef CONFIG_OF. Build tested only.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Don't use DEFINE_PCI_DEVICE_TABLE macro, because this macro
is not preferred.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cast pointers to uintptr_t instead of unsigned int. This fixes warnings
on platforms where pointers have a different size than int.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: linux-mtd@lists.infradead.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add a nice "nand:" prefix to all pr_xxx() messages. This allows
to get rid of the "NAND" words in messages, given the context
is already given by the prefix.
Remove the __func__ report from messages where it's not needed and refactor
the device detection messages to show itself in several lines.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
clk_prepare_enable() may fail, so let's check its return value and propagate it
in the case of error.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The ecc_stats.corrected count variable will already be incremented in
the above framework-layer just after this callback.
Cc: stable@vger.kernel.org # 2.6.36+
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The devm_request_irq function allocates irq that is released
when a driver detaches. Thus, there is no reason to explicitly
call devm_free_irq in probe or remove functions.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
There are pr_err and dev_err in the gpmi driver now.
It makes people confused.
This patch changes all the pr_err to dev_err except the one
in the gpmi_reset_block(). We also remove the unnecessary
print for OOM message.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The error messages for the failure of dmaengine_prep_slave_sg are
not necessary, this patch removes all these pr_err, and returns with
the proper error code -EINVAL, not -1.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch adds request_mem_region() prior ioremap() for diskonchip
driver. This will allow to check if memory region is occupied by any
other device, for example in case if we have memory region for several
optional devices and only one device can be used at once.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use devm_request_irq to simplify the code.
Also remove the unused fields of structure resources{}.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use the devm_ioremap_resource to simplify the code.
[Note: as a side effect, this adds a missing call to request_memory().]
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The gpmi_nfc_* is the legacy name. In order to avoid the confusion,
The patch renames the gpmi_nfc_* functions to gpmi_nand_*.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We do not use the chip->oob_poi in the mx23_write_transcription_stamp.
So remove the unused line.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We do not scan the BBT after we call the gpmi_pre_bbt_scan,
so it has lost the meaning of existence.
This patch merges this function into gpmi_init_last, and delete it.
This patch does not change any logic.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The local array feature[] is in the stack. We can see the warning
when we enable the CONFIG_DMA_API_DEBUG:
----------------------------------------------------------
WARNING: at lib/dma-debug.c:950 check_for_stack+0xac/0xf8()
gpmi-nand 112000.gpmi-nand: DMA-API: device driver maps memory fromstack [addr=dc05be34]
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.17-16851-g2414a73 #1324
[<80014cbc>] (unwind_backtrace+0x0/0x138) from [<8001251c>] (show_stack+0x10/0x14)
[<8001251c>] (show_stack+0x10/0x14) from [<8002699c>] (warn_slowpath_common+0x4c/0x68)
[<8002699c>] (warn_slowpath_common+0x4c/0x68) from [<80026a4c>] (warn_slowpath_fmt+0x30/0x40)
[<80026a4c>] (warn_slowpath_fmt+0x30/0x40) from [<8028e2f8>] (check_for_stack+0xac/0xf8)
[<8028e2f8>] (check_for_stack+0xac/0xf8) from [<8028e438>] (debug_dma_map_sg+0xf4/0x188)
[<8028e438>] (debug_dma_map_sg+0xf4/0x188) from [<803968d0>] (prepare_data_dma+0xb8/0x1a8)
[<803968d0>] (prepare_data_dma+0xb8/0x1a8) from [<80397b20>] (gpmi_send_data+0x84/0xfc)
[<80397b20>] (gpmi_send_data+0x84/0xfc) from [<8038c2b4>] (nand_onfi_set_features+0x50/0x74)
[<8038c2b4>] (nand_onfi_set_features+0x50/0x74) from [<80397198>] (gpmi_extra_init+0x90/0x170)
[<80397198>] (gpmi_extra_init+0x90/0x170) from [<8039520c>] (gpmi_nand_probe+0x2f8/0xb3c)
[<8039520c>] (gpmi_nand_probe+0x2f8/0xb3c) from [<8031b974>] (platform_drv_probe+0x18/0x1c)
----------------------------------------------------------
The patch uses the kzalloc to allocate the buffer, and free it when
we do not use it anymore.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The Armada BCH configuration in this driver uses one of the two
following ECC schemes:
16-bit correction per 2048 bytes
16-bit correction per 1024 bytes
These are sufficient for mapping to the 4-bit per 512-bytes and 8-bit
per 512-bytes (respectively) minimum correctability requirements of many
common NAND.
The current code only checks for the required strength (4-bit or 8-bit)
without checking the ECC step size that is associated with that strength
(and simply assumes it is 512). While that is often a safe assumption to
make, let's make it explicit, since we have that information.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
This commit extends the ECC correctable error detection to include
ECC BCH errors. The number of BCH correctable errors can be any up to 16,
and the actual value is exposed in the NDSR register.
Therefore, we change some symbol names to refer to correctable or
uncorrectable (instead of single-bit or double-bit as it was in the
Hamming case) and while at it, cleanup the detection code slightly.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit adds write support for large pages (4 KiB, 8 KiB).
Such support is implemented by issuing a multiple command sequence,
transfering a set of 2 KiB chunks per transaction.
The splitted command sequence requires to send the SEQIN command
independently of the PAGEPROG command and therefore it's set as
an execution command.
Since PAGEPROG enables ECC, each 2 KiB chunk of data is written
together with ECC code at a controller-fixed location within
the flash page.
Currently, only devices with a 4 KiB page size has been tested.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
As preparation work to fully support large pages, this commit adds
the initial infrastructure to support splitted (aka chunked) I/O
operation. This commit adds support for read, and follow-up patches
will add write support.
When a read (aka READ0) command is issued, the driver loops issuing
the same command until all the requested data is transfered, changing
the 'extended' command field as needed.
For instance, if the driver is required to read a 4 KiB page, using a
chunk size of 2 KiB, the transaction is splitted in:
1. Monolithic read, first 2 KiB page chunk is read
2. Last naked read, second and last 2KiB page chunk is read
If ECC is enabled it is calculated on each chunk transfered and added
at a controller-fixed location after the data chunk that must be
spare area.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In preparation to support multiple (aka chunked, aka splitted)
page I/O, this commit adds 'data_buff_pos' and 'oob_buff_pos' fields
to keep track of where the next read (or write) should be done.
This will allow multiple calls to handle_data_pio() to continue
the read (or write) operation.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit adds support page programming with a non-zero "column"
address setting. This is important to support OOB writing, through
command sequences such as:
cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, ofs);
write_buf(mtd, oob_buf, 6);
cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
To allow future support of multiple page reading/writing, move the data
buffer clean out of prepare_set_command().
This is done to prevent the data buffer from being cleaned on every command
preparation, when a multiple command sequence is implemented to read/write
pages larger than the FIFO size (2 KiB).
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit splits the prepare_command_pool() function into two
stages: prepare_start_command() / prepare_set_command().
This is a preparation patch without any functionality changes,
and is meant to allow support for multiple page reading/writing
operations.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
READ0 and READOOB command preparation has a falltrough to SEQIN
case, where the command address is specified.
This is certainly confusing and makes the code less readable with
no added value. Let's remove it.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Let's simplify the code by first introducing a helper function
to set the page address, as done by the READ0, READOOB and SEQIN
commands.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Command buffer #3 is not properly cleared and it keeps the last
set value. Fix this by clearing when a command is setup.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit adds the BCH ECC support available in NFCv2 controller.
Depending on the detected required strength the respective ECC layout
is selected.
This commit adds an empty ECC layout, since support to access large
pages is first required. Once that support is added, a proper ECC
layout will be added as well.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add support for flash-based bad block table using Marvell's
custom in-flash bad block table layout. The support is enabled
a 'flash_bbt' platform data or device tree parameter.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In pxa3xx_nand_sensing() instead of simply using info->is_ready
after issuing a command, the correct way of checking is to wait
for the device to be ready through the chip's waitfunc().
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The expected behavior of the waitfunc() NAND chip call is to wait
for the device to be READY (this is a standard chip line).
However, the current implementation does almost nothing, which opens
the possibility of issuing a command to a non-ready device.
Fix this by adding a new completion to wait for the ready event to arrive.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add a comment clarifying the use of pxa3xx_set_datasize() which is only
applicable on data read/write commands (i.e. commands with a data cycle,
such as READID, READ0, STATUS, etc.)
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
There's no need to privately store the device page size as it's
available in mtd structure field mtd->writesize.
Also, this removes the hardcoded page size value, leaving the
auto-detected value only.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Introduce a fifo_size field to represent the size of the controller's
FIFO buffer, and use it to distinguish that size from the amount
of data bytes to be read from the FIFO.
This is important to support devices with pages larger than the
controller's internal FIFO, that need to read the pages in FIFO-sized
chunks.
In particular, the current code is at least confusing, for it mixes
all the different sizes involved: FIFO size, page size and data size.
This commit starts the cleaning by removing the info->page_size field
that is not currently used. The host->page_size field should also
be removed and use always mtd->writesize instead. Follow up commits
will clean this up.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Whenever possible, it's always better to use the generic chip->cmdfunc
instead of the internal pxa3xx_nand_cmdfunc().
In this particular case, this will allow to have multiple cmdfunc()
implementations for different SoC variants.
Reviewed-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In order to customize early settings depending on the detected SoC variant,
move the detection to be before the nand_chip struct filling.
In a follow-up patch, this change is needed to detect the variant *before*
the call to alloc_nand_resource(), which allows to set a different cmdfunc()
for each variant.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
As per the ecc.read_page() prototype, we must return the maximum number
of bitflips that were corrected on any one region covering an ecc step.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The current driver doesn't support sub-page writing, so report
that to the NAND core.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Since we have now support for the NFCv2 controller found on
Armada 370/XP platforms.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Given there's no public specification to this date, and in order
to capture some important details and singularities about the
controller let's document them once and for good.
Cc: linux-doc@vger.kernel.org
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix the following checkpatch warnings:
WARNING: line over 80 characters
#268: FILE: mtd/nand/gpmi-nand/gpmi-lib.c:268:
+ * consecutive reboots. The latter case has not been seen on the MX23 yet,
WARNING: space prohibited before semicolon
#356: FILE: mtd/nand/gpmi-nand/gpmi-lib.c:356:
+ (target.tRHOH_in_ns >= 0) ;
WARNING: space prohibited before semicolon
#1006: FILE: mtd/nand/gpmi-nand/gpmi-lib.c:1006:
+ BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Using devm_clk_get() can make the code smaller and cleaner.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In default way, we use the ecc_strength/ecc_step size calculated by ourselves
and use all the OOB area.
This patch adds a new property : "fsl,use-minimum-ecc"
If we enable it, we will firstly try to use the datasheet's minimum required
ECC provided by the MTD layer (the ecc_strength_ds/ecc_step_ds fields
in the nand_chip{}). So we may have free space in the OOB area by using the
minimum ECC, and we may support JFFS2 with some SLC NANDs, such as Micron's
SLC NAND.
If we fail to use the minimum ECC, we will use the legacy method to calculate
the ecc_strength and ecc_step size.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This option does not need to depend in MTD_NAND, for it's enclosed
under it. Also, it's wrong to make it depend in ARCH_OMAP3 only
since the controller is used in a wider range of SoCs.
Instead, just leave the dependency on the OMAP2 driver option.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In commit:
commit 62e8b85178
Author: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Date: Fri Oct 4 15:30:38 2013 -0300
mtd: nand: pxa3xx: Allocate data buffer on detected flash size
the way the buffer is allocated was changed: the first READ_ID is issued
with a small kmalloc'ed buffer. Only once the flash page size is detected
the DMA buffers are allocated, and info->use_dma is set.
Currently, if the device detection fails, the driver checks the 'use_dma'
module parameter and tries to release unallocated DMA resources.
Fix this by checking the proper indicator of the DMA allocation, which
is 'info->use_dma'.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This partially reverts c0f3b8643a.
The "armada370-nand" compatible support is not complete, and it was mistake
to add it. Revert it and postpone the support until the infrastructure is
in place.
Cc: <stable@vger.kernel.org> # 3.12
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Pull slave-dmaengine changes from Vinod Koul:
"This brings for slave dmaengine:
- Change dma notification flag to DMA_COMPLETE from DMA_SUCCESS as
dmaengine can only transfer and not verify validaty of dma
transfers
- Bunch of fixes across drivers:
- cppi41 driver fixes from Daniel
- 8 channel freescale dma engine support and updated bindings from
Hongbo
- msx-dma fixes and cleanup by Markus
- DMAengine updates from Dan:
- Bartlomiej and Dan finalized a rework of the dma address unmap
implementation.
- In the course of testing 1/ a collection of enhancements to
dmatest fell out. Notably basic performance statistics, and
fixed / enhanced test control through new module parameters
'run', 'wait', 'noverify', and 'verbose'. Thanks to Andriy and
Linus [Walleij] for their review.
- Testing the raid related corner cases of 1/ triggered bugs in
the recently added 16-source operation support in the ioatdma
driver.
- Some minor fixes / cleanups to mv_xor and ioatdma"
* 'next' of git://git.infradead.org/users/vkoul/slave-dma: (99 commits)
dma: mv_xor: Fix mis-usage of mmio 'base' and 'high_base' registers
dma: mv_xor: Remove unneeded NULL address check
ioat: fix ioat3_irq_reinit
ioat: kill msix_single_vector support
raid6test: add new corner case for ioatdma driver
ioatdma: clean up sed pool kmem_cache
ioatdma: fix selection of 16 vs 8 source path
ioatdma: fix sed pool selection
ioatdma: Fix bug in selftest after removal of DMA_MEMSET.
dmatest: verbose mode
dmatest: convert to dmaengine_unmap_data
dmatest: add a 'wait' parameter
dmatest: add basic performance metrics
dmatest: add support for skipping verification and random data setup
dmatest: use pseudo random numbers
dmatest: support xor-only, or pq-only channels in tests
dmatest: restore ability to start test at module load and init
dmatest: cleanup redundant "dmatest: " prefixes
dmatest: replace stored results mechanism, with uniform messages
Revert "dmatest: append verify result to results"
...
Pull dmaengine changes from Dan
1/ Bartlomiej and Dan finalized a rework of the dma address unmap
implementation.
2/ In the course of testing 1/ a collection of enhancements to dmatest
fell out. Notably basic performance statistics, and fixed / enhanced
test control through new module parameters 'run', 'wait', 'noverify',
and 'verbose'. Thanks to Andriy and Linus for their review.
3/ Testing the raid related corner cases of 1/ triggered bugs in the
recently added 16-source operation support in the ioatdma driver.
4/ Some minor fixes / cleanups to mv_xor and ioatdma.
Conflicts:
drivers/dma/dmatest.c
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Pull trivial tree updates from Jiri Kosina:
"Usual earth-shaking, news-breaking, rocket science pile from
trivial.git"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (23 commits)
doc: usb: Fix typo in Documentation/usb/gadget_configs.txt
doc: add missing files to timers/00-INDEX
timekeeping: Fix some trivial typos in comments
mm: Fix some trivial typos in comments
irq: Fix some trivial typos in comments
NUMA: fix typos in Kconfig help text
mm: update 00-INDEX
doc: Documentation/DMA-attributes.txt fix typo
DRM: comment: `halve' -> `half'
Docs: Kconfig: `devlopers' -> `developers'
doc: typo on word accounting in kprobes.c in mutliple architectures
treewide: fix "usefull" typo
treewide: fix "distingush" typo
mm/Kconfig: Grammar s/an/a/
kexec: Typo s/the/then/
Documentation/kvm: Update cpuid documentation for steal time and pv eoi
treewide: Fix common typo in "identify"
__page_to_pfn: Fix typo in comment
Correct some typos for word frequency
clk: fixed-factor: Fix a trivial typo
...
Use this new function to make code more comprehensible, since we are
reinitialzing the completion, not initializing.
[akpm@linux-foundation.org: linux-next resyncs]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13)
Cc: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Unify some compile-time differences so that we have fewer uses of
#ifdef CONFIG_OF in atmel_nand
* Other general cleanups (removing unused functions, options, variables,
fields; use correct interfaces)
* Fix BUG() for new odd-sized NAND, which report non-power-of-2 dimensions via
ONFI
* Miscellaneous driver fixes (SPI NOR flash; BCM47xx NAND flash; etc.)
* Improve differentiation between SLC and MLC NAND -- this clarifies an ABI
issue regarding the MTD "type" (in sysfs and in ioctl(MEMGETINFO)), where
the MTD_MLCNANDFLASH type was present but inconsistently used
* Extend GPMI NAND to support multi-chip-select NAND for some platforms
* Many improvements to the OMAP2/3 NAND driver, including an expanded DT
binding to bring us closer to mainline support for some OMAP systems
* Fix a deadlock in the error path of the Atmel NAND driver probe
* Correct the error codes from MTD mmap() to conform to POSIX and the Linux
Programmer's Manual. This is an acknowledged change in the MTD ABI, but I
can't imagine somebody relying on the non-standard -ENOSYS error code
specifically. Am I just being unimaginative? :)
* Fix a few important GPMI NAND bugs (one regression from 3.12 and one
long-standing race condition)
* More? Read the log!
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJSgzYRAAoJEFySrpd9RFgtv8EP/3ZIS1w4fHyWafVSdgVFGR0Y
urlVDhg7iBauh9admN9xxBz6CYRwhjby8GnN87Q1qzu95Xp63RVx31nNfdBW3DGd
92vSyskijYJcUtanBxYqGp1i3EbQcpF4mumqxnre3C4KTLNije41t/wNVqnXAstU
DWho2iymZdkweKJ0DqBA7WF4l/YscdFyNDanO9JWiwII05Rh3Acv7FPMFm3Clblw
Nvfwzgp4XycYMeIQtkmQgQ3GgeWtxPgQwqMofn97MVH4zeTsmUP317ohIMukLGJD
db33J2xBdrIbk9P4D3RvjOCYyAyonu9y6/p+B1Vmj+R4CAUvQOIljhklHFoT3UZW
OzUHPxB6T0+NZyQ/5IRQIYH9As++vdb/bzsUXm/cXceI4o4I0QCPy/8adifakBOF
IUX9/BCdUOfKXvdOXY5dXMR2sY1IBg/1WfI+qcAoITsS/EVrUTrOcfSLyGqF0ERU
c7mAzXiyp4D51x66/QnfJ4aJjlioQSoa3mK1j4fXqH08YB5Zclpz938Bo1AO3lWy
/n+NYSbeXJoi4rVkNawjrRVs+0OTby2XQ5OqBlUMH6f30fqjUefPm66ZBMhbxzYu
5QFDctUbnHCyAPpOtM/WR3/NOkIqVhQl1331A+dG2TzLK0vTHs+kbt/YmIITpjI+
yn70XJGhk1F4gy8zhD+V
=z5qO
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20131112' of git://git.infradead.org/linux-mtd
Pull MTD changes from Brian Norris:
- Unify some compile-time differences so that we have fewer uses of
#ifdef CONFIG_OF in atmel_nand
- Other general cleanups (removing unused functions, options,
variables, fields; use correct interfaces)
- Fix BUG() for new odd-sized NAND, which report non-power-of-2
dimensions via ONFI
- Miscellaneous driver fixes (SPI NOR flash; BCM47xx NAND flash; etc.)
- Improve differentiation between SLC and MLC NAND -- this clarifies an
ABI issue regarding the MTD "type" (in sysfs and in the MEMGETINFO
ioctl), where the MTD_MLCNANDFLASH type was present but
inconsistently used
- Extend GPMI NAND to support multi-chip-select NAND for some platforms
- Many improvements to the OMAP2/3 NAND driver, including an expanded
DT binding to bring us closer to mainline support for some OMAP
systems
- Fix a deadlock in the error path of the Atmel NAND driver probe
- Correct the error codes from MTD mmap() to conform to POSIX and the
Linux Programmer's Manual. This is an acknowledged change in the MTD
ABI, but I can't imagine somebody relying on the non-standard -ENOSYS
error code specifically. Am I just being unimaginative? :)
- Fix a few important GPMI NAND bugs (one regression from 3.12 and one
long-standing race condition)
- More? Read the log!
* tag 'for-linus-20131112' of git://git.infradead.org/linux-mtd: (98 commits)
mtd: gpmi: fix the NULL pointer
mtd: gpmi: fix kernel BUG due to racing DMA operations
mtd: mtdchar: return expected errors on mmap() call
mtd: gpmi: only scan two chips for imx6
mtd: gpmi: Use devm_kzalloc()
mtd: atmel_nand: fix bug driver will in a dead lock if no nand detected
mtd: nand: use a local variable to simplify the nand_scan_tail
mtd: nand: remove deprecated IRQF_DISABLED
mtd: dataflash: Say if we find a device we don't support
mtd: nand: omap: fix error return code in omap_nand_probe()
mtd: nand_bbt: kill NAND_BBT_SCANALLPAGES
mtd: m25p80: fixup device removal failure path
mtd: mxc_nand: Include linux/of.h header
mtd: remove duplicated include from mtdcore.c
mtd: m25p80: add support for Macronix mx25l3255e
mtd: nand: omap: remove selection of BCH ecc-scheme via KConfig
mtd: nand: omap: updated devm_xx for all resource allocation and free calls
mtd: nand: omap: use drivers/mtd/nand/nand_bch.c wrapper for BCH ECC instead of lib/bch.c
mtd: nand: omap: clean-up ecc layout for BCH ecc schemes
mtd: nand: omap2: clean-up BCHx_HW and BCHx_SW ECC configurations in device_probe
...
Pull vfs updates from Al Viro:
"All kinds of stuff this time around; some more notable parts:
- RCU'd vfsmounts handling
- new primitives for coredump handling
- files_lock is gone
- Bruce's delegations handling series
- exportfs fixes
plus misc stuff all over the place"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: (101 commits)
ecryptfs: ->f_op is never NULL
locks: break delegations on any attribute modification
locks: break delegations on link
locks: break delegations on rename
locks: helper functions for delegation breaking
locks: break delegations on unlink
namei: minor vfs_unlink cleanup
locks: implement delegations
locks: introduce new FL_DELEG lock flag
vfs: take i_mutex on renamed file
vfs: rename I_MUTEX_QUOTA now that it's not used for quotas
vfs: don't use PARENT/CHILD lock classes for non-directories
vfs: pull ext4's double-i_mutex-locking into common code
exportfs: fix quadratic behavior in filehandle lookup
exportfs: better variable name
exportfs: move most of reconnect_path to helper function
exportfs: eliminate unused "noprogress" counter
exportfs: stop retrying once we race with rename/remove
exportfs: clear DISCONNECTED on all parents sooner
exportfs: more detailed comment for path_reconnect
...
The imx23 board will check the fingerprint, so it will call the
mx23_check_transcription_stamp. This function will use @chip->buffers->databuf
as its buffer which is allocated in the nand_scan_tail().
Unfortunately, the mx23_check_transcription_stamp is called before the
nand_scan_tail(). So we will meet a NULL pointer bug:
--------------------------------------------------------------------
[ 1.150000] NAND device: Manufacturer ID: 0xec, Chip ID: 0xd7 (Samsung NAND 4GiB 3,3V 8-bit), 4096MiB, page size: 4096, OOB size: 8
[ 1.160000] Unable to handle kernel NULL pointer dereference at virtual address 000005d0
[ 1.170000] pgd = c0004000
[ 1.170000] [000005d0] *pgd=00000000
[ 1.180000] Internal error: Oops: 5 [#1] ARM
[ 1.180000] Modules linked in:
[ 1.180000] CPU: 0 PID: 1 Comm: swapper Not tainted 3.12.0 #89
[ 1.180000] task: c7440000 ti: c743a000 task.ti: c743a000
[ 1.180000] PC is at memcmp+0x10/0x54
[ 1.180000] LR is at gpmi_nand_probe+0x42c/0x894
[ 1.180000] pc : [<c025fcb0>] lr : [<c02f6a68>] psr: 20000053
[ 1.180000] sp : c743be2c ip : 600000d3 fp : ffffffff
[ 1.180000] r10: 000005d0 r9 : c02f5f08 r8 : 00000000
[ 1.180000] r7 : c75858a8 r6 : c75858a8 r5 : c7585b18 r4 : c7585800
[ 1.180000] r3 : 000005d0 r2 : 00000004 r1 : c05c33e4 r0 : 000005d0
[ 1.180000] Flags: nzCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment kernel
[ 1.180000] Control: 0005317f Table: 40004000 DAC: 00000017
[ 1.180000] Process swapper (pid: 1, stack limit = 0xc743a1c0)
--------------------------------------------------------------------
This patch rearrange the init procedure:
Set the NAND_SKIP_BBTSCAN to skip the nand scan firstly, and after we
set the proper settings, we will call the chip->scan_bbt() manually.
Cc: stable@vger.kernel.org # 3.12
Signed-off-by: Huang Shijie <b32955@freescale.com>
Reported-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
usual for this cycle with lots of clean-up.
- Cross arch clean-up and consolidation of early DT scanning code.
- Clean-up and removal of arch prom.h headers. Makes arch specific
prom.h optional on all but Sparc.
- Addition of interrupts-extended property for devices connected to
multiple interrupt controllers.
- Refactoring of DT interrupt parsing code in preparation for deferred
probe of interrupts.
- ARM cpu and cpu topology bindings documentation.
- Various DT vendor binding documentation updates.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQEcBAABAgAGBQJSgPQ4AAoJEMhvYp4jgsXif28H/1WkrXq5+lCFQZF8nbYdE2h0
R8PsfiJJmAl6/wFgQTsRel+ScMk2hiP08uTyqf2RLnB1v87gCF7MKVaLOdONfUDi
huXbcQGWCmZv0tbBIklxJe3+X3FIJch4gnyUvPudD1m8a0R0LxWXH/NhdTSFyB20
PNjhN/IzoN40X1PSAhfB5ndWnoxXBoehV/IVHVDU42vkPVbVTyGAw5qJzHW8CLyN
2oGTOalOO4ffQ7dIkBEQfj0mrgGcODToPdDvUQyyGZjYK2FY2sGrjyquir6SDcNa
Q4gwatHTu0ygXpyphjtQf5tc3ZCejJ/F0s3olOAS1ahKGfe01fehtwPRROQnCK8=
=GCbY
-----END PGP SIGNATURE-----
Merge tag 'devicetree-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DeviceTree updates for 3.13. This is a bit larger pull request than
usual for this cycle with lots of clean-up.
- Cross arch clean-up and consolidation of early DT scanning code.
- Clean-up and removal of arch prom.h headers. Makes arch specific
prom.h optional on all but Sparc.
- Addition of interrupts-extended property for devices connected to
multiple interrupt controllers.
- Refactoring of DT interrupt parsing code in preparation for
deferred probe of interrupts.
- ARM cpu and cpu topology bindings documentation.
- Various DT vendor binding documentation updates"
* tag 'devicetree-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (82 commits)
powerpc: add missing explicit OF includes for ppc
dt/irq: add empty of_irq_count for !OF_IRQ
dt: disable self-tests for !OF_IRQ
of: irq: Fix interrupt-map entry matching
MIPS: Netlogic: replace early_init_devtree() call
of: Add Panasonic Corporation vendor prefix
of: Add Chunghwa Picture Tubes Ltd. vendor prefix
of: Add AU Optronics Corporation vendor prefix
of/irq: Fix potential buffer overflow
of/irq: Fix bug in interrupt parsing refactor.
of: set dma_mask to point to coherent_dma_mask
of: add vendor prefix for PHYTEC Messtechnik GmbH
DT: sort vendor-prefixes.txt
of: Add vendor prefix for Cadence
of: Add empty for_each_available_child_of_node() macro definition
arm/versatile: Fix versatile irq specifications.
of/irq: create interrupts-extended property
microblaze/pci: Drop PowerPC-ism from irq parsing
of/irq: Create of_irq_parse_and_map_pci() to consolidate arch code.
of/irq: Use irq_of_parse_and_map()
...
[1] The gpmi uses the nand_command_lp to issue the commands to NAND chips.
The gpmi issues a DMA operation with gpmi_cmd_ctrl when it handles
a NAND_CMD_NONE control command. So when we read a page(NAND_CMD_READ0)
from the NAND, we may send two DMA operations back-to-back.
If we do not serialize the two DMA operations, we will meet a bug when
1.1) we enable CONFIG_DMA_API_DEBUG, CONFIG_DMADEVICES_DEBUG,
and CONFIG_DEBUG_SG.
1.2) Use the following commands in an UART console and a SSH console:
cmd 1: while true;do dd if=/dev/mtd0 of=/dev/null;done
cmd 1: while true;do dd if=/dev/mmcblk0 of=/dev/null;done
The kernel log shows below:
-----------------------------------------------------------------
kernel BUG at lib/scatterlist.c:28!
Unable to handle kernel NULL pointer dereference at virtual address 00000000
.........................
[<80044a0c>] (__bug+0x18/0x24) from [<80249b74>] (sg_next+0x48/0x4c)
[<80249b74>] (sg_next+0x48/0x4c) from [<80255398>] (debug_dma_unmap_sg+0x170/0x1a4)
[<80255398>] (debug_dma_unmap_sg+0x170/0x1a4) from [<8004af58>] (dma_unmap_sg+0x14/0x6c)
[<8004af58>] (dma_unmap_sg+0x14/0x6c) from [<8027e594>] (mxs_dma_tasklet+0x18/0x1c)
[<8027e594>] (mxs_dma_tasklet+0x18/0x1c) from [<8007d444>] (tasklet_action+0x114/0x164)
-----------------------------------------------------------------
1.3) Assume the two DMA operations is X (first) and Y (second).
The root cause of the bug:
Assume process P issues DMA X, and sleep on the completion
@this->dma_done. X's tasklet callback is dma_irq_callback. It firstly
wake up the process sleeping on the completion @this->dma_done,
and then trid to unmap the scatterlist S. The waked process P will
issue Y in another ARM core. Y initializes S->sg_magic to zero
with sg_init_one(), while dma_irq_callback is unmapping S at the same
time.
See the diagram:
ARM core 0 | ARM core 1
-------------------------------------------------------------
(P issues DMA X, then sleep) --> |
|
(X's tasklet wakes P) --> |
|
| <-- (P begin to issue DMA Y)
|
(X's tasklet unmap the |
scatterlist S with dma_unmap_sg) --> | <-- (Y calls sg_init_one() to init
| scatterlist S)
|
[2] This patch serialize both the X and Y in the following way:
Unmap the DMA scatterlist S firstly, and wake up the process at the end
of the DMA callback, in such a way, Y will be executed after X.
After this patch:
ARM core 0 | ARM core 1
-------------------------------------------------------------
(P issues DMA X, then sleep) --> |
|
(X's tasklet unmap the |
scatterlist S with dma_unmap_sg) --> |
|
(X's tasklet wakes P) --> |
|
| <-- (P begin to issue DMA Y)
|
| <-- (Y calls sg_init_one() to init
| scatterlist S)
|
Cc: stable@vger.kernel.org # 3.2
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We cannot scan two chips for imx23 and imx28:
imx23: the Ready-Busy1 line is not connected for some board.
imx28: we do not set the pinctrl for Ready-Busy1
So we only scan two chips for imx6.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Commit b5b4bb3f6a (of: only include prom.h on sparc) removed implicit
includes of of_*.h headers by powerpc's prom.h. Some components were
missed in initial clean-up patch, so add the necessary includes to fix
powerpc builds.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Tejun Heo <tj@kernel.org>
Cc: Matt Mackall <mpm@selenic.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-ide@vger.kernel.org
Cc: linux-crypto@vger.kernel.org
Using devm_kzalloc() can make the code simpler.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In the atmel driver probe function, the code shows like following:
atmel_nand_probe(...) {
...
err_nand_ioremap:
platform_driver_unregister(&atmel_nand_nfc_driver);
return res;
}
If no nand flash detected, the driver probe function will goto
err_nand_ioremap label.
Then platform_driver_unregister() will be called. It will get the
lock of atmel_nand device since it is parent of nfc_device. The
problem is the lock is already hold by atmel_nand_probe itself.
So system will be in a dead lock.
This patch just simply removed to platform_driver_unregister() call.
When atmel_nand driver is quit the platform_driver_unregister() will
be called in atmel_nand_remove().
[Brian: the NAND platform probe really has no business
registering/unregistering another driver; this fixes the deadlock, but
we should follow up the likely racy behavior here with a better
architecture]
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Cc: <stable@vger.kernel.org> # 3.12
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
There are too many "chip->ecc" in the nand_scan_tail() which makes the eyes
sore.
This patch uses a local variable "ecc" to replace the "chip->ecc" to
make the code more graceful.
Do the code change with "s/chip->ecc\./ecc->/g" in the nand_scan_tail,
and also change some lines by hand.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch proposes to remove the use of the IRQF_DISABLED flag
It's a NOOP since 2.6.35 and it will be removed one day.
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Fix to return a negative error code from the error handling case instead
of 0, to more closely match the rest of this function.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Now that the last user of NAND_BBT_SCANALLPAGES has been removed, let's
kill this peculiar BBT feature flag.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
'of_match_ptr' is defined in linux/of.h. Include it explicitly to
avoid build breakage in the future.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
With OMAP NAND driver updates, selection of ecc-scheme:
*DT enabled kernel*
depends on ti,nand-ecc-opt and ti,elm-id DT bindings.
*Non DT enabled kernel*
depends on elm_dev and ecc-scheme passed along with platform-data
from board file.
So, selection of ecc-scheme (BCH8 or BCH4) from KConfig can be removed
Signed-off-by: Pekon Gupta <pekon@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
"Managed Device Resource" or devm_xx calls takes care of automatic freeing
of the resource in case of:
- failure during driver probe
- failure during resource allocation
- detaching or unloading of driver module (rmmod)
Reference: Documentation/driver-model/devres.txt
Though OMAP NAND driver handles freeing of resource allocation in most of
the cases, but using devm_xx provides more clean and effortless approach
to handle all such cases.
- simplifies label for exiting probe during error
s/out_release_mem_region/return_error
Signed-off-by: Pekon Gupta <pekon@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
generic frame-work in mtd/nand/nand_bch.c is a wrapper above lib/bch.h which
encapsulates all control information specific to BCH ecc algorithm in software.
Thus this patch:
(1) replace omap specific implementations with equivalent wrapper in nand_bch.c
so that generic code from nand_bch.c is re-used. like;
omap3_correct_data_bch() -> nand_bch_correct_data()
omap3_free_bch() -> nand_bch_free()
(2) replace direct calls to lib/bch.c with wrapper functions defined in nand_bch.c
init_bch() -> nand_bch_init()
Signed-off-by: Pekon Gupta <pekon@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In current implementation omap3_init_bch_tail() is a common function to
define ecc layout for different BCHx ecc schemes.This patch:
(1) removes omap3_init_bch_tail() and defines ecc layout for individual
ecc-schemes along with populating their nand_chip->ecc data in
omap_nand_probe(). This improves the readability and scalability of
code for add new ecc schemes in future.
(2) removes 'struct nand_bbt_descr bb_descrip_flashbased' because default
nand_bbt_descr in nand_bbt.c matches the same (.len=1 for x8 devices).
(3) add the check to see if NAND device has enough OOB/Spare bytes to
store ECC signature of whole page, as defined by ecc-scheme.
Signed-off-by: Pekon Gupta <pekon@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
current implementation in omap3_init_bch() has some redundant code like:
(1) omap3_init_bch() re-probes the DT-binding to detect presence of ELM h/w
engine on SoC. And based on that it selects implemetation of ecc-scheme.
However, this is already done as part of GPMC DT parsing.
(2) As omap3_init_bch() serves as common function for configuring all types of
BCHx ecc-schemes, so there are multiple levels of redudant if..then..else
checks while populating nand_chip->ecc.
This patch make following changes to OMAP NAND driver:
(1) removes omap3_init_bch(): each ecc-scheme is individually configured in
omap_nand_probe() there by removing redundant if..then..else checks.
(2) adds is_elm_present(): re-probing of ELM device via DT is not required as
it's done in GPMC driver probe. Thus is_elm_present() just initializes ELM
driver with NAND probe data, when ecc-scheme with h/w based error-detection
is used.
(3) separates out configuration of different flavours of "BCH4" and "BCH8"
ecc-schemes as given in below table
(4) conditionally compiles callbacks implementations of ecc.hwctl(),
ecc.calculate(), ecc.correct() to avoid warning of un-used functions.
+---------------------------------------+---------------+---------------+
| ECC scheme |ECC calculation|Error detection|
+---------------------------------------+---------------+---------------+
|OMAP_ECC_HAM1_CODE_HW |H/W (GPMC) |S/W |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)|
| (needs CONFIG_MTD_NAND_ECC_BCH) | | |
| | | |
|OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) |
| (needs CONFIG_MTD_NAND_OMAP_BCH && | | |
| ti,elm-id) | | |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W (lib/bch.c)|
| (needs CONFIG_MTD_NAND_ECC_BCH) | | |
| | | |
|OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) |
| (needs CONFIG_MTD_NAND_OMAP_BCH && | | |
| ti,elm-id) | | |
+---------------------------------------+---------------+---------------+
- 'CONFIG_MTD_NAND_ECC_BCH' is generic KConfig required to build lib/bch.c
which is required for ECC error detection done in software.
(mainly used for legacy platforms which do not have on-chip ELM engine)
- 'CONFIG_MTD_NAND_OMAP_BCH' is OMAP specific Kconfig to detemine presence
on ELM h/w engine on SoC.
Signed-off-by: Pekon Gupta <pekon@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch:
- calls nand_scan_ident() using bus-width as passed by DT
- removes double calls to nand_scan_ident(), in case first call fails
then omap_nand_probe just returns error.
Signed-off-by: Pekon Gupta <pekon@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
In the imx6, all the ready/busy pins are binding togeter.
So we should always check the ready/busy pin of the chip 0.
In the other word, when the CS1 is enabled, we should also check the
ready/busy of chip 0; if we check the ready/busy of chip 1,
we will get the wrong result.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Some nand chip has two DIEs in a single chip, such as Micron MT29F32G08QAA.
Each die has its own chip select pin, so this chip acts as two nand
chips.
If we only scan one chip, we may find that we only get 2G for this chip,
but in actually, this chip's size is 4G.
So scan two chips by default.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We only have one DMA channel : the channel 0.
Use DMA channel 0 to access all the nand chips.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Decouple the chip select from the DMA channel, we use the DMA channel 0
to accecc all the nand devices.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
as per controller description,
"While programming a NAND flash, status read should never skipped.
Because it may happen that a new command is issued to the NAND Flash,
even when the device has not yet finished processing the previous request.
This may result in unpredictable behaviour."
IFC controller never polls for R/B signal after command send. It just return
control to software. This behaviour may not occur with NAND flash access.
because new commands are sent after polling R/B signal. But it may happen
in scenario where GPCM-ASIC and NAND flash device are working simultaneously.
Update the controller driver to take care of this requirement
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Current IFC driver supports till 4K page size NAND flash.
Add support of 8K Page size NAND flash
- Add nand_ecclayout for 4 bit & 8 bit ecc
- Defines constants
- also fix ecc.strength for 8bit ecc of 8K page size NAND
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
devm_kzalloc is device managed and simplifies the code.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Some bright specification writers decided to write this in the ONFI spec
(from ONFI 3.0, Section 3.1):
"The number of blocks and number of pages per block is not required to
be a power of two. In the case where one of these values is not a
power of two, the corresponding address shall be rounded to an
integral number of bits such that it addresses a range up to the
subsequent power of two value. The host shall not access upper
addresses in a range that is shown as not supported."
This breaks every assumption MTD makes about NAND block/chip-size
dimensions -- they *must* be a power of two!
And of course, an enterprising manufacturer has made use of this lovely
freedom. Exhibit A: Micron MT29F32G08CBADAWP
"- Plane size: 2 planes x 1064 blocks per plane
- Device size: 32Gb: 2128 blockss [sic]"
This quickly hits a BUG() in nand_base.c, since the extra dimensions
overflow so we think it's a second chip (on my single-chip setup):
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0x44 (Micron MT29F32G08CBADAWP), 4256MiB, page size: 8192, OOB size: 744
------------[ cut here ]------------
kernel BUG at drivers/mtd/nand/nand_base.c:203!
Internal error: Oops - BUG: 0 [#1] SMP ARM
[... trim ...]
[<c02cf3e4>] (nand_select_chip+0x18/0x2c) from [<c02d25c0>] (nand_do_read_ops+0x90/0x424)
[<c02d25c0>] (nand_do_read_ops+0x90/0x424) from [<c02d2dd8>] (nand_read+0x54/0x78)
[<c02d2dd8>] (nand_read+0x54/0x78) from [<c02ad2c8>] (mtd_read+0x84/0xbc)
[<c02ad2c8>] (mtd_read+0x84/0xbc) from [<c02d4b28>] (scan_read.clone.4+0x4c/0x64)
[<c02d4b28>] (scan_read.clone.4+0x4c/0x64) from [<c02d4c88>] (search_bbt+0x148/0x290)
[<c02d4c88>] (search_bbt+0x148/0x290) from [<c02d4ea4>] (nand_scan_bbt+0xd4/0x5c0)
[... trim ...]
---[ end trace 0c9363860d865ff2 ]---
So to fix this, just truncate these dimensions down to the greatest
power-of-2 dimension that is less than or equal to the specified
dimension.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: <stable@vger.kernel.org>
This commit replaces the currently hardcoded buffer size, by a
dynamic detection scheme. First a small 256 bytes buffer is allocated
so the device can be detected (using READID and friends commands).
After detection, this buffer is released and a new buffer is allocated
to acommodate the page size plus out-of-band size.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Instead of setting info->dma each time a command is prepared,
we can move it after the DMA buffers are allocated.
This is more clear and it's the proper place to enable this, given
DMA cannot be turned on and off during runtime.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The loop that polls the status register waiting for an operation to complete
foolishly bases the timeout simply on the number of loop iterations that have
ocurred. When I increased the processor clock speed, timeouts started to appear
for long block erasure operations. This patch measures the timeout using
jiffies.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
devm_kzalloc is device managed and makes code simpler.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Driver core will set the driver data to NULL upon detach or
probe failure.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
module_platform_driver removes boiler plate code and makes it
simpler.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Driver core will set the driver data to NULL upon detach or
probe failure.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The data structure of_match_ptr() protects is always compiled in.
Hence of_match_ptr() is not needed.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The data structure of_match_ptr() protects is always compiled in.
Hence of_match_ptr() is not needed.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The data structure of_match_ptr() protects is always compiled in.
Hence of_match_ptr() is not needed.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The driver core clears the driver data to NULL after device_release
or on probe failure. Thus, it is not needed to manually clear the
device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Here's the big driver core / sysfs update for 3.13-rc1.
There's lots of dev_groups updates for different subsystems, as they all
get slowly migrated over to the safe versions of the attribute groups
(removing userspace races with the creation of the sysfs files.) Also
in here are some kobject updates, devres expansions, and the first round
of Tejun's sysfs reworking to enable it to be used by other subsystems
as a backend for an in-kernel filesystem.
All of these have been in linux-next for a while with no reported
issues.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iEYEABECAAYFAlJ6xAMACgkQMUfUDdst+yk1kQCfcHXhfnrvFZ5J/mDP509IzhNS
ddEAoLEWoivtBppNsgrWqXpD1vi4UMsE
=JmVW
-----END PGP SIGNATURE-----
Merge tag 'driver-core-3.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core
Pull driver core / sysfs patches from Greg KH:
"Here's the big driver core / sysfs update for 3.13-rc1.
There's lots of dev_groups updates for different subsystems, as they
all get slowly migrated over to the safe versions of the attribute
groups (removing userspace races with the creation of the sysfs
files.) Also in here are some kobject updates, devres expansions, and
the first round of Tejun's sysfs reworking to enable it to be used by
other subsystems as a backend for an in-kernel filesystem.
All of these have been in linux-next for a while with no reported
issues"
* tag 'driver-core-3.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (83 commits)
sysfs: rename sysfs_assoc_lock and explain what it's about
sysfs: use generic_file_llseek() for sysfs_file_operations
sysfs: return correct error code on unimplemented mmap()
mdio_bus: convert bus code to use dev_groups
device: Make dev_WARN/dev_WARN_ONCE print device as well as driver name
sysfs: separate out dup filename warning into a separate function
sysfs: move sysfs_hash_and_remove() to fs/sysfs/dir.c
sysfs: remove unused sysfs_get_dentry() prototype
sysfs: honor bin_attr.attr.ignore_lockdep
sysfs: merge sysfs_elem_bin_attr into sysfs_elem_attr
devres: restore zeroing behavior of devres_alloc()
sysfs: fix sysfs_write_file for bin file
input: gameport: convert bus code to use dev_groups
input: serio: remove bus usage of dev_attrs
input: serio: use DEVICE_ATTR_RO()
i2o: convert bus code to use dev_groups
memstick: convert bus code to use dev_groups
tifm: convert bus code to use dev_groups
virtio: convert bus code to use dev_groups
ipack: convert bus code to use dev_groups
...
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Current code sets the mtd->type with MTD_NANDFLASH for both
SLC and MLC. So the jffs2 may supports the MLC nand, but in actually,
the jffs2 should not support the MLC.
This patch uses the nand_is_slc() to check the nand cell type,
and set the mtd->type with the right nand type.
After this patch, the jffs2 only supports the SLC nand.
The side-effect of this patch:
Before this patch, the ioctl(MEMGETINFO) can only return with the
MTD_NANDFLASH; but after this patch, the ioctl(MEMGETINFO) will
return with the MTD_NANDFLASH for SLC, and MTD_MLCNANDFLASH for MLC.
So the user applictions(such as mtd-utils) should also changes a little
for this.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
When we use the ECC info which is get from the nand chip's datasheet,
we may have some freed oob area now.
This patch rewrites the gpmi_ecc_write_oob() to implement the ecc.write_oob().
We also update the comment for gpmi_hw_ecclayout.
Yes! We can support the JFFS2 for the SLC nand now.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Print out the cell information for nand chip.
(Since the message is too long, this patch also splits the log
with two separate pr_info())
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The current code does not set the SLC/MLC information for onfi nand.
(This makes that the kernel treats all the onfi nand as SLC nand.)
This patch fills the cell information for ONFI nands.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The legacy ID NAND are all SLC.
This patch sets 1 to the @bits_per_cell for the legacy ID NAND,
which means they are all SLC.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The @cellinfo fields contains unused information, such as write caching,
internal chip numbering, etc. But we only use it to check the SLC or MLC.
This patch tries to make it more clear and simple, renames the @cellinfo
to @bits_per_cell.
In order to avoiding the bisect issue, this patch also does the following
changes:
(0) add a macro NAND_CI_CELLTYPE_SHIFT to avoid the hardcode.
(1) add a helper to parse out the cell type : nand_get_bits_per_cell()
(2) parse out the cell type for extended-ID chips and the full-id nand chips.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add a helper to check if a nand chip is SLC or MLC.
This helper makes the code more readable.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
If the ONFI extended parameter page gives codeword_size == 0, the
extended ECC information is corrupt and should not be used. Currently,
we (correctly) avoid using the information, but we don't report the
error to the caller, so the caller doesn't know that we didn't
initialize ecc_strength_ds and ecc_step_ds. Now the caller can warn the
user that it does not have sufficient information.
This also removes the false and useless "ONFI extended param page
detected" debug message (it was printed even on the aforementioned
corruption, and for the success case, we don't really want a print).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com>
Since ecc_{strength,step}_ds is introduced in nand_chip structure for
minimum ecc requirements. So we can use them directly and remove our
own get_onfi_ecc_param function.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch also add a const keyword for the of_device_id of nfc.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Since the of specific code are declared in <linux/of_mtd.h> regardless
of CONFIG_OF. Remove the #if defined(CONFIG_OF) guard and use an
IS_ENABLED(CONFIG_OF) instead.
Thanks to Ezequiel Garcia's for this protype.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The ONFI detection routine is too verbose in some cases and not verbose
enough in others. This patch refactors it to print only when there are
significant warnings/errors.
Probing in 16-bit mode:
It is unnecessary to print until after the READID (address 20h)
command. READID *has* to work properly in whatever bus width
configuration we are in, or else no identification mode works. So we
can silence some useless warnings on systems which come up in 16-bit
mode and do not even respond with an O-N-F-I string.
Valid parameter page:
Nobody needs to see this. Do we inform the user every time other
hardware responds properly? Instead, add an error message if *no*
uncorrupted parameter pages are found.
ONFI ECC:
Most drivers don't yet use the reported minimum ECC values, so it
shouldn't yet be a fatal condition if the extended parameter page is
incorrect. But we should at least give a warning for the corner cases
that we don't expect.
ONFI flash detected:
Nobody needs to see this. This is the expected case, that we detect
ONFI properly, or else it wasn't ONFI-compliant and is detected by
some other routine.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Huang Shijie <b32955@freescale.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
I removed the last non-nand_base users of this, and we shouldn't have
any more modules that need to access it. It's only non-static to share
between nand_base and nand_bbt.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This driver is doing some strange logic here. If it doesn't have
flash-based BBT enabled, it allows nand_scan_tail() to scan the BBT. But
if it is using flash-based BBT, it tells nand_scan_tail() to skip
scanning, then it immediately calls the default BBT scanning function
itself.
As I read it, this logic is equivalent to the default nand_scan_tail()
behavior without interfering with NAND_SKIP_BBTSCAN or calling
nand_default_bbt() directly at all.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
There's no point in the low level driver doing the work that nand_base
already is doing; just let nand_base set the default BBT scanning
function.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Mike Dunn <mikedunn@newsguy.com>
The "legacy" ECC layout used until 3.12-rc1 uses all the OOB area by
computing the ECC strength and ECC step size ourselves.
Commit 2febcdf84b ("mtd: gpmi: set the BCHs geometry with the ecc info")
makes the driver use the ECC info (ECC strength and ECC step size)
provided by the MTD code, and creates a different NAND ECC layout
for the BCH, and use the new ECC layout. This causes a regression:
We can not mount the ubifs which was created by the old NAND ECC layout.
This patch fixes this issue by reverting to the legacy ECC layout.
We will probably introduce a new device-tree property to indicate that
the new ECC layout can be used. For now though, for the imminent 3.12
release, we just unconditionally revert to the 3.11 behaviour.
This leaves a harmless cosmetic warning about an unused function. At
this point in the cycle I really don't care.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
In a recent commit:
commit f455578dd9
Author: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Date: Mon Aug 12 14:14:53 2013 -0300
mtd: nand: pxa3xx: Remove hardcoded mtd name
There's no advantage in using a hardcoded name for the mtd device.
Instead use the provided by the platform_device.
The MTD name was changed to use the one provided by the platform_device.
However, this can be problematic as some users want to set partitions
using the kernel parameter 'mtdparts', where the name is needed.
Therefore, to avoid regressions in users relying in 'mtdparts' we revert
the change and use the previous one 'pxa3xx_nand-0'.
While at it, let's put a big comment and prevent this change from happening
ever again.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Correct spelling typo within various part of the kernel
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Powerpc is a mess of implicit includes by prom.h. Add the necessary
explicit includes to drivers in preparation of prom.h cleanup.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Grant Likely <grant.likely@linaro.org>
This fixes a memory leak in the ONFI support code for detecting the
required ECC levels from this commit:
commit 6dcbe0cdd8
Author: Huang Shijie <b32955@freescale.com>
Date: Wed May 22 10:28:27 2013 +0800
mtd: get the ECC info from the Extended Parameter Page
In the success case, we never freed the 'ep' buffer.
Also, this fixes an oversight in the same commit where we (harmlessly)
freed the NULL pointer.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Move probe out of __init section and don't use platform_driver_probe
which cannot be used with deferred probing.
Since commit e9354576 ("gpiolib: Defer failed gpio requests by default")
this driver might return -EPROBE_DEFER if a gpio_request fails.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Johan Hovold <jhovold@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
There's no need to enclose this code within idef CONFIG_OF,
because the OF framework provides no-op stubs if CONFIG_OF=n.
Cc: devicetree@vger.kernel.org
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
- nand-gpio cleanup and portability to non-ARM
- m25p80 support for 4-byte addressing chips, other new chips
- pxa3xx cleanup and support for new platforms
- remove obsolete alauda, octagon-5066 drivers
- erase/write support for bcm47xxsflash
- improve detection of ECC requirements for NAND, controller setup
- NFC acceleration support for atmel-nand, read/write via SRAM
- etc.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iEYEABECAAYFAlIt3VsACgkQdwG7hYl686NKBQCgqFzV1S+TiXZSjbqanK0374Hu
lMIAoI2IOQb1bgQFSqaOzgSaBmVhLtMc
=xWBt
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20130909' of git://git.infradead.org/linux-mtd
Pull mtd updates from David Woodhouse:
- factor out common code from MTD tests
- nand-gpio cleanup and portability to non-ARM
- m25p80 support for 4-byte addressing chips, other new chips
- pxa3xx cleanup and support for new platforms
- remove obsolete alauda, octagon-5066 drivers
- erase/write support for bcm47xxsflash
- improve detection of ECC requirements for NAND, controller setup
- NFC acceleration support for atmel-nand, read/write via SRAM
- etc
* tag 'for-linus-20130909' of git://git.infradead.org/linux-mtd: (184 commits)
mtd: chips: Add support for PMC SPI Flash chips in m25p80.c
mtd: ofpart: use for_each_child_of_node() macro
mtd: mtdswap: replace strict_strtoul() with kstrtoul()
mtd cs553x_nand: use kzalloc() instead of memset
mtd: atmel_nand: fix error return code in atmel_nand_probe()
mtd: bcm47xxsflash: writing support
mtd: bcm47xxsflash: implement erasing support
mtd: bcm47xxsflash: convert to module_platform_driver instead of init/exit
mtd: bcm47xxsflash: convert kzalloc to avoid invalid access
mtd: remove alauda driver
mtd: nand: mxc_nand: mark 'const' properly
mtd: maps: cfi_flagadm: add missing __iomem annotation
mtd: spear_smi: add missing __iomem annotation
mtd: r852: Staticize local symbols
mtd: nandsim: Staticize local symbols
mtd: impa7: add missing __iomem annotation
mtd: sm_ftl: Staticize local symbols
mtd: m25p80: add support for mr25h10
mtd: m25p80: make CONFIG_M25PXX_USE_FAST_READ safe to enable
mtd: m25p80: Pass flags through CAT25_INFO macro
...
It's cleaner to use kzalloc() instead of zeroing out in a separate call
to memset().
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Fix to return a negative error code from the error handling
case instead of 0, as done elsewhere in this function.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver has very low utility. Devices in question are limited to
about 400kB/s and the only known user (me) discarded the hardware
several years back.
Signed-off-by: Joern Engel <joern@logfs.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The values pointed by the pointer are used as read-only.
Also, mtd_device_parse_register() uses 'part_probes[]' as
the second argument which is defined as 'const char * const *types'.
Thus, the 'const' should be moved to be after the '*'.
drivers/mtd/nand/mxc_nand.c:269:25: warning: duplicate const
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
These local symbols are used only in this file.
Fix the following sparse warnings:
drivers/mtd/nand/r852.c:232:6: warning: symbol 'r852_write_buf' was not declared. Should it be static?
drivers/mtd/nand/r852.c:264:6: warning: symbol 'r852_read_buf' was not declared. Should it be static?
drivers/mtd/nand/r852.c:315:6: warning: symbol 'r852_cmdctl' was not declared. Should it be static?
drivers/mtd/nand/r852.c:360:5: warning: symbol 'r852_wait' was not declared. Should it be static?
drivers/mtd/nand/r852.c:389:5: warning: symbol 'r852_ready' was not declared. Should it be static?
drivers/mtd/nand/r852.c:400:6: warning: symbol 'r852_ecc_hwctl' was not declared. Should it be static?
drivers/mtd/nand/r852.c:432:5: warning: symbol 'r852_ecc_calculate' was not declared. Should it be static?
drivers/mtd/nand/r852.c:464:5: warning: symbol 'r852_ecc_correct' was not declared. Should it be static?
drivers/mtd/nand/r852.c:532:6: warning: symbol 'r852_engine_enable' was not declared. Should it be static?
drivers/mtd/nand/r852.c:550:6: warning: symbol 'r852_engine_disable' was not declared. Should it be static?
drivers/mtd/nand/r852.c:560:6: warning: symbol 'r852_card_update_present' was not declared. Should it be static?
drivers/mtd/nand/r852.c:575:6: warning: symbol 'r852_update_card_detect' was not declared. Should it be static?
drivers/mtd/nand/r852.c:589:9: warning: symbol 'r852_media_type_show' was not declared. Should it be static?
drivers/mtd/nand/r852.c:600:1: warning: symbol 'dev_attr_media_type' was not declared. Should it be static?
drivers/mtd/nand/r852.c:604:6: warning: symbol 'r852_update_media_status' was not declared. Should it be static?
drivers/mtd/nand/r852.c:633:5: warning: symbol 'r852_register_nand_device' was not declared. Should it be static?
drivers/mtd/nand/r852.c:671:6: warning: symbol 'r852_unregister_nand_device' was not declared. Should it be static?
drivers/mtd/nand/r852.c:685:6: warning: symbol 'r852_card_detect_work' was not declared. Should it be static?
drivers/mtd/nand/r852.c:824:6: warning: symbol 'r852_probe' was not declared. Should it be static?
drivers/mtd/nand/r852.c:964:6: warning: symbol 'r852_remove' was not declared. Should it be static?
drivers/mtd/nand/r852.c:995:6: warning: symbol 'r852_shutdown' was not declared. Should it be static?
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
These local symbols are used only in this file.
Fix the following sparse warnings:
drivers/mtd/nand/nandsim.c:1436:5: warning: symbol 'do_read_error' was not declared. Should it be static?
drivers/mtd/nand/nandsim.c:1448:6: warning: symbol 'do_bit_flips' was not declared. Should it be static?
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
If NO_DMA=y:
drivers/built-in.o: In function `denali_remove':
drivers/mtd/nand/denali.c:1605: undefined reference to `dma_unmap_single'
drivers/built-in.o: In function `denali_read_page_raw':
drivers/mtd/nand/denali.c:1190: undefined reference to `dma_sync_single_for_cpu'
drivers/built-in.o: In function `denali_read_page':
drivers/mtd/nand/denali.c:1140: undefined reference to `dma_sync_single_for_cpu'
drivers/built-in.o: In function `write_page':
drivers/mtd/nand/denali.c:1051: undefined reference to `dma_sync_single_for_cpu'
drivers/built-in.o: In function `denali_init':
drivers/mtd/nand/denali.c:1433: undefined reference to `dma_set_mask'
drivers/mtd/nand/denali.c:1438: undefined reference to `dma_map_single'
drivers/mtd/nand/denali.c:1442: undefined reference to `dma_mapping_error'
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Remove unneeded error handling on the result of a call to
platform_get_resource_byname when the value is passed to devm_ioremap_resource.
A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)
// <smpl>
@@
expression pdev,res,e,e1;
expression ret != 0;
identifier l;
@@
res = platform_get_resource_byname(...);
- if (res == NULL) { ... \(goto l;\|return ret;\) }
e = devm_ioremap_resource(e1, res);
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The PMECC use BCH algorithm to correct error. In BCH algorithm, the primitive
polynomial value is GF(2^13) for 512-bytes sector size. And it is GF(2^14) for
1024-bytes sector size.
This patch will choose correct degree of the remainders (13 or 14) for
different sector size.
Tested in AT91SAM9X5-EK with MLC nand flash.
More detail can be found in §5.4.1 of:
AT91SAM ARM-based Embedded MPU Application Note
<http://www.atmel.com/Images/doc11127.pdf>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
First, the function argument is 'offset' not 'column'.
Second, the 'data_buf' name is inconsistent with the rest of this file.
Just use 'buf'.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Gupta, Pekon <pekon@ti.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
In order to make the nand_scan() work, the current code uses the hack code
to init the @nand_chip->ecc.size and the @nand_chip->ecc.strength. and
re-init some the ECC info in the gpmi_pre_bbt_scan().
This code is really a little ugly.
The patch does following changes:
(1) Use the nand_scan_ident()/nand_scan_tail() to replace the nand_scan().
(2) Init all the necessary values in the gpmi_init_last()
before we call the nand_scan_tail().
(3) remove the code setting the ECC info, let the mtd layer to do the
real job.
(4) remove the gpmi_scan_bbt(). we do not need this function any more.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
We may do some ONFI get/set features operations before we call the
nand_scan_tail().
So move the default ONFI nand hooks into nand_set_defaults().
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Set the ecc step size for master/slave mtd_info{}.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
There are static checkers which complain when we declare variables as
64 bit bitfields but only use the lower 32 bits because of shift
wrapping. In this case "len" is declared as u64 as opposed to unsigned
long or something which might be 32 bits.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Remove unneeded error handling on the result of a call to
platform_get_resource when the value is passed to devm_ioremap_resource.
Move the call to platform_get_resource adjacent to the call to
devm_ioremap_resource to make the connection between them more clear.
A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)
// <smpl>
@@
expression pdev,res,n,e,e1;
expression ret != 0;
identifier l;
@@
- res = platform_get_resource(pdev, IORESOURCE_MEM, n);
... when != res
- if (res == NULL) { ... \(goto l;\|return ret;\) }
... when != res
+ res = platform_get_resource(pdev, IORESOURCE_MEM, n);
e = devm_ioremap_resource(e1, res);
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The Armada 370 and Armada XP SoC families, selected by PLAT_ORION,
have a Nand Flash Controller (NFC) IP very similar to the one present
in PXA platforms. Therefore, we want to build this driver on PLAT_ORION.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When use_dma=0 there's no point in requesting resources for dma,
since they won't be used anyway. Therefore we remove that requirement,
therefore allowing devices without dma to pass the driver probe.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Now that we have added ARCH_HAS_DMA conditional the function
enable_int() may be unused. Declare it as __maybe_unused,
in order to remove the following warning, when the function is not used:
drivers/mtd/nand//pxa3xx_nand.c:343:24: warning: 'enable_int' defined
but not used [-Wunused-function]
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch adds a macro ARCH_HAS_DMA to compile-out arch specific
dma code, namely pxa_request_dma() and pxa_free_dma(). These symbols
are available only in pxa, which makes impossible to build the driver in
other platforms than ARCH_PXA.
In order to handle non-dma capable platforms, we implement a fallbacks that
allocate buffers as if 'use_dma=false', putting the dma related code
under the ARCH_HAS_DMA conditional.
Please note that the correct way to handle this is to migrate the
dma code to use of the mmp_pdma dmaengine driver. However, currently
this is not possible because the two dmaengine drivers can't work together.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This registers are not per-chip (aka host) but controller-wide,
so it's better to store them in the global 'info' structure.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Use the defined macros for NAND command instead of using a constant
internal structure. This commit is only a cleanup, there's no
functionality modification.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
There's no advantage in using a hardcoded name for the mtd device.
Instead use the provided by the platform_device.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This is just a cosmetic change, to make the code more readable.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The ONFI command 'parameter page read' needs a non-standard length.
Therefore, we enable the 'length override' field in NDCB0 and set
a non-zero 'length count' in NDCB3.
Additionally, the 'spare enable' bit must be disabled for any command
that sets a non-zero 'length count' in NDCB3.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Some newer controllers support a fourth command buffer. This additional
command buffer allows to set an arbitrary length count, using the
NDCB3.NDLENCNT field, to perform non-standard length operations
such as the ONFI parameter page read.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Some commands (such as the ONFI parameter page read) need to
clear the 'spare enable' bit. This commit allows to set/clear
depending on the prepared command, instead of having it always
set.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When ECC is not selected, the ECC enable bit must be cleared
in the NAND control register. Same applies to DMA.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This driver supports NFCv1 (as found in PXA SoC) and NFCv2 (as found in
Armada 370/XP SoC). As both controller has a few differences, a way of
distinguishing between the two is needed.
This commit introduces a new compatible string 'marvell,armada370-nand'
and assigns a compatible data of type enum pxa3xx_nand_variant to allow
such distinction.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
If the nand chip provides us the ECC info, we can use it firstly.
The set_geometry_by_ecc_info() will use the ECC info, and
calculate the parameters we need.
Rename the old code to legacy_set_geometry() which will takes effect
when there is no ECC info from the nand chip or we fails in the ECC info case.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Add the ecc info for TC58NVG2S0F, TC58NVG3S0F, TC58NVG5D2 and TC58NVG6D2.
From these chips' datasheets, we know that:
The TC58NVG2S0F and TC58NVG3S0F require 4bit ECC for per 512byte.
The TC58NVG5D2 and TC58NVG6D2 require 40bits ECC for per 1024byte.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Parse out the ECC information for the full-id nand chips.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The current code uses the hardcode to detect the 16-bit bus width.
Use the onfi_feature() to replace it.
Signed-off-by: Huang Shijie <b32955@freescale.com>
[Brian: small fixup]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Since the ONFI 2.1, the onfi spec adds the Extended Parameter Page
to store the ECC info.
The onfi spec tells us that if the nand chip's recommended ECC codeword
size is not 512 bytes, then the @ecc_bits is 0xff. The host _SHOULD_ then
read the Extended ECC information that is part of the extended parameter
page to retrieve the ECC requirements for this device.
This patch implement the reading of the Extended Parameter Page, and parses
the sections for ECC type, and get the ECC info from the ECC section.
Tested this patch with Micron MT29F64G08CBABAWP.
Acked-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
From the ONFI spec, we can just get the ECC info from the @ecc_bits field of
the parameter page.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
It is better to do the sanity check for the parameter before any hardware
operation.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Use the wrapper function for retrieving the platform data instead of
accessing dev->platform_data directly.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Use NAND_CI_CELLTYPE_MSK to extract the cell type from nand_chip.cellinfo
instead of hardcoded constant.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Artem Bityutskiy <dedekind1@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch fix following warning:
drivers/mtd/nand/atmel_nand.c:2007: warning: 'atmel_nand_nfc_match' defined but not used
This patch add '#if defined(CONFIG_OF)' block to guard around the definition
of atmel_nand_nfc_match, in order to avoid the warning when the kernel is
configured without DT support.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
NAND_BBT_SCANEMPTY is a strange, badly-supported option with omap as its
single remaining user.
NAND_BBT_SCANEMPTY was likely used by accident in omap2[1]. And anyway,
omap2 doesn't scan the chip for bad blocks (courtesy of
NAND_SKIP_BBTSCAN), and so its use of this option is irrelevant.
This patch drops the NAND_BBT_SCANEMPTY option.
[1] http://lists.infradead.org/pipermail/linux-mtd/2012-July/042902.html
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Ivan Djelic <ivan.djelic@parrot.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
nand_base.c shouldn't have to know the implementation details of
nand_bbt's in-memory BBT. Specifically, nand_base shouldn't perform the
bit masking and shifting to isolate a BBT entry.
Instead, just move some of the BBT code into a new nand_markbad_bbt()
interface. This interface allows external users (i.e., nand_base) to
mark a single block as bad in the BBT. Then nand_bbt will take care of
modifying the in-memory BBT and updating the flash-based BBT (if
applicable).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The chip->block_markbad pointer should really only be responsible for
writing a bad block marker for new bad blocks. It should not take care
of BBT-related functionality, nor should it handle bookkeeping of bad
block stats.
This patch refactors the 3 users of the block_markbad interface (plus
the default nand_base implementation) so that the common code is kept in
nand_block_markbad_lowlevel(). It removes some inconsistencies between
the various implementations and should allow for more centralized
improvements in the future.
Because gpmi-nand no longer needs the nand_update_bbt() function, let's
stop exporting it as well.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Huang Shijie <b32955@freescale.com> (for gpmi-nand parts)
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Just make 'res' an int.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The parent commit 771c568bcf ("mtd: nand: add
accessors, macros for in-memory BBT") makes the following comment obsolete:
/*
* Note that numblocks is 2 * (real numblocks) here, see i+=2
* below as it makes shifting and masking less painful
*/
I don't think it ever could have been "less painful" to have to shift an
extra bit (or 2, or 3) at various points in nand_bbt.c (and even
outside, since we leak our in-memory format). But now it is certainly
more painful, since we have nice macros and functions to retrieve the
relevant portions of the BBT.
This patch removes any points where the block number is
doubled/halved/otherwise-shifted, instead representing the block number
in its most natural form: as the actual block number.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
There is an abundance of magic numbers and complicated shifting/masking
logic in the in-memory BBT code which makes the code unnecessary complex
and hard to read.
This patch adds macros to represent the 00b, 01b, 10b, and 11b
memory-BBT magic numbers, as well as two accessor functions for reading
and marking the memory-BBT bitfield for a given block.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
use devm_clk_get() for automatic put after device close, check for and
propagate errors when enabling clocks, need to prepare clocks before
they can get enabled, adjust error code paths to correctly balance
get/put and prepare/unprepare and enable/disable calls
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This patch enable writing nand flash via NFC SRAM. It will minimize the CPU
overhead. The SRAM write only support ECC_NONE and ECC_HW with PMECC.
To enable this NFC write by SRAM feature, you can add a string in dts under
NFC driver node.
This driver has been tested on SAMA5D3X-EK with JFFS2, YAFFS2, UBIFS and
mtd-utils.
Here is part of mtd_speedtest (writing test) result, compare with non-NFC
writing, it reduces %65 cpu load with loss %12 speed.
- commands use to test:
# insmod /mnt/mtd_speedtest.ko dev=2 &
# top -n 30 -d 1 | grep speedtest
- test result:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
mtd_speedtest: testing eraseblock write speed
509 495 root D 1164 0% 7% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root D 1164 0% 8% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root R 1164 0% 5% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: eraseblock write speed is 5194 KiB/s
mtd_speedtest: testing page write speed
509 495 root D 1164 0% 32% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root D 1164 0% 27% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root D 1164 0% 25% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root D 1164 0% 30% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: page write speed is 5024 KiB/s
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
this will allow to simply the error and remove path
Cc: linux-mtd@lists.infradead.org
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
[josh.wu@atmel.com: fix checkpatch warnings and rebase to latest mtd git tree]
[josh.wu@atmel.com: replace devm_request_and_ioremap with devm_ioremap_resource]
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
ns->geom.oobshift holds bits number in OOB size, but OOB size is not
always power of two. So it is useless and it actually isn't used in
this driver except for just printing the value at module loading.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Use NS_RAW_OFFSET() to calculate the page offset in flash RAM image by
(row, column) address.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Simplify the definision of NS_RAW_OFFSET() by using (ns)->geom.pgszoob
which holds the sum of page size and OOB size.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Use kasprintf() which combines kmalloc and sprintf.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
nandsim.pages_written[] is the array of unsigned char which is indexed
by the page number and used for identifying which pages have been written
when cache_file is used. Each entry holds 0 (not written) or 1 (written),
so it can be converted to bitmap. This reduces the allocation size of
pages_written[] by 1/8.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Toshiba NAND datasheets have not been very forthcoming on OOB size
information; they do not provide any bitfields in the ID string for
spare area. In their 24nm technology flash, however, Toshiba migrated
their NAND to have 32 bytes spare per 512 bytes of page area (up from
the traditional 16 bytes), as they now require 8-bit ECC or higher.
I have discussed this issue directly with Toshiba representatives, and
they acknowledge this problem. They recommend detecting these flash
based on their technology node as follows:
For 24nm Toshiba SLC raw NAND (not BENAND -- Built-in Ecc NAND), there
are 32 bytes of spare area for every 512 bytes of in-band data area.
We can implement this rule with the following snippet of a device ID
decode table, which applies to all their 43nm, 32nm, and 24nm SLC NAND
(this table is not fully in the NAND datasheets, but it was provided
directly by Toshiba representatives):
- ID byte 5, bit[7]:
1 -> BENAND
0 -> raw SLC
- ID byte 6, bits[2:0]:
100b -> 43nm
101b -> 32nm
110b -> 24nm
111b -> Reserved
I'm also working with Toshiba on including this bitfield description for
their 5th and 6th ID bytes in their public data sheets.
I will provide the 8-byte ID strings from the two 24nm Toshiba samples I
have; their first 6 bytes match the documentation I received from
Toshiba:
24nm SLC 1Gbit TC58NVG0S3HTA00
0x98 0xf1 0x80 0x15 0x72 0x16 0x08 0x00
24nm SLC 2Gbit TC58NVG1S3HTA00
0x98 0xda 0x90 0x15 0x76 0x16 0x08 0x00
I have also tested for regressions with:
43nm SLC 4Gbit TC58NVG2S3ETA00
0x98 0xdc 0x90 0x15 0x76 0x14 0x03 0x10
32nm SLC 8Gbit TC58NVG3SOFA00
0x98 0xd3 0x90 0x26 0x76 0x15 0x02 0x08
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Atmel PMECC support 2, 4, 8, 12, 24 bit error correction.
So if the ecc requirement in ONFI is <= 2, 4, 8, 12, 24.
We will use 2, 4, 8, 12, 24.
This patch fix the typo. Use '<=' replace '<'.
Reported-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The code for NAND_BUSWIDTH_AUTO is broken. According to Alexander:
"I have a problem with attach NAND UBI in 16 bit mode.
NAND works fine if I specify NAND_BUSWIDTH_16 option, but not
working with NAND_BUSWIDTH_AUTO option. In second case NAND
chip is identifyed with ONFI."
See his report for the rest of the details:
http://lists.infradead.org/pipermail/linux-mtd/2013-July/047515.html
Anyway, the problem is that nand_set_defaults() is called twice, we
intend it to reset the chip functions to their x16 buswidth verions
if the buswidth changed from x8 to x16; however, nand_set_defaults()
does exactly nothing if called a second time.
Fix this by hacking nand_set_defaults() to reset the buswidth-dependent
functions if they were set to the x8 version the first time. Note that
this does not do anything to reset from x16 to x8, but that's not the
supported use case for NAND_BUSWIDTH_AUTO anyway.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reported-by: Alexander Shiyan <shc_work@mail.ru>
Tested-by: Alexander Shiyan <shc_work@mail.ru>
Cc: Matthieu Castet <matthieu.castet@parrot.com>
Cc: <stable@vger.kernel.org> # v3.8+
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch proposes to remove kernel configuration parameters
defined in drivers/mtd/devices/Kconfig, but used nowhere
in the makefiles and source code (except in comments).
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Acked-by: Kees Cook <keescook@chromium.org>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Since commit ab78029 (drivers/pinctrl: grab default handles from device core),
we can rely on device core for setting the default pins. Compile tested only.
Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13)
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Since commit ab78029 (drivers/pinctrl: grab default handles from device core),
we can rely on device core for setting the default pins. Compile tested only.
Acked-by: Linus Walleij <linus.walleij@linaro.org> (personally at LCE13)
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
devm_ioremap_resource() checks its arguments, so there is no need for
explicitly checking the return value from platform_get_resource().
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
We don't have to issue a warning when a stronger error correcting
capability is chosen.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Tested-by: Roland Stigge <stigge@antcom.de>
Acked-by: Roland Stigge <stigge@antcom.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver core clears the driver data to NULL after device_release
or on probe failure, since commit 0998d06310
(device-core: Ensure drvdata = NULL when no driver is bound).
Thus, it is not needed to manually clear the device driver data to NULL.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This allows to support READID ONFI command which sends 0x20
as address together with the 0x90 READID command.
This is required to detect ONFI compliant devices.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch replaces cpu_is_pxa3xx() with of_machine_is_compatible()
which allows to build this driver for other platforms than ARCH_PXA.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Currently, the variable info->use_dma is never set and always
zero-valued which means the driver never does DMA transfers.
We fix this by simply setting info->use_dma to the module parameter,
also named 'use_dma'. Note that the module parameter has the same name,
but different semantics.
This fixes a regression introduced by the below commit
which removed the info->use_dma variable set.
commit 4eb2da8994
Author: Lei Wen <leiwen@marvell.com>
Date: Mon Feb 28 10:32:13 2011 +0800
mtd: pxa3xx_nand: unify prepare command
Before the above commit, the driver had use_dma=1 on all NAND commands
except on CMD_STATUS. This behavior is long lost and we are not
recovering in this patch, either.
This was spotted and verified by human inspection.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch will set the nand dma support in dts. Since we will not use
cpu_is_xxx() in nand driver. We needn't include the mach/cpu.h any more.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The nand driver use cpu_is_at32ap7000() macro for a workaround. For the
multi-platform support, we will remove this cpu_is_xxx() macro.
This patch adds a boolean variable need_reset_workaround in structure
atmel_nand_data. Using this variable we can remove cpu_is_at32ap7000() macro.
Hans-Christian: Feel free to push this through the mtd tree, if they won't
accept it I'm working on getting my workflow up on the linux-avr32.git tree.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Replace a call to deprecated devm_request_and_ioremap by devm_ioremap_resource.
Found with coccicheck and this semantic patch:
scripts/coccinelle/api/devm_request_and_ioremap.cocci.
Signed-off-by: Laurent Navet <laurent.navet@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Spansion's S34MLx chips support ONFI but not the GET/SET FEATURES calls.
Signed-off-by: David Mosberger <dmosberger@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Add nand bank selection and timings to the device tree bindings.
Signed-off-by: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
[Added some documentation]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Create a function to release the buffer and the dma channel, thus undoing
what pxa3xx_nand_init_buff() did. This commit makes the code more readable
and will allow to handle non-DMA capable platforms easier.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
clk_prepare_enable() can fail due to unknown reason.
Add a check for this and return the error code if it fails.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch converts the module to use clk_prepare_enable and
clk_disable_unprepare variants as required by common clock framework.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Replacing clk_get by managed devm_clk_get, the error path
can be greatly simplified.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Using the new devm_ioremap_resource() we can greatly
simplify resource handling.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch replaces the usage of loops in the nand_base code with
io{read,write}{8,16}_rep calls instead.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Patch converts driver to using resource-managed functions.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This controller only does ECC on full-page accesses, even though the
ECC consists of multiple steps. fsl_elbc_nand can get away with this
because the ECC of an all-0xff region will be all-0xff, but this is not
true with the ECC algorithms used by IFC.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Add CONFIG_PM_SLEEP to suspend/resume functions to fix the following
build warning when CONFIG_PM_SLEEP is not selected. This is because
sleep PM callbacks defined by SIMPLE_DEV_PM_OPS are only used when
the CONFIG_PM_SLEEP is enabled. Also, unnecessary CONFIG_PM ifdefs
are removed.
drivers/mtd/nand/fsmc_nand.c:1194:12: warning: 'fsmc_nand_suspend' defined but not used [-Wunused-function]
drivers/mtd/nand/fsmc_nand.c:1202:12: warning: 'fsmc_nand_resume' defined but not used [-Wunused-function]
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Add CONFIG_PM_SLEEP to suspend/resume functions to fix the following
build warning when CONFIG_PM_SLEEP is not selected. This is because
sleep PM callbacks defined by SIMPLE_DEV_PM_OPS are only used when
the CONFIG_PM_SLEEP is enabled. Also, unnecessary NULL defines are
removed.
drivers/mtd/nand/r852.c:1006:12: warning: 'r852_suspend' defined but not used [-Wunused-function]
drivers/mtd/nand/r852.c:1027:12: warning: 'r852_resume' defined but not used [-Wunused-function]
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The struct fsl_ifc_mtd is allocated with devm_kzalloc, so its memory
is "managed" automatically by the kernel. That is, we do not need to
free it explicitly; it will be freed when the device is removed. And we
*certainly* shouldn't free it with a regular kfree().
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The omap2 nand device driver calls into the the elm code, which can
be a loadable module, and in that case it cannot be built-in itself.
I can see no reason why the omap2 driver cannot also be a module,
so let's make the option "tristate" in Kconfig to fix this allmodconfig
build error:
ERROR: "elm_config" [drivers/mtd/nand/omap2.ko] undefined!
ERROR: "elm_decode_bch_error_page" [drivers/mtd/nand/omap2.ko] undefined!
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Cc: Afzal Mohammed <afzal@ti.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: linux-mtd@lists.infradead.org
devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
- Support partitions larger than 4GiB in device tree
- Support for new SPI chips
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.13 (GNU/Linux)
iEYEABECAAYFAlGLxzEACgkQdwG7hYl686M+PgCdHAn3fDzGW7gUL1tj43NCqaC8
PWoAoNAD5YpI3wYEBxped2MjSfgbQMvq
=hM2T
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20130509' of git://git.infradead.org/linux-mtd
Pull MTD update from David Woodhouse:
- Lots of cleanups from Artem, including deletion of some obsolete
drivers
- Support partitions larger than 4GiB in device tree
- Support for new SPI chips
* tag 'for-linus-20130509' of git://git.infradead.org/linux-mtd: (83 commits)
mtd: omap2: Use module_platform_driver()
mtd: bf5xx_nand: Use module_platform_driver()
mtd: denali_dt: Remove redundant use of of_match_ptr
mtd: denali_dt: Change return value to fix smatch warning
mtd: denali_dt: Use module_platform_driver()
mtd: denali_dt: Fix incorrect error check
mtd: nand: subpage write support for hardware based ECC schemes
mtd: omap2: use msecs_to_jiffies()
mtd: nand_ids: use size macros
mtd: nand_ids: improve LEGACY_ID_NAND macro a bit
mtd: add 4 Toshiba nand chips for the full-id case
mtd: add the support to parse out the full-id nand type
mtd: add new fields to nand_flash_dev{}
mtd: sh_flctl: Use of_match_ptr() macro
mtd: gpio: Use of_match_ptr() macro
mtd: gpio: Use devm_kzalloc()
mtd: davinci_nand: Use of_match_ptr()
mtd: dataflash: Use of_match_ptr() macro
mtd: remove h720x flash support
mtd: onenand: remove OneNAND simulator
...
GENERIC_GPIO now synonymous with GPIOLIB. There are no longer any valid
cases for enableing GENERIC_GPIO without GPIOLIB, even though it is
possible to do so which has been causing confusion and breakage. This
branch does the work to completely eliminate GENERIC_GPIO.
However, it is not trivial to just create a branch to remove it. Over
the course of the v3.9 cycle more code referencing GENERIC_GPIO has been
added to linux-next that conflicts with this branch. The following must
be done to resolve the conflicts when merging this branch into mainline:
* "git grep CONFIG_GENERIC_GPIO" should return 0 hits. Matches should be
replaced with CONFIG_GPIOLIB
* "git grep '\bGENERIC_GPIO\b'" should return 1 hit in the Chinese
documentation.
* Selectors of GENERIC_GPIO should be turned into selectors of GPIOLIB
* definitions of the option in architecture Kconfig code should be deleted.
Stephen has 3 merge fixup patches[1] that do the above. They are currently
applicable on mainline as of May 2nd.
[1] http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg428056.html
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRifUnAAoJEEFnBt12D9kBs2YP/0U6+ia+xYvkVaJc28PDVIzn
OReZNcJOYU8D5voxz0voaRD0EdcPwjbMu9Kp9aXMHlk4VxevF+8jCc/us0bIjtO1
VcB5VmSCIhMhxdnBlum11Mk7Vr5MCweyl9NBsypnPt8cl4obMBZHf2yzoodFktNb
wtyYlOb6FALtc6iDbOO6dG3w9F7FAOLvskUFzdv89m8mupTsBu9jw9NqFDbJHOex
rxq0Sdd+kWF/nkJVcV5Y6jIdletRlhpipefMJ9diexreHvwqh+c4kJEYZaXgB5+m
ha95cPbReK1d+RqzM3A8d4irzSVSmq4k7ijI6QkFOr48+AH7XsgKv5so885LKzMN
IIXg2Phm9i0H8+ecEvhcc4oIYBHJiEKK54Y0qUD9dqbFoDGPTCSqMHdSSMbpAY+J
bIIXlVzj1En3PPNUJLPt8q8Qz6WxCT9mDST3QSGYnD4o90HT+1R9j92RxGL6McOq
rUOyJDwmzFvpBvKK4raGdOU435M+ps2NPKKNIRaIGQPPY9rM1kN4YqvhXukEsC9L
3a3+3cQLh7iKxBHncxeQsJfethP1CPkJnzvF9r+ZZLf2rcPH4pbQIE2uO0XnX/nd
5/DKi0nGgAJ//GMMzdo3RiOA5zGFjIZ/KMvfhQldpP6qFJRhqdGi6FPlAcwr1z1n
YnCByPwwlvfC4LTXFOGL
=xodc
-----END PGP SIGNATURE-----
Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux
Pull removal of GENERIC_GPIO from Grant Likely:
"GENERIC_GPIO now synonymous with GPIOLIB. There are no longer any
valid cases for enableing GENERIC_GPIO without GPIOLIB, even though it
is possible to do so which has been causing confusion and breakage.
This branch does the work to completely eliminate GENERIC_GPIO."
* tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux:
gpio: update gpio Chinese documentation
Remove GENERIC_GPIO config option
Convert selectors of GENERIC_GPIO to GPIOLIB
blackfin: force use of gpiolib
m68k: coldfire: use gpiolib
mips: pnx833x: remove requirement for GENERIC_GPIO
openrisc: default GENERIC_GPIO to false
avr32: default GENERIC_GPIO to false
xtensa: remove explicit selection of GENERIC_GPIO
sh: replace CONFIG_GENERIC_GPIO by CONFIG_GPIOLIB
powerpc: remove redundant GENERIC_GPIO selection
unicore32: default GENERIC_GPIO to false
unicore32: remove unneeded select GENERIC_GPIO
arm: plat-orion: use GPIO driver on CONFIG_GPIOLIB
arm: remove redundant GENERIC_GPIO selection
mips: alchemy: require gpiolib
mips: txx9: change GENERIC_GPIO to GPIOLIB
mips: loongson: use GPIO driver on CONFIG_GPIOLIB
mips: remove redundant GENERIC_GPIO select
GENERIC_GPIO is now equivalent to GPIOLIB and features that depended on
GENERIC_GPIO can now depend on GPIOLIB to allow removal of this option.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
module_platform_driver macro removes some boilerplate and makes
the code simpler.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Since this driver is dt only and denali_nand_dt_ids is always
compiled in, use of of_match_ptr() macro is not necessary.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
platform_get_irq() also returns -ENXIO upon failure.
Use it instead of hardcoded return type.
Fixes the following smatch warning:
drivers/mtd/nand/denali_dt.c:93 denali_dt_probe() info:
why not propagate 'denali->irq' from platform_get_irq() instead of (-6)?
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
module_platform_driver() removes some boilerplate and makes the code
simpler.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The return value of devm_ioremap_nocache should be checked here instead
of res.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch adds support for subpage (partial-page) writes when using
hardware based ECC schemes.
Advantages:
(1) reduces storage overhead when using file-systems like UBIFS, which
store LEB header at page-size granularity.
(2) allows independent subpage writes, thereby increasing NAND storage
efficiency for non-page aligned data.
+ updated cafe_nand and lpc32xx_mlc NAND drivers for change in
chip->write_page interface.
Signed-off-by: Gupta, Pekon <pekon@ti.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Fix mtd-utils from returning -EIO. Formatting jffs2 filesystem was impossible
when CONFIG_HZ was set to a low value.
Signed-off-by: Toan Pham <tpham3783@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Use the convenient 'SZ_8K' and 'SZ_16K' macros for the eraseblock size in the
NAND IDs table. This is a little more readable.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Notice that all the flashes belonging to the "legacy ID" class have 512 bytes
NAND page. This means we may simplify the 'LEGACY_ID_NAND()' macro as well as
the NAND ID table a little.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
I have 4 Toshiba nand chips which can not be parsed out by the
id data. We can not get the oob size from the id data. So add them
as the full-id nand chips in the first of nand_flash_ids.
The comment for the full-id items is from Brian.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Reviewed-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When we meet a full-id nand type whose @id_len is not zero, we can use
the find_full_id_nand() to parse out the necessary information for a
nand chip.
If we meet a non full-id nand type, we can handle it in the legacy way.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Reviewed-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This eliminates having an #ifdef returning NULL for the case
when OF is disabled.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This eliminates having an #ifdef returning NULL for the case
when OF is disabled.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
devm_kzalloc() is device managed and makes cleanup simpler.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This eliminates having an #ifdef returning NULL for the case
when OF is disabled.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This driver is marked as broken for 2 years, and no one cares to make it
compile and work. Now it is time to zap it.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This driver has been marked as broken for long time and it depends on a
non-existing PPCHAMELEONEVB Kconfig symbol.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch uses module_platform_driver_probe() macro which makes
the code smaller and simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch uses module_platform_driver_probe() macro which makes
the code smaller and simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch uses module_platform_driver_probe() macro which makes
the code smaller and simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch uses module_platform_driver_probe() macro which makes
the code smaller and simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch uses module_platform_driver_probe() macro which makes
the code smaller and simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch uses module_platform_driver_probe() macro which makes
the code smaller and simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch uses module_platform_driver_probe() macro which makes
the code smaller and simpler.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
In case the driver is not probed - due to config mismatches or errors
in the DTS files - dev_get_drvdata() returns NULL, leading to an Ooops
during boot.
Make elm_config() return an error in such cases to propagate the error
up to the user, so it can fall back to software mode.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Variable "onfi_version" is already set to zero before nand_flash_detect_onfi()
call, so additional cleaning is not necessary.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
NAND command, passed to cmd_ctrl(), is masked with 0xff. This patch
removes this since masking is not necessary and masking is not performed
in other places for same call.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Introduce helper macros for defining NAND chips. These macros do not really add
much value in the current code-base. However, we are going to add full ID
support which adds some more complexity to the table, and helper macros become
useful for readability.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
NAND flashes with 256 bytes NAND pages are so old that probably do not exist
any more. Let's remove few related pieces of code and forget about them
forever. The assumption will be that 512 bytes NAND page size is the minimum
possible.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The 'id' is a bit confusing name because NAND IDs are multi-byte. Re-name
it to 'dev_id' to make it clear that this is the "device ID" part (the second
byte).
While on it, clean-up the commentary for 'struct nand_flash_dev'.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
We have this unused macro, let's use it and justify its existence.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
We have only one AG-AND driver and it was not touched since 2005. It looks
like AG-AND was not really make it to mass-production and can be considered
a dead technology.
Along with the AG-AND support, this patch removes the BBT_AUTO_REFRESH feature,
because the only user of this feature is AG-AND. And even though it is
implemented as a generic feature, I prefer to remove it because NAND flashes do
not really need it in this form.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The AG-AND support is about to be removed from MTD, because this technology is
dead for long time. Thus, remove this the only AG-AND driver we have in the
kernel tree.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The MTD subsystem has its own small museum of ancient NANDs in a form of the
CONFIG_MTD_NAND_MUSEUM_IDS configuration option. The museum contains stone age
NANDs with 256 bytes pages, as well as iron age NANDs with 512 bytes per page
and up to 8MiB page size.
It is with great sorrow that I inform you that the museum is being
decommissioned. The MTD subsystem is out of budget for Kconfig options and
already has too many of them, and there is a general kernel trend to simplify
the configuration menu.
We remove the stone age exhibits along with closing the museum, but some of the
iron age ones are transferred to the regular NAND depot. Namely, only those
which have unique device IDs are transferred, and the ones which have
conflicting device IDs are removed.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Clean-up the code a little bit:
* clean-up commentaries.
* move macro definitions to the top of the file.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
With the generic DMA device tree helper supported by mxs-dma driver,
client devices only need to call dma_request_slave_channel() for
requesting a DMA channel from dmaengine.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
This partially reverts commit 1696e6bc2a
("mtd: nand: kill NAND_NO_READRDY").
In that patch I overlooked a few things.
The original documentation for NAND_NO_READRDY included "True for all
large page devices, as they do not support autoincrement." I was
conflating "not support autoincrement" with the NAND_NO_AUTOINCR option,
which was in fact doing nothing. So, when I dropped NAND_NO_AUTOINCR, I
concluded that I then could harmlessly drop NAND_NO_READRDY. But of
course the fact the NAND_NO_AUTOINCR was doing nothing didn't mean
NAND_NO_READRDY was doing nothing...
So, NAND_NO_READRDY is re-introduced as NAND_NEED_READRDY and applied
only to those few remaining small-page NAND which needed it in the first
place.
Cc: stable@kernel.org [3.5+]
Reported-by: Alexander Shiyan <shc_work@mail.ru>
Tested-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* misc clean-ups in the MTD command-line partitioning parser (cmdlinepart)
* add flash locking support for STmicro chips serial flash chips, as well as
for CFI command set 2 chips.
* new driver for the ELM error correction HW module found in various TI chips,
enable the OMAP NAND driver to use the ELM HW error correction
* added number of new serial flash IDs
* various fixes and improvements in the gpmi NAND driver
* bcm47xx NAND driver improvements
* make the mtdpart module actually removable
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.13 (GNU/Linux)
iEYEABECAAYFAlExEs8ACgkQdwG7hYl686Oa+gCgiBNt+I0MiixDeN+MGuE1uw9s
i2wAniD9sR2HDy6y5SkbdXK/aPr8ez/p
=xV1l
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20130301' of git://git.infradead.org/linux-mtd
Pull MTD update from David Woodhouse:
"Fairly unexciting MTD merge for 3.9:
- misc clean-ups in the MTD command-line partitioning parser
(cmdlinepart)
- add flash locking support for STmicro chips serial flash chips, as
well as for CFI command set 2 chips.
- new driver for the ELM error correction HW module found in various
TI chips, enable the OMAP NAND driver to use the ELM HW error
correction
- added number of new serial flash IDs
- various fixes and improvements in the gpmi NAND driver
- bcm47xx NAND driver improvements
- make the mtdpart module actually removable"
* tag 'for-linus-20130301' of git://git.infradead.org/linux-mtd: (45 commits)
mtd: map: BUG() in non handled cases
mtd: bcm47xxnflash: use pr_fmt for module prefix in messages
mtd: davinci_nand: Use managed resources
mtd: mtd_torturetest can cause stack overflows
mtd: physmap_of: Convert device allocation to managed devm_kzalloc()
mtd: at91: atmel_nand: for PMECC, add code to check the ONFI parameter ECC requirement.
mtd: atmel_nand: make pmecc-cap, pmecc-sector-size in dts is optional.
mtd: atmel_nand: avoid to report an error when lookup table offset is 0.
mtd: bcm47xxsflash: adjust names of bus-specific functions
mtd: bcm47xxpart: improve probing of nvram partition
mtd: bcm47xxpart: add support for other erase sizes
mtd: bcm47xxnflash: register this as normal driver
mtd: bcm47xxnflash: fix message
mtd: bcm47xxsflash: register this as normal driver
mtd: bcm47xxsflash: write number of written bytes
mtd: gpmi: add sanity check for the ECC
mtd: gpmi: set the Golois Field bit for mx6q's BCH
mtd: devices: elm: Removes <xx> literals in elm DT node
mtd: gpmi: fix a dereferencing freed memory error
mtd: fix the wrong timeo for panic_nand_wait()
...
Pull vfs pile (part one) from Al Viro:
"Assorted stuff - cleaning namei.c up a bit, fixing ->d_name/->d_parent
locking violations, etc.
The most visible changes here are death of FS_REVAL_DOT (replaced with
"has ->d_weak_revalidate()") and a new helper getting from struct file
to inode. Some bits of preparation to xattr method interface changes.
Misc patches by various people sent this cycle *and* ocfs2 fixes from
several cycles ago that should've been upstream right then.
PS: the next vfs pile will be xattr stuff."
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: (46 commits)
saner proc_get_inode() calling conventions
proc: avoid extra pde_put() in proc_fill_super()
fs: change return values from -EACCES to -EPERM
fs/exec.c: make bprm_mm_init() static
ocfs2/dlm: use GFP_ATOMIC inside a spin_lock
ocfs2: fix possible use-after-free with AIO
ocfs2: Fix oops in ocfs2_fast_symlink_readpage() code path
get_empty_filp()/alloc_file() leave both ->f_pos and ->f_version zero
target: writev() on single-element vector is pointless
export kernel_write(), convert open-coded instances
fs: encode_fh: return FILEID_INVALID if invalid fid_type
kill f_vfsmnt
vfs: kill FS_REVAL_DOT by adding a d_weak_revalidate dentry op
nfsd: handle vfs_getattr errors in acl protocol
switch vfs_getattr() to struct path
default SET_PERSONALITY() in linux/elf.h
ceph: prepopulate inodes only when request is aborted
d_hash_and_lookup(): export, switch open-coded instances
9p: switch v9fs_set_create_acl() to inode+fid, do it before d_instantiate()
9p: split dropping the acls from v9fs_set_create_acl()
...
Pull slave-dmaengine updates from Vinod Koul:
"This is fairly big pull by my standards as I had missed last merge
window. So we have the support for device tree for slave-dmaengine,
large updates to dw_dmac driver from Andy for reusing on different
architectures. Along with this we have fixes on bunch of the drivers"
Fix up trivial conflicts, usually due to #include line movement next to
each other.
* 'next' of git://git.infradead.org/users/vkoul/slave-dma: (111 commits)
Revert "ARM: SPEAr13xx: Pass DW DMAC platform data from DT"
ARM: dts: pl330: Add #dma-cells for generic dma binding support
DMA: PL330: Register the DMA controller with the generic DMA helpers
DMA: PL330: Add xlate function
DMA: PL330: Add new pl330 filter for DT case.
dma: tegra20-apb-dma: remove unnecessary assignment
edma: do not waste memory for dma_mask
dma: coh901318: set residue only if dma is in progress
dma: coh901318: avoid unbalanced locking
dmaengine.h: remove redundant else keyword
dma: of-dma: protect list write operation by spin_lock
dmaengine: ste_dma40: do not remove descriptors for cyclic transfers
dma: of-dma.c: fix memory leakage
dw_dmac: apply default dma_mask if needed
dmaengine: ioat - fix spare sparse complain
dmaengine: move drivers/of/dma.c -> drivers/dma/of-dma.c
ioatdma: fix race between updating ioat->head and IOAT_COMPLETION_PENDING
dw_dmac: add support for Lynxpoint DMA controllers
dw_dmac: return proper residue value
dw_dmac: fill individual length of descriptor
...
These are device tree conversions for a number of platforms,
with the intention of turning code from board files into
device tree descriptions. Notable changes are:
* davinci bindings for pinctrl, MTD, RTC, watchdog and i2c
* nomadik bindings for all devices, removing the board files
* bcm2835 bindings for mmc and i2c
* tegra bindings for hdmi, keyboard, audio, as well as some updates
* at91 bindings for hardware ecc and for devices on RM9200
* mxs bindings for cfa100xx
* sunxi support for Miniand Hackberry board
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAUSUyRWCrR//JCVInAQKjPg/6AlHFCcLd2ZNjbp/br9uY9VGDTXC8XBJP
aIlEIujOi8PZUzyOK+RfAbMtI9EYlFIM1angoQE2x4E8Wf/5bh0zMD1qdsndhceV
acBGcUug4hv1OBFU+VZNNHu+WzcbiWIwNPXGksIOZpgkYJ+6P2BqVdv/HgwdKiJD
/Qo5iO6qNeYW387DcVXY5GoDhof56WtsUkb7VrXn5z/ewTq+xu+GuDaAtdsKjHyW
hjsAjv6BCCf4fKjxGVhePdVqMtTv3pwVQO0B3DuXdNLESecpTobin/jc+oCSY9Yy
LI21KOjjwYYQahwVsNp2sMcfmbVzeOyHqITF/Qt11OY4YtPbf4OBPM61TDqIYlJ3
0PoBtm4AL24wiKSCSiQNn6k7woW531r65lqpGOKYoglGYo50gCvxzsBZYkGzpEkV
7JmUm76Ohppk5QDhO/pIQBFE783IA9rjMg+aPc0SDDwrr499iGBZ2nM7s75MThkm
EjHpf4O8JYsXj9KANo9D5cL4zupdnH1jm+qhD8zl9w7EBQXJ6zXy38FaUy04Lgr1
NkHEtwlAeNJ0W6qpu89cNZEaerzeF6uzEFgp06dMwy8X+/NTCLXM1kCJC+mytW83
aFYDlQedqnXeh9fDCrkbYDA8HGKZm0ENxoLOx40iqF761h8cBfhfCIEObClKhXy2
mGBl4NF5ZAU=
=NLEa
-----END PGP SIGNATURE-----
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree conversions from Arnd Bergmann:
"These are device tree conversions for a number of platforms, with the
intention of turning code from board files into device tree
descriptions. Notable changes are:
- davinci bindings for pinctrl, MTD, RTC, watchdog and i2c
- nomadik bindings for all devices, removing the board files
- bcm2835 bindings for mmc and i2c
- tegra bindings for hdmi, keyboard, audio, as well as some updates
- at91 bindings for hardware ecc and for devices on RM9200
- mxs bindings for cfa100xx
- sunxi support for Miniand Hackberry board"
* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (72 commits)
Revert "sunxi: a10-cubieboard: Add user LEDs to the device tree"
Revert "sunxi: a13-olinuxino: Add user LED to the device tree"
clk: tegra: initialise parent of uart clocks
ARM: tegra: remove clock-frequency properties from serial nodes
clk: tegra: fix driver to match DT binding
clk: tegra: local arrays should be static
clk: tegra: Add missing spinlock for hclk and pclk
clk: tegra: Implement locking for super clock
clk: tegra: fix wrong clock index between se to sata_cold
sunxi: a13-olinuxino: Add user LED to the device tree
ARM: davinci: da850 DT: add support for machine reboot
ARM: davinci: da850: add wdt DT node
ARM: davinci: da850: add DT node for I2C0
ARM: at91: at91sam9n12: add DT parameters to enable PMECC
ARM: at91: at91sam9x5: add DT parameters to enable PMECC
ARM: at91: add EMAC bindings to RM9200 DT
ARM: at91: add SSC bindings to RM9200 DT
ARM: at91: add MMC bindings to RM9200 DT
ARM: at91: Animeo IP: enable watchdog support
ARM: nomadik: fix OF compilation regression
...
* Updates to the ux500 cpufreq code
* Moving the u300 DMA controller driver to drivers/dma
* Moving versatile express drivers out of arch/arm for sharing with arch/arm64
* Device tree bindings for the OMAP General Purpose Memory Controller
There is a simple conflict in drivers/cpufreq/dbx500-cpufreq.c, because
the mach/id.h header and the cpu_is_u8500_family() function in it are
now gone.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAUSaEc2CrR//JCVInAQKROg//V6LrAmewM4ugCLJFOHDsRN5n27QHOnMb
7g1b56OVtwb+Zer9HLAyZyY6MX12JbDTdC53LDWf6CEU8Z3LfdaPNXyDoGwKQMsA
cq2qDufcFoVnaAFMO4uxpe/Y/ZuJJTPm+24dviztMp5PIl4gRkgou5w2fRzd7iLk
rETnjvDzB1lKrlrTlnEoPemroErX10AhkjGIQ1zkImqlCOUL1Fs+IMui5gUA3I8X
S7q+JPMoIjCFUtuG9QV+/PWcY0SnsGJBZiYdh1XGbCiint5Oi/6hawbBtT4L067H
HfSsWe+mx8c2B84V0AFOpKcV6v9VYeyxSkmr40yG3laPReGA8CWjjGQj1kIkyY07
1XujeEjbpp4zgaggtv9Jdb7BAPWWopuqMrpGdcuxBWYN7HwiPoseGzJMo3F7D5Ti
KBRsBLDoK514oGLZdgh3i/QQZwhFuJRcHdaoqRU0pWNJBKMxAFdfgeKYdNWtB7HA
XrtJvANrrIeKin3bbeodlhaHLxlBImarQjqdK85H0nmLs71jNphihDRVe3wNy5Qu
OYbVHbf3cIboIQiLYLgiVc4NxypCXzeAB6pCdX/NWee9P2qgDCb0SEI6OcpBftPh
di004nMEquomIkoyNSlAZffcxeUrHiFlqSvHWqzuLqLCGRToxaoWUC0ES3qJA321
23zzC9IYF6Y=
=R0p0
-----END PGP SIGNATURE-----
Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver specific changes from Arnd Bergmann:
- Updates to the ux500 cpufreq code
- Moving the u300 DMA controller driver to drivers/dma
- Moving versatile express drivers out of arch/arm for sharing with arch/arm64
- Device tree bindings for the OMAP General Purpose Memory Controller
* tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (27 commits)
ARM: OMAP2+: gpmc: Add device tree documentation for elm handle
ARM: OMAP2+: gpmc: add DT bindings for OneNAND
ARM: OMAP2+: gpmc-onenand: drop __init annotation
mtd: omap-onenand: pass device_node in platform data
ARM: OMAP2+: Prevent potential crash if GPMC probe fails
ARM: OMAP2+: gpmc: Remove unneeded of_node_put()
arm: Move sp810.h to include/linux/amba/
ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs
ARM: OMAP: gpmc-nand: drop __init annotation
mtd: omap-nand: pass device_node in platform data
ARM: OMAP: gpmc: don't create devices from initcall on DT
dma: coh901318: cut down on platform data abstraction
dma: coh901318: merge header files
dma: coh901318: push definitions into driver
dma: coh901318: push header down into the DMA subsystem
dma: coh901318: skip hard-coded addresses
dma: coh901318: remove hardcoded target addresses
dma: coh901318: push platform data into driver
dma: coh901318: create a proper platform data file
...
Here is the big driver core merge for 3.9-rc1
There are two major series here, both of which touch lots of drivers all
over the kernel, and will cause you some merge conflicts:
- add a new function called devm_ioremap_resource() to properly be
able to check return values.
- remove CONFIG_EXPERIMENTAL
If you need me to provide a merged tree to handle these resolutions,
please let me know.
Other than those patches, there's not much here, some minor fixes and
updates.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iEYEABECAAYFAlEmV0cACgkQMUfUDdst+yncCQCfbmnQZju7kzWXk6PjdFuKspT9
weAAoMCzcAtEzzc4LXuUxxG/sXBVBCjW
=yWAQ
-----END PGP SIGNATURE-----
Merge tag 'driver-core-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core
Pull driver core patches from Greg Kroah-Hartman:
"Here is the big driver core merge for 3.9-rc1
There are two major series here, both of which touch lots of drivers
all over the kernel, and will cause you some merge conflicts:
- add a new function called devm_ioremap_resource() to properly be
able to check return values.
- remove CONFIG_EXPERIMENTAL
Other than those patches, there's not much here, some minor fixes and
updates"
Fix up trivial conflicts
* tag 'driver-core-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (221 commits)
base: memory: fix soft/hard_offline_page permissions
drivercore: Fix ordering between deferred_probe and exiting initcalls
backlight: fix class_find_device() arguments
TTY: mark tty_get_device call with the proper const values
driver-core: constify data for class_find_device()
firmware: Ignore abort check when no user-helper is used
firmware: Reduce ifdef CONFIG_FW_LOADER_USER_HELPER
firmware: Make user-mode helper optional
firmware: Refactoring for splitting user-mode helper code
Driver core: treat unregistered bus_types as having no devices
watchdog: Convert to devm_ioremap_resource()
thermal: Convert to devm_ioremap_resource()
spi: Convert to devm_ioremap_resource()
power: Convert to devm_ioremap_resource()
mtd: Convert to devm_ioremap_resource()
mmc: Convert to devm_ioremap_resource()
mfd: Convert to devm_ioremap_resource()
media: Convert to devm_ioremap_resource()
iommu: Convert to devm_ioremap_resource()
drm: Convert to devm_ioremap_resource()
...
davinci_nand driver currently uses normal kzalloc, ioremap and get_clk
routines. This patch replaces these routines with devm_kzalloc,
devm_request_and_ioremap and devm_clk_get resp.
Signed-off-by: Mrugesh Katepallewar <mrugesh.mk@ti.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This patch will check NAND flash's ecc minimum requirement in ONFI parameter.
1. if pmecc-cap, pmecc-sector-size is set in dts. then use it. Driver will
print out a WARNING if the values are different from ONFI parameters.
2. if pmecc-cap, pmecc-sector-size is not set in dts, then use the value
from ONFI parameters.
* If ONFI ECC parameters are in ONFI extended parameter page, since we are
not support it, so assume the minimum ecc requirement is 2 bits in 512
bytes.
* For non-ONFI support nand flash, also assume the minimum ecc requirement is
2 bits in 512 bytes.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
If those two are not specified in dts file, driver will report an error.
TODO: in this case, driver will find ecc requirement in NAND ONFI parameters.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Before this patch, we assume the whole ROM code are mapping to memory. So
it is wrong if the lookup table offset is 0.
After this patch, we can map only the lookup table of ROM code to memory
intead of the whole ROM code (about 1M). In this case, one lookup table
offset can be 0.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
When platform_driver_probe() is used and no device is registered for
this driver -ENODEV is returned and and error message is shown. Not all
BCM47xx SoC have a nand flash chip controller and chip and for them an
error message was shown.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This is not a serial flash driver, but a nand flash driver
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
We do the check based on the following two facts:
[1] The mx23/mx28 can only support 20-bits ECC, while the mx6
can supports 40-bits ECC.
[2] The mx23/mx28 can only support the GF13, while the mx6
can supports GF13 and GF14.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The GF13 can be only used in the following case:
The ECC data chunk is less then 1K bytes.
In mx23/mx28, the ecc data chunk is 512 bytes. So it is okay.
But in mx6q, we begin to use some large nand chip whose ecc
data chunk maybe 1K bytes long. So when the data chunk is 1K bytes,
we have to use the GF14.
This patch sets the Golois Field bit when the GF14 is needed.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The panic_nand_wait() expects the timeo in ms and not in jiffies.
But in nand_wait(), the timeo for panic_nand_wait() is assigned with
wrong value(jiffies + some delay). The timeo should be set like the
panic_nand_write() does.
This patch passes timeo in ms to panic_nand_wait().
And this patch also passes timeo in jiffies(converted by msecs_to_jiffies)
to time_before() which makes the code more readable.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Add the function name to the error message.
These messages are not very helpful:
[183356.176682] uncorrectable error :
[183356.180273] uncorrectable error :
[183356.184194] uncorrectable error :
[183356.187773] uncorrectable error :
[183356.191280] uncorrectable error :
Artem: amended the patch a bit
Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
in/out_be32 accessors are Power arch centric whereas
ioread/writebe32 are available in other arches.
Since the IFC device registers are annotated big endian in
fsl_ifc.h, the accessor annotations now match, resulting in the
pleasant side-effect of this patch silencing sparse endian
warnings such as the following:
drivers/mtd/nand/fsl_ifc_nand.c:179:19: warning: incorrect type in argument 1 (different base types)
drivers/mtd/nand/fsl_ifc_nand.c:179:19: expected unsigned int volatile [noderef] [usertype] <asn:2>*addr
drivers/mtd/nand/fsl_ifc_nand.c:179:19: got restricted __be32 [noderef] <asn:2>*<noident>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
ELM module can be used for hardware error correction of BCH 4 & 8 bit.
ELM module functionality is verified by checking the availability of
handle for ELM module in device tree. Hence supporting
1. ELM module available, BCH error correction done by ELM module. Also
support read & write page in one shot by adding custom read_page and
write_page methods. This helps in optimizing code for NAND flashes with
page size less than 4 KB.
2. If ELM module not available fall back to software BCH error
correction support.
New structure member is added to omap_nand_info
1. "is_elm_used" to know the status of whether the ELM module is used for
error correction or not.
2. "elm_dev" device pointer to elm device on detection of ELM module.
Also being here update the device tree documentation of gpmc-nand for
adding optional property elm_id.
Note:
ECC layout uses 1 extra bytes for 512 byte of data to handle erased
pages. Extra byte programmed to zero for programmed pages. Also BCH8
requires 14 byte ecc to maintain compatibility with RBL ECC layout.
This results a common ecc layout across RBL, U-boot & Linux with BCH8.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Remove check of ecc bytes with 13, number of errors can directly update
from nand ecc strength. This will increase re-usability of the code.
Also add macro definitions BCH8_ERROR_MAX & BCH4_ERROR_MAX for better
readability and cleaner code.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Also compress the id in case of a v3 NAND flash controller (i.mx51, i.mx53)
and 16Bit buswidth.
Signed-off-by: Roman Schneider <schneider@at.festo.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Use more preferable function name which implies using a pseudo-random
number generator.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Always report corrected and failed ECC stats back up to the MTD layer. Also
return max_bitflips from read_page() as is expected from NAND drivers now.
Signed-off-by: Zach Sadecki <zsadecki@itwatchdogs.com>
Acked-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Commit cdeadd712f (mtd: nand: davinci: add OF
support for davinci nand controller) has never been really build tested with
the driver as a module. When the driver is built-in, the missing semicolon
after structure initializer is "compensated" by MODULE_DEVICE_TABLE() macro
being empty and so the initializer using the trailing semicolon on the next
line; when the driver is built as a module, compilation error ensues, and as
the 'davinci_all_defconfig' has the NAND driver modular, this error prevents
DaVinci family kernel from building...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Cc: stable@vger.kernel.org # 3.7
This adds the FSMC NAND driver and flash partitions to the Nomadik
device tree.
The only compatible string accepted by this driver is currently
"st,spear600-fsmc-nand" which is inappropriate for this system, so
this patch adds the compatible value "stericsson,fsmc-nand" as
well.
Cc: linux-mtd@vger.kernel.org
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Artem Bityutskiy <dedekind1@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Convert all uses of devm_request_and_ioremap() to the newly introduced
devm_ioremap_resource() which provides more consistent error handling.
devm_ioremap_resource() provides its own error messages so all explicit
error messages can be removed from the failure code paths.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Cc: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Commit ff3206b245 ('mtd: nand: onfi need
to be probed in 8 bits mode') adds a WARN if the onfi probe is in 16
bits mode. This allows to detect driver that need to be fixed, but this
is a bit noisy¹. Transform the WARN in a pr_err.
¹ http://article.gmane.org/gmane.linux.ports.arm.omap/91317
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Pass an optional device_node pointer in the platform data, which in turn
will be put into a mtd_part_parser_data. This way, code that sets up the
platform devices can pass along the node from DT so that the partitions
can be parsed.
For non-DT boards, this change has no effect.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Artem Bityutskiy <dedekind1@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The CONFIG_EXPERIMENTAL config item has not carried much meaning for a
while now and is almost always enabled by default. As agreed during the
Linux kernel summit, remove it from any "depends on" lines in Kconfigs.
CC: David Woodhouse <dwmw2@infradead.org>
CC: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
CC: Huang Shijie <b32955@freescale.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Shubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Acked-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com>
Commit cdeadd712f (mtd: nand: davinci: add OF
support for davinci nand controller) has never been really build tested with
the driver as a module. When the driver is built-in, the missing semicolon
after structure initializer is "compensated" by MODULE_DEVICE_TABLE() macro
being empty and so the initializer using the trailing semicolon on the next
line; when the driver is built as a module, compilation error ensues, and as
the 'davinci_all_defconfig' has the NAND driver modular, this error prevents
DaVinci family kernel from building...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Cc: stable@vger.kernel.org # 3.7
Make dma_xfer() do DMA unmapping itself and fix handling
of failure cases.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Dan Williams <djbw@fb.com>
CONFIG_HOTPLUG is going away as an option. As a result, the __dev*
markings need to be removed.
This change removes the use of __devinit, __devexit_p, and __devexit
from these drivers.
Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.
Cc: Bill Pemberton <wfp5p@virginia.edu>
Cc: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Recently imlemented writing support has shown that current num of
retries is too low. Writing requires longer waiting than simple reading.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
- Various cleanups especially in NAND tests
- Add support for NAND flash on BCMA bus
- DT support for sh_flctl and denali NAND drivers
- Kill obsolete/superceded drivers (fortunet, nomadik_nand)
- Fix JFFS2 locking bug in ENOMEM failure path
- New SPI flash chips, as usual
- Support writing in 'reliable mode' for DiskOnChip G4
- Debugfs support in nandsim
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iEYEABECAAYFAlDSAa4ACgkQdwG7hYl686MMcACeNYa//ghPtccb5L+IRXsqaFDL
Yi4AoLWOaOjN8qM4KUF/bfMEkwNGAePz
=DaAQ
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20121219' of git://git.infradead.org/linux-mtd
Pull MTD updates from David Woodhouse:
- Various cleanups especially in NAND tests
- Add support for NAND flash on BCMA bus
- DT support for sh_flctl and denali NAND drivers
- Kill obsolete/superceded drivers (fortunet, nomadik_nand)
- Fix JFFS2 locking bug in ENOMEM failure path
- New SPI flash chips, as usual
- Support writing in 'reliable mode' for DiskOnChip G4
- Debugfs support in nandsim
* tag 'for-linus-20121219' of git://git.infradead.org/linux-mtd: (96 commits)
mtd: nand: typo in nand_id_has_period() comments
mtd: nand/gpio: use io{read,write}*_rep accessors
mtd: block2mtd: throttle writes by calling balance_dirty_pages_ratelimited.
mtd: nand: gpmi: reset BCH earlier, too, to avoid NAND startup problems
mtd: nand/docg4: fix and improve read of factory bbt
mtd: nand/docg4: reserve bb marker area in ecclayout
mtd: nand/docg4: add support for writing in reliable mode
mtd: mxc_nand: reorder part_probes to let cmdline override other sources
mtd: mxc_nand: fix unbalanced clk_disable() in error path
mtd: nandsim: Introduce debugfs infrastructure
mtd: physmap_of: error checking to prevent a NULL pointer dereference
mtg: docg3: potential divide by zero in doc_write_oob()
mtd: bcm47xxnflash: writing support
mtd: tests/read: initialize buffer for whole next page
mtd: at91: atmel_nand: return bit flips for the PMECC read_page()
mtd: fix recovery after failed write-buffer operation in cfi_cmdset_0002.c
mtd: nand: onfi need to be probed in 8 bits mode
mtd: nand: add NAND_BUSWIDTH_AUTO to autodetect bus width
mtd: nand: print flash size during detection
mted: nand_wait_ready timeout fix
...
This also removes unnecessary memset call which is immediately overwritten
with random bytes.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Artem Bityutskiy <dedekind1@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: "Theodore Ts'o" <tytso@mit.edu>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: David Laight <david.laight@aculab.com>
Cc: Eilon Greenstein <eilong@broadcom.com>
Cc: Michel Lespinasse <walken@google.com>
Cc: Robert Love <robert.w.love@intel.com>
Cc: Valdis Kletnieks <valdis.kletnieks@vt.edu>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Pull trivial branch from Jiri Kosina:
"Usual stuff -- comment/printk typo fixes, documentation updates, dead
code elimination."
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (39 commits)
HOWTO: fix double words typo
x86 mtrr: fix comment typo in mtrr_bp_init
propagate name change to comments in kernel source
doc: Update the name of profiling based on sysfs
treewide: Fix typos in various drivers
treewide: Fix typos in various Kconfig
wireless: mwifiex: Fix typo in wireless/mwifiex driver
messages: i2o: Fix typo in messages/i2o
scripts/kernel-doc: check that non-void fcts describe their return value
Kernel-doc: Convention: Use a "Return" section to describe return values
radeon: Fix typo and copy/paste error in comments
doc: Remove unnecessary declarations from Documentation/accounting/getdelays.c
various: Fix spelling of "asynchronous" in comments.
Fix misspellings of "whether" in comments.
eisa: Fix spelling of "asynchronous".
various: Fix spelling of "registered" in comments.
doc: fix quite a few typos within Documentation
target: iscsi: fix comment typos in target/iscsi drivers
treewide: fix typo of "suport" in various comments and Kconfig
treewide: fix typo of "suppport" in various comments
...
This branch contains a largeish set of updates of power management and
clock setup. The bulk of it is for OMAP/AM33xx platforms, but also a
few around hotplug/suspend/resume on Exynos.
It includes a split-up of some of the OMAP clock data into separate
files which adds to the diffstat, but gross delta is fairly reasonable.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJQySrdAAoJEIwa5zzehBx3XBMQAJCgrE/I1vbuiENiVMLpQkN7
0Y5t89SwoALnme5jsM8vW/H0o6b163FfH+249UNs6dyk6MdCqqSv8cQVvSfCKRKn
m4JTXS6njSnYgU025klNU9W3FyMuFcgH8b63+c5+sCcqfvdkxrjpNoKqAYNxQlgJ
6DHgHCKZP3JB1e2EFqViw0GJgZIjTNxlWvx8XLcAShSapQ+Ovq/iAcKo41o7ZadB
4zV//VkBMv0TLNTs6SoR0EO8qM+2nIUKE8fgPrRxvvb98tuasKPvlSq9VUeIjnYk
kWjNTQYbD1IkrAMPYrwcpLU3xkEr14wrKDBtPK6GdCDcXzdyKq3fzROOXNsqrLmn
Y8PkY+J39B59F0DKjyrCjasZyi0tQQV6ps5Xm2X2CB003GWEbo1yu+BodShYEyaL
7OvkLiVpOtq+LOYcsScHtOGdO9le2O3yZevNRvlrCDCvJUYbXNjaM9ZrWcQuTlJc
oseYNSRPaIP5PMv2c+Xup9qh/dyAjj8g6gSi9BlDvwVOu/+Cf3laaCAXaFph22jT
/m8fW2paiP5UJ0gSt1MLAGFxKi0YI/Qxck8G11LJxUwMZd3SIfOPUAY27tnNC4yL
GRynOi3BFRMUAe/Leu2qgwEyoME5nHn+OmAKb36WTYH/HL+PGzHq84e+Wfdan8ha
YcSKc1A52LSoYTi4XTUX
=h2Qo
-----END PGP SIGNATURE-----
Merge tag 'pm-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC power management and clock changes from Olof Johansson:
"This branch contains a largeish set of updates of power management and
clock setup. The bulk of it is for OMAP/AM33xx platforms, but also a
few around hotplug/suspend/resume on Exynos.
It includes a split-up of some of the OMAP clock data into separate
files which adds to the diffstat, but gross delta is fairly reasonable."
* tag 'pm-merge' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
ARM: OMAP: Move plat-omap/dma-omap.h to include/linux/omap-dma.h
ASoC: OMAP: mcbsp fixes for enabling ARM multiplatform support
watchdog: OMAP: fixup for ARM multiplatform support
ARM: EXYNOS: Add flush_cache_all in suspend finisher
ARM: EXYNOS: Remove scu_enable from cpuidle
ARM: EXYNOS: Fix soft reboot hang after suspend/resume
ARM: EXYNOS: Add support for rtc wakeup
ARM: EXYNOS: fix the hotplug for Cortex-A15
ARM: OMAP2+: omap_device: Correct resource handling for DT boot
ARM: OMAP2+: hwmod: Add possibility to count hwmod resources based on type
ARM: OMAP2+: hwmod: Add support for per hwmod/module context lost count
ARM: OMAP2+: PRM: initialize some PRM functions early
ARM: OMAP2+: voltage: fixup oscillator handling when CONFIG_PM=n
ARM: OMAP4: USB: power down MUSB PHY during boot
ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP2xxx: clock: drop obsolete clock data
ARM: OMAP2: clock: Cleanup !CONFIG_COMMON_CLK parts
ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections
ARM: AM33xx: clock: drop obsolete clock data
ARM: OMAP3xxx: clk: drop obsolete clock data
...
Here are more patches in the progression towards multiplatform, sparse
irq conversions in particular.
Tegra has a handful of cleanups and general groundwork, but is
not quite there yet on full enablement.
Platforms that are enabled through this branch are VT8500 and Zynq. note
that i.MX was converted in one of the earlier cleanup branches as
well (before we started a separate topic for multiplatform). And both
new platforms for this merge window, sunxi and bcm, were merged with
multiplatform support enabled.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJQySb/AAoJEIwa5zzehBx3Wo4P/0GrpUhB/qwuhgy43MA2I1Dv
tnyuFvsfW9uRExcw2IwT39GFls98QUM9TwQxPqOTHVf+u0LkYMZ9aDeWJOdj3RvG
H70Ypj4gZDrzZAFr2TUf8NnYGHd6G2EcMn3261Hjfd7YrswCjsMPvgRns7VOyHCa
deif3KcLu3+HzxvuzqlVlTuSAagCQbfqqnTQduMRdJPHT3X3sXwl7ABW+qfOoeYC
rjqIbjdh5dB1d/f7igtgBbXjSTnVz/Mr1+wk4rp9Xr1Wv0IXvIaSKjK2Df8ZuNAk
aQ6mMy/oDVxlDSrYv0F7lB40/rsZcPqz8+fgYJ2FnvCpIM7z7NeTWD2kQJ2UaQ/s
VunShloRxF8It6104EVWZDfEA9NvVBcCALSze0NukqiHZRZYGUzxRNQDrncaksC9
Lm+Z16cUWogsZq7VDCgXYQJeakPQfBDnsx7siMvAbOgvtpSClxuwhdC/czJiix7h
BcpA+l5xSviUhHvzHhDt9iJxHjbUmo1xLDvaZSgj2OjAj257JcwaNBCk5BjZTCwe
xZmQu1FjwaGtjLiG6QY0WJRsq1hiFRIb/MaWar/WpfqADFqARoambGFUjOl+P4Mu
DIM5Z0AS04H+pLuP1QOz/yXxOPEP6Ri36to6XrgzfL/XGet5LW2P59xXxhcWC/OL
/3IAcQrsAqh4aGMOstW1
=UJlh
-----END PGP SIGNATURE-----
Merge tag 'multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC multiplatform conversion patches from Olof Johansson:
"Here are more patches in the progression towards multiplatform, sparse
irq conversions in particular.
Tegra has a handful of cleanups and general groundwork, but is not
quite there yet on full enablement.
Platforms that are enabled through this branch are VT8500 and Zynq.
Note that i.MX was converted in one of the earlier cleanup branches as
well (before we started a separate topic for multiplatform). And both
new platforms for this merge window, sunxi and bcm, were merged with
multiplatform support enabled."
Fix up conflicts mostly as per Olof.
* tag 'multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits)
ARM: zynq: Remove all unused mach headers
ARM: zynq: add support for ARCH_MULTIPLATFORM
ARM: zynq: make use of debug_ll_io_init()
ARM: zynq: remove TTC early mapping
ARM: tegra: move debug-macro.S to include/debug
ARM: tegra: don't include iomap.h from debug-macro.S
ARM: tegra: decouple uncompress.h and debug-macro.S
ARM: tegra: simplify DEBUG_LL UART selection options
ARM: tegra: select SPARSE_IRQ
ARM: tegra: enhance timer.c to get IO address from device tree
ARM: tegra: enhance timer.c to get IRQ info from device tree
ARM: timer: fix checkpatch warnings
ARM: tegra: add TWD to device tree
ARM: tegra: define DT bindings for and instantiate RTC
ARM: tegra: define DT bindings for and instantiate timer
clocksource/mtu-nomadik: use apb_pclk
clk: ux500: Register mtu apb_pclocks
ARM: plat-nomadik: convert platforms to SPARSE_IRQ
mfd/db8500-prcmu: use the irq_domain_add_simple()
mfd/ab8500-core: use irq_domain_add_simple()
...
The simple example provided in the comments for nand_id_has_period()
actually has a period of 3, not 2. Silly mistake...
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The {read,write}s{b,w,l} operations are not defined by all
architectures and are being removed from the asm-generic/io.h
interface.
This patch replaces the usage of these string functions in the mtd
gpio accessors with io{read,write}{8,16,32}_rep calls instead.
Signed-off-by: Matthew Leach <matthew@mattleach.net>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
It could happen (1 out of 100 times) that NAND did not start up
correctly after warm rebooting, so the kernel could not find the UBI or
DMA timed out due to a stalled BCH. When resetting BCH together with
GPMI, the issue could not be observed anymore (after 10000+ reboots). We
probably need the consistent state already before sending any command to
NAND, even when no ECC is needed. I chose to keep the extra reset for
BCH when changing the flash layout to be on the safe side.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Huang Shijie <b32955@freescale.com>
Cc: stable@vger.kernel.org
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This contains the bulk of new SoC development for this merge window.
Two new platforms have been added, the sunxi platforms (Allwinner A1x
SoCs) by Maxime Ripard, and a generic Broadcom platform for a new
series of ARMv7 platforms from them, where the hope is that we can
keep the platform code generic enough to have them all share one mach
directory. The new Broadcom platform is contributed by Christian Daudt.
Highbank has grown support for Calxeda's next generation of hardware,
ECX-2000.
clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also
taken on maintainership of the platform.
Beyond this there has been a bunch of work from a number of people on
converting more platforms to IRQ domains, pinctrl conversion, cleanup
and general feature enablement across most of the active platforms.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJQyLCjAAoJEIwa5zzehBx3AdQP/R+L3+EQMjiEWt/p7g/ql5Em
0SnP92CcGzrjgLTg9z1FeOazfOsGnkZAYUlDRkqfKobH3VqkhYFFtt1/0x0KMahm
xcowHgMBOyimFdWT9vLK3J8U6DLui5XrEG9LGH2VL+lqmfjIyP/OOF3mVc0/+pV9
WTLAsYswdBRSeiNuF43kqlfrOwF6xsPLgiNMlc82w6BzHqoHu6dOif5M9MqWaApS
V74DPmwLD371Tyit6aHqt3JOqpgiPSHlmxkzomK+5idcW3Pa7HnzzFYmx85dk/eN
J2siqIkoOu7tEfjIbNZTL2MYoX4tUUKv4qZZ3IOl3YSWaV3P5ilMApF01XVrkk8E
DWOMhzte9hC7L90W+/kCPLF1VyeAhCem2KQWUitO71fKur3r+3ZaUokNVvWzkJIL
7aduxAJOV2hfLgEqbjbjF3o4S8p63OV3kzivFJM1And15zDJo4+qqOh67+bPo4jj
+R4du+SqzXriw4i3tDLGVpdjDffk4D41tbLzgkWAtvGyoP45yeYfHAzAh0pDFPRv
ASfZVmZ5PhwAUAkIMnpC2sjgmxMYff3SYqmDgnsqXES7rbDH/hG+teymtHFTyUQp
m+f60DNotSMcMvkLdvruLSB4aeTiwbfOqPn/g+aXYUlPuNMq1fVWgN7EJKWkamK4
nRwaJmLwx1/ojcVbpy2G
=YMKB
-----END PGP SIGNATURE-----
Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC updates from Olof Johansson:
"This contains the bulk of new SoC development for this merge window.
Two new platforms have been added, the sunxi platforms (Allwinner A1x
SoCs) by Maxime Ripard, and a generic Broadcom platform for a new
series of ARMv7 platforms from them, where the hope is that we can
keep the platform code generic enough to have them all share one mach
directory. The new Broadcom platform is contributed by Christian
Daudt.
Highbank has grown support for Calxeda's next generation of hardware,
ECX-2000.
clps711x has seen a lot of cleanup from Alexander Shiyan, and he's
also taken on maintainership of the platform.
Beyond this there has been a bunch of work from a number of people on
converting more platforms to IRQ domains, pinctrl conversion, cleanup
and general feature enablement across most of the active platforms."
Fix up trivial conflicts as per Olof.
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits)
mfd: vexpress-sysreg: Remove LEDs code
irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids
clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids
irq: versatile: delete dangling variable
ARM: sunxi: add missing include for mdelay()
ARM: EXYNOS: Avoid early use of of_machine_is_compatible()
ARM: dts: add node for PL330 MDMA1 controller for exynos4
ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
ARM: EXYNOS: add UART3 to DEBUG_LL ports
ARM: S3C24XX: Add clkdev entry for camif-upll clock
ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers
ARM: sunxi: Add missing sun4i.dtsi file
pinctrl: samsung: Do not initialise statics to 0
ARM i.MX6: remove gate_mask from pllv3
ARM i.MX6: Fix ethernet PLL clocks
ARM i.MX6: rename PLLs according to datasheet
ARM i.MX6: Add pwm support
ARM i.MX51: Add pwm support
ARM i.MX53: Add pwm support
ARM: mx5: Replace clk_register_clkdev with clock DT lookup
...
Cleanup patches for various ARM platforms and some of their associated
drivers. There's also a branch in here that enables Freescale i.MX to be
part of the multiplatform support -- the first "big" SoC that is moved
over (more multiplatform work comes in a separate branch later during
the merge window).
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJQx2p9AAoJEIwa5zzehBx3aPUQAIjV3VDf/ACkA4KUQu0BFg5U
57OIkl6RCZvfKhYgq5+6OJ2AK6VkGh9PqTmXkDS7Nj3QMS/uWcb3U419aPJsd3Z/
vNGpTl+J/YcAcFrKMqTyNv98TAiAOJlpm70CqmRbkhpMfoJb7//1JKqGTJPBO+tj
8ZEwNGC0WbRNOSQTY/TTAhbZE1sqXwKy9mDLGmcwqKBY8H1TFHyPB6yWYFSxMHxS
JAegbYhYO9FawOOLoi9ovT+2vUR9vDu0xxV4zUK9f5DqKcCb/wYuN0QkusjnEutm
RfIt7iXHHzi35YPxtlrGgSz9EIYXKAafSzkgf3Ydpjci5DH/vbVexm/CT+V+SwOT
SvucYJMALI/aOEFJWN/50L6B9zipSrWb51tK7WFXz/sUCrMQrXH3Mu99mjHZXSoL
1cylsvs3DFQC7vHFLSjRpX6eJdfE+Hb0LZ878eXSbDVCOnU8odAQrofugqfmeVDk
eN0+BWmchJgvljOiKVUQMC3PCquCaAAO1lm/HU7bWPlVigTuHSW0uisDyCYAtlt1
dGxnbbhoFJvSH7CMOoMO7hIFnoNJEe6+uVUuwA/+iJouMXMJLoY6Da4L72h1Mp81
o4Hr6Kxly/SMtURZ/6pCycx5ahb5TaahstYAoe7Qp1dMj5U2m6fUVfKkG7tUx1CW
MIuvN3qJeW2qKWKmZRVM
=zfPd
-----END PGP SIGNATURE-----
Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups on various subarchitectures from Olof Johansson:
"Cleanup patches for various ARM platforms and some of their associated
drivers. There's also a branch in here that enables Freescale i.MX to
be part of the multiplatform support -- the first "big" SoC that is
moved over (more multiplatform work comes in a separate branch later
during the merge window)."
Conflicts fixed as per Olof, including a silent semantic one in
arch/arm/mach-omap2/board-generic.c (omap_prcm_restart() was renamed to
omap3xxx_restart(), and a new user of the old name was added).
* tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (189 commits)
ARM: omap: fix typo on timer cleanup
ARM: EXYNOS: Remove unused regs-mem.h file
ARM: EXYNOS: Remove unused non-dt support for dwmci controller
ARM: Kirkwood: Use hw_pci.ops instead of hw_pci.scan
ARM: OMAP3: cm-t3517: use GPTIMER for system clock
ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER
ARM: SAMSUNG: use devm_ functions for ADC driver
ARM: EXYNOS: no duplicate mask/unmask in eint0_15
ARM: S3C24XX: SPI clock channel setup is fixed for S3C2443
ARM: EXYNOS: Remove i2c0 resource information and setting of device names
ARM: Kirkwood: checkpatch cleanups
ARM: Kirkwood: Fix sparse warnings.
ARM: Kirkwood: Remove unused includes
ARM: kirkwood: cleanup lsxl board includes
ARM: integrator: use BUG_ON where possible
ARM: integrator: push down SC dependencies
ARM: integrator: delete static UART1 mapping
ARM: integrator: delete SC mapping on the CP
ARM: integrator: remove static CP syscon mapping
ARM: integrator: remove static AP syscon mapping
...
This is a collection of header file cleanups, mostly for OMAP and AT91,
that keeps moving the platforms in the direction of multiplatform by
removing the need for mach-dependent header files used in drivers and
other places.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJQx2reAAoJEIwa5zzehBx3Z/oQAIHp8aXbUD0GvbBPQ2vIydZ8
Qfdh2ypbyFB9GSLmPP6BhurEFUcwmW3MH2r9Kq68omPt4XxrFEt1SdEn3TgZlhTY
YYzEv2DLbWfmKCDBFAEFullsfVkrpggyou5ty30YVp/u2lVLvChpkciE5/9HADy5
uoh/W2KZcLE51tvnbRy/1DBaOtxEdCjJ9hTaef7FCB9ugOG+yMDYwIPRW/b4fNA6
o/1NuZTWp0H4ePRG2oqLxYnjSiF63DVTJZjSJ+c5gW34bWgh8+/xzaLFA9U++/ig
meGUD1Oe65+ctr+Wk2mV29eb02jauUe6qvkwt+iFIDDopgc2mn5BcW+ENpgpjhe3
6l3ClRd94qh4cMWzqDa5PZCdetshiKqSH2IGpKS/dHNB1h5sBP7CCbvbalwzWd5n
qjfkPC7kSFyU3XV+9SEAXE6HLKsiMQy9kRcKOMdTE5BA4FEAZk0wfiG9WcVCvS2D
9tDC3X0aScyXx4Mkd4wIAZVhY68QuI17fPft9zZSj691YiUW5cR2yF1qbCka0yd5
pHu/QSZg1+dUitMUvMPQmWJ15jnAtEYUtV/8zQFFVchgkxlrW+UtvW3zxghB6D+J
ZwcjAMfQQz9fLoMQXlVovjQIhYsjw3SlV62ReBH7eyPs3+KfPIBn7Ks6mVQs3dS5
AMUWORsB5u92XHl9EL9C
=aggA
-----END PGP SIGNATURE-----
Merge tag 'headers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC Header cleanups from Olof Johansson:
"This is a collection of header file cleanups, mostly for OMAP and
AT91, that keeps moving the platforms in the direction of
multiplatform by removing the need for mach-dependent header files
used in drivers and other places."
Fix up mostly trivial conflicts as per Olof.
* tag 'headers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (106 commits)
ARM: OMAP2+: Move iommu/iovmm headers to platform_data
ARM: OMAP2+: Make some definitions local
ARM: OMAP2+: Move iommu2 to drivers/iommu/omap-iommu2.c
ARM: OMAP2+: Move plat/iovmm.h to include/linux/omap-iommu.h
ARM: OMAP2+: Move iopgtable header to drivers/iommu/
ARM: OMAP: Merge iommu2.h into iommu.h
atmel: move ATMEL_MAX_UART to platform_data/atmel.h
ARM: OMAP: Remove omap_init_consistent_dma_size()
arm: at91: move at91rm9200 rtc header in drivers/rtc
arm: at91: move reset controller header to arm/arm/mach-at91
arm: at91: move pit define to the driver
arm: at91: move at91_shdwc.h to arch/arm/mach-at91
arm: at91: move board header to arch/arm/mach-at91
arn: at91: move at91_tc.h to arch/arm/mach-at91
arm: at91 move at91_aic.h to arch/arm/mach-at91
arm: at91 move board.h to arch/arm/mach-at91
arm: at91: move platfarm_data to include/linux/platform_data/atmel.h
arm: at91: drop machine defconfig
ARM: OMAP: Remove NEED_MACH_GPIO_H
ARM: OMAP: Remove unnecessary mach and plat includes
...
This patch does two things related to reading the factory badblock table during
initialization: (1) fix error where a non-zero return code from
docg4_read_page() is assumed to be an error (it was later changed to be
max_bitflips; thanks to Brian Norris for bringing this to my attention a while
back), and (2) if there is an error reading the factory bbt, it tries reading
another (redundant) factory bbt table.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Modify the nand_ecclayout to place the two bb marker bytes in the oob region
off-limits to the user.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The controller on the docg4 has a "reliable" mode, where consecutive 2k pages
are used in parallel. The initial program loader (IPL) on my Treo 680 expects
the secondary program loader (SPL) to be written in this mode. This patch adds
support for writing data in reliable mode, by way of a module parameter.
Support for reading in this mode (as the IPL does) is not supported yet, but
alternate (even-numbered) 2k pages written in reliable mode can be read normally
(odd-numbered pages will contain junk and generate ecc errors).
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
* Introduction of device PM QoS flags.
* ACPI device power management update allowing subsystems other than
PCI to use it more easily.
* ACPI device enumeration rework allowing additional kinds of devices
to be enumerated via ACPI. From Mika Westerberg, Adrian Hunter,
Mathias Nyman, Andy Shevchenko, and Rafael J. Wysocki.
* ACPICA update to version 20121018 from Bob Moore and Lv Zheng.
* ACPI memory hotplug update from Wen Congyang and Yasuaki Ishimatsu.
* Introduction of acpi_handle_<level>() messaging macros and ACPI-based CPU
hot-remove support from Toshi Kani.
* ACPI EC updates from Feng Tang.
* cpufreq updates from Viresh Kumar, Fabio Baltieri and others.
* cpuidle changes to quickly notice governor prediction failure from
Youquan Song.
* Support for using multiple cpuidle drivers at the same time and cpuidle
cleanups from Daniel Lezcano.
* devfreq updates from Nishanth Menon and others.
* cpupower update from Thomas Renninger.
* Fixes and small cleanups all over the place.
--
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQIcBAABAgAGBQJQxxevAAoJEKhOf7ml8uNsHacQAK2xoQozDddPBAaTCf1OWW/G
J4E2qMn+gy4AtFmQ0/xeZVvvylOCn9eu/kv3QJ/bFlVoUsqTgfPwQBjT6HjF1Acn
7yVFdr9H/tn2wi9nW2Gv6Tl2Hr/kFLpo0f5Kd40Z+P8SV5sKX5ktJcVpJ/I/P4Vh
Qw2nWtj7hQktZDERzgG4ZpMbQToNhbLhbKWB9ad3/XQSSA9JkfgvBFgrTEGHcZD5
bwsggjNdOAWNGeDdzRsQSDn0Alld5ILVdSJ5xKimO1O70WvKc7fqA1IdYRIeKL90
yz4bcoYKzl9iktlw8+x5o1U9mrc8TFV5p4+zV+t5Z6pzS/J3kWvnsW4zu9sCrxFv
Wic3SKyiem7s2dxrYyj4ZXAci3GK4ouRTrCLqk7/00tEGdwAQD1ZNfsUJp6jKayz
FvtZUgItcOyrlQ6B4nh951OY6dI3AUYJ2NuWWNr5NZkgVAvQGV8zTGOImbeVeL2+
pMiw14zScO3ylYilVcjTKDDMj2sDZ68mw5PIcbmksvWsCLo26jDBVDtLVmtYWyd4
ek3WnOrQZr0R3agvOLLssMKXompvpP+N4Klf4rV+GtqGsWtHryYKys2Laju9FwFj
yYLchxYlxhGTzqq8LjF90HDL0TWpPe6cPi+B5ow9g/SXLexbMKNQGhv3Jovm2yR3
j54tKBWy7e9AAYEDPirX
=6OEP
-----END PGP SIGNATURE-----
Merge tag 'pm+acpi-for-3.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull ACPI and power management updates from Rafael Wysocki:
- Introduction of device PM QoS flags.
- ACPI device power management update allowing subsystems other than
PCI to use it more easily.
- ACPI device enumeration rework allowing additional kinds of devices
to be enumerated via ACPI. From Mika Westerberg, Adrian Hunter,
Mathias Nyman, Andy Shevchenko, and Rafael J. Wysocki.
- ACPICA update to version 20121018 from Bob Moore and Lv Zheng.
- ACPI memory hotplug update from Wen Congyang and Yasuaki Ishimatsu.
- Introduction of acpi_handle_<level>() messaging macros and ACPI-based
CPU hot-remove support from Toshi Kani.
- ACPI EC updates from Feng Tang.
- cpufreq updates from Viresh Kumar, Fabio Baltieri and others.
- cpuidle changes to quickly notice governor prediction failure from
Youquan Song.
- Support for using multiple cpuidle drivers at the same time and
cpuidle cleanups from Daniel Lezcano.
- devfreq updates from Nishanth Menon and others.
- cpupower update from Thomas Renninger.
- Fixes and small cleanups all over the place.
* tag 'pm+acpi-for-3.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (196 commits)
mmc: sdhci-acpi: enable runtime-pm for device HID INT33C6
ACPI: add Haswell LPSS devices to acpi_platform_device_ids list
ACPI: add documentation about ACPI 5 enumeration
pnpacpi: fix incorrect TEST_ALPHA() test
ACPI / PM: Fix header of acpi_dev_pm_detach() in acpi.h
ACPI / video: ignore BIOS initial backlight value for HP Folio 13-2000
ACPI : do not use Lid and Sleep button for S5 wakeup
ACPI / PNP: Do not crash due to stale pointer use during system resume
ACPI / video: Add "Asus UL30VT" to ACPI video detect blacklist
ACPI: do acpisleep dmi check when CONFIG_ACPI_SLEEP is set
spi / ACPI: add ACPI enumeration support
gpio / ACPI: add ACPI support
PM / devfreq: remove compiler error with module governors (2)
cpupower: IvyBridge (0x3a and 0x3e models) support
cpupower: Provide -c param for cpupower monitor to schedule process on all cores
cpupower tools: Fix warning and a bug with the cpu package count
cpupower tools: Fix malloc of cpu_info structure
cpupower tools: Fix issues with sysfs_topology_read_file
cpupower tools: Fix minor warnings
cpupower tools: Update .gitignore for files created in the debug directories
...
As can be seen from the diffstat the major changes
are:
- A big conversion of the AT91 pinctrl driver and
the associated ACKed platform changes under
arch/arm/max-at91 and its device trees. This
has been coordinated with the AT91 maintainers
to go in through the pinctrl tree.
- A larger chunk of changes to the SPEAr drivers
and the addition of the "plgpio" driver for the
SPEAr as well.
- The removal of the remnants of the Nomadik driver
from the arch/arm tree and fusion of that into
the Nomadik driver and platform data header files.
- Some local movement in the Marvell MVEBU drivers,
these now have their own subdirectory.
- The addition of a chunk of code to gpiolib under
drivers/gpio to register gpio-to-pin range mappings
from the GPIO side of things. This has been
requested by Grant Likely and is now implemented,
it is particularly useful for device tree work.
Then we have incremental updates all over the place,
many of these are cleanups and fixes from Axel Lin
who has done a great job of removing minor mistakes
and compilation annoyances.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJQupLkAAoJEEEQszewGV1z8ykP/3yLi5hb3QstajrL3jvrHcqN
7sc4uW1/9pCa6802nBw7qOfIGxgTAriGtAIePdtGhIkij6TLyyWfvlmUz3iJkeZ5
4nYy69yOdNMeBGvhXBkBD4K4lL3NGZ9eR+S1rgWY0J3Y+a5upibJeaXxmYBayjBH
bN/OiK77zaKv91zKSZ4YW9WCzrjn2E0w1mDRcWdffcyrNplY8qm/G2iXBT+UoCLa
UoR1zxG9nqF+nQ8mL+dVtVjlHsUcj0NEp34HQrUQ8ACOaEIiSI/zDe7afOC38Iy7
EUTV4IwKeKJyTnAN/QSzbTXF41CR/Qbihubo6sUrbAmyJXLnybVotd4Inh4ca7II
c2TPV89tSnJWwDSizHwbY3sXIVw8ojmjYMr1ib0Z9GBGyoij1va5WqCJ4iIzTzuc
imvDSz8ctuuxo6iOQs3smUaHXGz1V+3zvQ5v+Ioc1h9mN2LVKNa6NjmFNZmeFHLa
44zIes51DUXizaRobOffjoTIlUkAdwYQUpRtq0hvQtgYTyUIeXzfzCNzDoT6bhK3
VhLn4c4apETER6KtYCPu8PtxM/yyopwUj95WvnPK2fu/m+1B26jUVawomWfRtCQF
kuovLCTTemn04jWWl3r0JovE/tVcgBrpxTYi6Z4RPY7PuD4sQ477DeM2x3DWZPQQ
MHveLGA87735XKZkqQRR
=rUOP
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-for-v3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl changes from Linus Walleij:
"These are the first and major pinctrl changes for the v3.8 merge
cycle. Some of this is used as merge base for other trees so I better
be early on the trigger.
As can be seen from the diffstat the major changes are:
- A big conversion of the AT91 pinctrl driver and the associated ACKed
platform changes under arch/arm/max-at91 and its device trees. This
has been coordinated with the AT91 maintainers to go in through the
pinctrl tree.
- A larger chunk of changes to the SPEAr drivers and the addition of
the "plgpio" driver for the SPEAr as well.
- The removal of the remnants of the Nomadik driver from the arch/arm
tree and fusion of that into the Nomadik driver and platform data
header files.
- Some local movement in the Marvell MVEBU drivers, these now have
their own subdirectory.
- The addition of a chunk of code to gpiolib under drivers/gpio to
register gpio-to-pin range mappings from the GPIO side of things.
This has been requested by Grant Likely and is now implemented, it
is particularly useful for device tree work.
Then we have incremental updates all over the place, many of these are
cleanups and fixes from Axel Lin who has done a great job of removing
minor mistakes and compilation annoyances."
* tag 'pinctrl-for-v3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (114 commits)
ARM: mmp: select PINCTRL for ARCH_MMP
pinctrl: Drop selecting PINCONF for MMP2, PXA168 and PXA910
pinctrl: pinctrl-single: Fix error check condition
pinctrl: SPEAr: Update error check for unsigned variables
gpiolib: Fix use after free in gpiochip_add_pin_range
gpiolib: rename pin range arguments
pinctrl: single: support gpio request and free
pinctrl: generic: add input schmitt disable parameter
pinctrl/u300/coh901: stop spawning pinctrl from GPIO
pinctrl/u300/coh901: let the gpio_chip register the range
pinctrl: add function to retrieve range from pin
gpiolib: return any error code from range creation
pinctrl: make range registration defer properly
gpiolib: rename find_pinctrl_*
gpiolib: let gpiochip_add_pin_range() specify offset
ARM: at91: pm9g45: add mmc support
ARM: at91: Animeo IP: add mmc support
ARM: at91: dt: add mmc pinctrl for Atmel reference boards
ARM: at91: dt: at91sam9: add mmc pinctrl support
ARM: at91/dts: add nodes for atmel hsmci controllers for atmel boards
...
The cmdline is the easiest to change source of information. Thus
let it take precedence over 'RedBoot' and 'ofpart'. This makes the
mxc_nand driver to be in sync with all other NAND drivers that support
'cmdlinepart' partition parsing.
Also change 'const char *' to 'const char const *' as advised by checkpatch.pl
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
If nand_scan_ident() or nand_scan_tail() fails, the NAND chip may have
been deselected and the clock already disabled. Thus, check 'clk_act'
in the error path to decide whether the clock still needs to be
disabled.
This fixes a:
|WARNING: at drivers/clk/clk.c:472 __clk_disable+0x3c/0x78()
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
It's more user friendly to report debug information and statistics
through debugfs, than to use printing facilites.
This patch introduces a very minimal debugfs infrastructure
and moves eraseblock wear report to an entry located at:
/sys/kernel/debug/nandsim/wear_report
This means we can remove rptwear option and just let
the user get the wear report when we needs to.
Signed-off-by: Ezequiel Garcia <elezegarcia@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This patch fix pmecc's read_page() to return maximum number of bitflips, 0 if uncorrectable.
In the commit: 3f91e94f7f ("mtd: nand: read_page() returns max_bitflips ()"),
The ecc.read_page() is changed to return the maximum number of bitflips.
And when meet uncorrectable bitflips it needs to return 0.
See the comment in nand.h:
* @read_page: function to read a page according to the ECC generator
* requirements; returns maximum number of bitflips corrected in
* any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
- NAND_CMD_READID want an address that it is not scaled on x16 device (it is always 0x20)
- NAND_CMD_PARAM want 8 bits data
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The driver call nand_scan_ident in 8 bit mode, then
readid or onfi detection are done (and detect bus width).
The driver should update its bus width before calling nand_scan_tail.
This work because readid and onfi are read work 8 byte mode.
Note that nand_scan_ident send command (NAND_CMD_RESET, NAND_CMD_READID, NAND_CMD_PARAM), address and read data
The ONFI specificication is not very clear for x16 device if high byte of address should be driven to 0,
but according to [1] it should be ok to not drive it during autodetection.
[1]
3.3.2. Target Initialization
[...]
The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus.
The host shall not issue commands that use a word data width on x16 devices until the host
determines the device supports a 16-bit data bus width in the parameter page.
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This help to detect bad flash identification in case the size is not present
on the name (ONFI).
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
nand_wait_ready timeout should not assume HZ=100.
Make it independent of HZ value by using msecs_to_jiffies.
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
There are two reasons to remove the "chip" parameter in nand_get_device():
[1] The nand_release_device() does not have the "chip" parameter.
[2] We can get the nand_chip by the mtd->priv field.
This patch removes the "chip" parameter in nand_get_device().
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The nand_get_device() does not select the chip, but nand_release_device()
does de-select the chip. It is really strange.
With the current code, nand_sync() will de-select the chip, even if the chip
has never been selected.
To make the balance of select/de-select chip, it's better to remove the
de-select chip code in nand_release_device() which makes the code more
clear.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
enabled. Unfortunately the DMA header patch had to be redone
to avoid adding new multiplatform specific include paths, the
other patches are just trivial compile fixes.
Note that this does not yet contain the necessary Kconfig
changes as we are still waiting for some drivers to get
fixed up first.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQuOZOAAoJEBvUPslcq6Vz9wIQAM/L8NQFGZy8Z5wIMV6MMHRl
maChJfhyHXAP4f/MHKz+bO1CDxUNzbgDvDdrraJl/KLypHClpHMcy8QI2EpsSqBu
EZfBZpwZhChVTExnpcmCOFX7QC5ASP13XPMkz9iA8+gMM8r9gNTiNKYpHbBI24zu
PmyNbsxfXILUdGZgi532+MaEr1szHcyqb5cgQqIg/yPJ5lJ4FIDMCg4d+N4DGrWp
5WIFWt3yZ0bu/W5UTR7sSRuafjHatfoueh6Z31IBQYj556WBjJrl6rkSPZGEzFik
uAsWIJI/QAGyBpH7VYKea9+bZsSOGirF4pZM21yLcyjpgd81ojTygMl63nkaxfyg
3aPm3aljSOtkhOs8xeR9FKhyx9jML6jbxGT3WtCjDsEVeyMgl52ltkfVSJWxmdSt
asgQu+ZZLGvPF/CmQRx0aeOrqZCr+5y+yfSJbNHHHx6Rv3RMFwzTJJESgA9nx9WH
qrY7xEbsXXOSV3d8v9PvI42iFxp9mK6XvA0XewpFRZAN/GfsrAQZGYRK2mrhbWZh
aYv9Hz3W/tXM31/9cQMnel6WI9tWUFCqWIjkJrko1vMFvYZ/XQDCrXg47D4O+z40
+CK2xhcmLtuv1Zr9zahuW0YvXfDdc6eptyDDhYvKKjE2BnxxREdsT7WZoV3sc7qI
rNg1z8rLxFPp+n4buqTe
=w+UN
-----END PGP SIGNATURE-----
Merge tag 'tags/omap-for-v3.8/cleanup-multiplatform-no-clock-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/pm2
From Tony Lindgren:
Remaining patches to allow omap2+ to build with multiplatform
enabled. Unfortunately the DMA header patch had to be redone
to avoid adding new multiplatform specific include paths, the
other patches are just trivial compile fixes.
Note that this does not yet contain the necessary Kconfig
changes as we are still waiting for some drivers to get
fixed up first.
* tag 'tags/omap-for-v3.8/cleanup-multiplatform-no-clock-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP: Move plat-omap/dma-omap.h to include/linux/omap-dma.h
ASoC: OMAP: mcbsp fixes for enabling ARM multiplatform support
watchdog: OMAP: fixup for ARM multiplatform support
Conflicts due to surrounding changes in:
arch/arm/mach-omap2/omap_hwmod_2420_data.c
arch/arm/mach-omap2/omap_hwmod_2430_data.c
Signed-off-by: Olof Johansson <olof@lixom.net>
Based on earlier discussions[1] we attempted to find a suitable
location for the omap DMA header in commit 2b6c4e73 (ARM: OMAP:
DMA: Move plat/dma.h to plat-omap/dma-omap.h) until the conversion
to dmaengine is complete.
Unfortunately that was before I was able to try to test compile
of the ARM multiplatform builds for omap2+, and the end result
was not very good.
So I'm creating yet another all over the place patch to cut the
last dependency for building omap2+ for ARM multiplatform. After
this, we have finally removed the driver dependencies to the
arch/arm code, except for few drivers that are being worked on.
The other option was to make the <plat-omap/dma-omap.h> path
to work, but we'd have to add some new header directory to for
multiplatform builds.
Or we would have to manually include arch/arm/plat-omap/include
again from arch/arm/Makefile for omap2+.
Neither of these alternatives sound appealing as they will
likely lead addition of various other headers exposed to the
drivers, which we want to avoid for the multiplatform kernels.
Since we already have a minimal include/linux/omap-dma.h,
let's just use that instead and add a note to it to not
use the custom omap DMA functions any longer where possible.
Note that converting omap DMA to dmaengine depends on
dmaengine supporting automatically incrementing the FIFO
address at the device end, and converting all the remaining
legacy drivers. So it's going to be few more merge windows.
[1] https://patchwork.kernel.org/patch/1519591/#
cc: Russell King <linux@arm.linux.org.uk>
cc: Kevin Hilman <khilman@ti.com>
cc: "Benoît Cousson" <b-cousson@ti.com>
cc: Herbert Xu <herbert@gondor.apana.org.au>
cc: "David S. Miller" <davem@davemloft.net>
cc: Vinod Koul <vinod.koul@intel.com>
cc: Dan Williams <djbw@fb.com>
cc: Mauro Carvalho Chehab <mchehab@infradead.org>
cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
cc: David Woodhouse <dwmw2@infradead.org>
cc: Kyungmin Park <kyungmin.park@samsung.com>
cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
cc: Hans Verkuil <hans.verkuil@cisco.com>
cc: Vaibhav Hiremath <hvaibhav@ti.com>
cc: Lokesh Vutla <lokeshvutla@ti.com>
cc: Rusty Russell <rusty@rustcorp.com.au>
cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
cc: Afzal Mohammed <afzal@ti.com>
cc: linux-crypto@vger.kernel.org
cc: linux-media@vger.kernel.org
cc: linux-mtd@lists.infradead.org
cc: linux-usb@vger.kernel.org
cc: linux-fbdev@vger.kernel.org
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
* pm-qos:
PM / QoS: Handle device PM QoS flags while removing constraints
PM / QoS: Resume device before exposing/hiding PM QoS flags
PM / QoS: Document request manipulation requirement for flags
PM / QoS: Fix a free error in the dev_pm_qos_constraints_destroy()
PM / QoS: Fix the return value of dev_pm_qos_update_request()
PM / ACPI: Take device PM QoS flags into account
PM / Domains: Check device PM QoS flags in pm_genpd_poweroff()
PM / QoS: Make it possible to expose PM QoS device flags to user space
PM / QoS: Introduce PM QoS device flags support
PM / QoS: Prepare struct dev_pm_qos_request for more request types
PM / QoS: Introduce request and constraint data types for PM QoS flags
PM / QoS: Prepare device structure for adding more constraint types
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.18 (GNU/Linux)
iQEcBAABAgAGBQJQss0FAAoJEHm+PkMAQRiG6cEH/An3PYsWBBy27tzoLyVfJKF1
3m3vR8HS2tnHg6erxms+738jos59vrWXV0Ygnvw0DHbGR0HNb4rkwce/KXu/jgOD
MRYNYhlhMFJTEUFrSrcwKITrAV3kVPWXxPXgAR6Gzpr6NPKKM9TBzEv0ze56TFYz
asOxqeBcPSS7aFZlkoNsy1wG4l0Quo5ke8VZIxo9Me5qlqubAoZ6pING4wAGXqeE
tf81CevSdpe0nqr8/dlYyCvLjrurgpJQczxRCBI3mP6kLWGfUCVzZmcu86PfT9b+
35zNJwDneIoN+D9bVDHy6mrq9uQdmhWnQuhv1joTPn6RDn1nyBRBd+A5qLxSov4=
=CPoy
-----END PGP SIGNATURE-----
Merge tag 'v3.7-rc7' into next/cleanup
Merging in mainline back to next/cleanup since it has collected a few
conflicts between fixes going upstream and some of the cleanup patches.
Git doesn't auto-resolve some of them, and they're mostly noise so let's
take care of it locally.
Conflicts are in:
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
arch/arm/plat-omap/i2c.c
drivers/video/omap2/dss/dss.c
Signed-off-by: Olof Johansson <olof@lixom.net>
While checking the "__devinit" removal patches with checkpatch.pl, I
noticed several warnings related to a space between the function name
and '(', as well as long lines. I fixed the warnings up in this patch.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
CONFIG_HOTPLUG is going away as an option so __devexit is no
longer needed.
Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
CONFIG_HOTPLUG is going away as an option so __devinitdata is no
longer needed.
Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
CONFIG_HOTPLUG is going away as an option so __devinit is no longer
needed.
Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
CONFIG_HOTPLUG is going away as an option so __devexit_p is no longer
needed.
Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
BCMA bus can contain NAND flash memory, it's registered in system as
platform device. This adds required hooks and place for controler
specific drivers.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
From Alexander Shiyan:
The main direction of this patchset - approaching the platform to the
possibility of using configurations with multiple platforms in a single
kernel. Added support of the majority of the necessary kernel symbol.
Also part of the driver code used only for the platform was moved to the
board code and converted to the use of standard drivers.
* clps711x/soc2:
MAINTAINERS: Add ARM CLPS711X entry
ARM: clps711x: Update defconfig due latest changes and new kernel symbols
ARM: clps711x: Rename board files to match functionality
ARM: clps711x: edb7211: Add support for NOR-Flash
ARM: clps711x: Moving backlight controls of framebuffer driver to the board
ARM: clps711x: p720t: Special driver for handling NAND memory is removed
ARM: clps711x: Moving power management of framebuffer driver to the board
ARM: clps711x: autcpu12: Special driver for handling NAND memory is removed
ARM: clps711x: Unused empty "ACK" calls for IRQ-chips removed
ARM: clps711x: Add FIQ interrupt handling
ARM: clps711x: Implement usage "MULTI_IRQ_HANDLER" kernel option for a platform
ARM: clps711x: Implement usage "SPARSE_IRQ" kernel option for a platform
ARM: clps711x: cdb89712: Special driver for handling memory is removed
ARM: clps711x: Always select AUTO_ZRELADDR for a platform
ARM: clps711x: p720t: Unneeded inclusion of head-sa1100.S removed
ARM: clps711x: Transform clps711x-framebuffer to platform driver and use it
ARM: clps711x: p720t: Using "leds-gpio" driver for LED control
ARM: clps711x: Using platform_driver for ethernet device
This patch provide migration to using "gpio-nand" driver instead of using
special driver for handling NAND memory.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch provide migration to using "gpio-nand" and "basic-mmio-gpio"
drivers instead of using special driver for handling NAND memory.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
"Whether" is misspelled in various comments across the tree; this
fixes them. No code changes.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
When we scan several nand chips with nand_scan(), such as
.......................
nand_scan(*, 2);
.......................
In nand_scan_ident(), the maxchips will become 2, so the current code
will select chip 1 to read the device ID. But the chip 0 is still
selected in this case.
To make the logic clear, we'd better de-select the chip when it is not used.
This patch de-select the nand chip if it is not used any more.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
'set' is tested for NULL. But subsequently accessed without the check.
Thus making it conditional to avoid NULL pointer dereferencing.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
IFC_FIR_OP_CMD0 issues command for execution without checking flash
readiness. It may cause problem if flash is not ready. Instead use
IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or
time-out, before issuing command.
NAND_CMD_READID command implemention does not fulfill above requirement. So
update its programming.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Hemant Nautiyal <hemant.nautiyal@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Enabling the diskonchip drivers on most architectures results
in a pointless warning "#warning Unknown architecture for
DiskOnChip. No default probe locations defined". The driver
can in fact handle the default location already through the
CONFIG_MTD_DOCPROBE_ADDRESS, which gets set on the platforms
that need it, and we get a run-time error if this is not
set correctly.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This patch allow to detect buggy driver/hardware with
bad RnB (dev_ready) management or when timeout occurs in polling mode.
This works when dev_ready is set or not set.
There are 2 methods to wait for an erase/program command completion:
1. Wait until nand RnB pin goes high (that's what chip->dev_ready usually does)
2. Poll the device: send a status (0x70) command and read status byte in a loop
until bit NAND_STATUS_READY is set
In all cases, you should send a status command after completion, to check if
the operation was successful. And if the operation completed, the status should
have bit NAND_STATUS_READY set.
Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Enhance the driver to support partition subnodes inside the nand
device bindings to describe partions on the nand device.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The flctl can now be probed via device tree setup in addition to the
existing platform data way.
SoC specific setup data is set in the .data member of the OF match, so
kept within the driver itself, while board/user specific setup - like
partitioning - is taken from the device tree.
Actual configuration is added for the SoC sh7372.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The code probes if DMA channels can get allocated and tears them down at
removal/failure if needed.
If available it uses them to transfer the data part (not ECC). On
failure we fall back to PIO mode.
Based on Guennadi Liakhovetski's code from the sh_mmcif driver.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Reviewed-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Some small fixes to avoid sparse and smatch complain. Other cosmetic fixes
as well.
- Change of the type of the member index in struct sh_flctl from signed
to unsigned. We use index by addressing array members, so unsigned is more
concise here. Adapt functions relying on sh_flctl::index.
- Remove a blurring cast in write_fiforeg().
- Apply consistent naming scheme when refering to the data buffer.
- Shorten some unnecessarily verbose functions.
- Remove spaces at start of lines.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The whole gpmi-nand driver has turned to pure devicetree supported.
So the linux/mtd/gpmi-nand.h is not neccessary now. Just remove it,
and move some macros to the gpmi-nand driver itself.
Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
In some configurations of "gpio-nand" RDY-pin may be not connected.
This patch allow to use driver for these configurations. In this case
we are assume that device always ready.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Use the NAND_STATUS_FAIL to replace the hardcode "0x01",
which make the code more readable.
Signed-off-by: Huang Shijie <shijie8@gmail.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Use relaxed variants of readl/writel accessors. readl/writel io accessors use
explicit dsb instruction which causes stalls in the processor core resulting
several cycles of delay for each access
Use relaxed variants where ever possible. This also results in an improved
read/write performance.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Interruptible wait caused trouble in fsmc hardware state machine if the
application was killed abruptly. To make fsmc operation safe turn wait in to
un-interruptible.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Do not use the platform_data to pass resource and be smart in the drivers.
Just pass it via resource
Switch to devm_request_and_ioremap at the sametime
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-By: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The nomadik_nand driver is really just a subset of the FSMC
NAND driver, and there are no users anymore so let's delete
it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Add a device tree version of the Denali NAND driver. Based
on an original patch from Jamie Iles to add a MMIO version
of this driver.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
The Denali controller can also be found in SoC devices attached to a
simple bus. Move the PCI specific parts into denali_pci so that we can
add a denali_dt that uses the same driver but for a device tree driver
instead of a PCI based device.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Since the introduction of nand_create_default_bbt_descr() (now known as
nand_create_badblock_pattern()) in
commit 58373ff0af
nand_chip.badblock_pattern will be dynamically calculated to the same
1-byte-length pattern that is required by fsl_elbc_nand. This custom
badblock_pattern is no longer needed, then, and its removal may help
facilitate further nand_bbt.c/nand_base.c cleanup in the future (one
down, many to go?)
Anyway, with nand_bbt.c fixed, this effectively reverts:
commit 452db27243
[MTD] [NAND] fsl_elbc_nand: fix OOB workability for large page NAND chips
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This patch fixes errors seen in identifying old Samsung SLC, due to the
following commits:
commit e2d3a35ee4
mtd: nand: detect Samsung K9GBG08U0A, K9GAG08U0F ID
commit e3b88bd604
mtd: nand: add generic READ ID length calculation functions
Some Samsung NAND with "5-byte" ID really appear to have 6-byte IDs, with
wraparound like:
Samsung K9K8G08U0D
ec d3 51 95 58 ec ec d3
Samsung K9F1G08U0C
ec f1 00 95 40 ec ec f1
Samsung K9F2G08U0B
ec da 10 95 44 00 ec da
This bad wraparound makes it hard to reliably detect the difference
between Samsung SLC with 5-byte ID and Samsung SLC with 6-byte ID.
The fix is to, for now, only use the new Samsung table for MLC. We
cannot support the new SLC (K9FAG08U0M) until Samsung gives better ID
decode information.
Note that this applies in addition to the previous regression fix:
commit bc86cf7af2
mtd: nand: fix Samsung SLC NAND identification regression
Together, these patches completely restore the previous detection
behavior so that we cannot see any more regressions in Samsung SLC NAND
(finger crossed). With luck, I can get a hold of a Samsung
representative and stop having to cross my fingers eventually.
Reported-by: Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
Tested-by: Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
A combination of the following two commits caused a regression in 3.7-rc1
when identifying some Samsung NAND, so that some previously working NAND
were no longer detected properly:
commit e3b88bd604
mtd: nand: add generic READ ID length calculation functions
commit e2d3a35ee4
mtd: nand: detect Samsung K9GBG08U0A, K9GAG08U0F ID
Particularly, a regression was seen on Samsung K9F2G08U0B, with the
following full 8-byte READ ID string:
ec da 10 95 44 00 ec da
The basic problem is that Samsung manufactures both SLC and MLC NAND
that use a non-standard decoding table for deriving information from
their IDs. I have heuristically determined that all the chips that use
the new table have ID strings which wrap around after the 6th byte.
Unfortunately, I overlooked the fact that some older Samsung SLC (which
use a different decoding table) have "5 byte ID strings" which also wrap
around after the 6th byte.
This patch re-introduces a distinction between these old and new Samsung
NAND by checking that the 6th byte is non-zero, allowing both old and
new Samsung NAND to be detected properly.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Brian Norris <computersforpeace@gmail.com>
Reported-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This moves the MTU timer driver from arch/arm/plat-nomadik
to drivers/clocksource and moves the header file to the
platform_data directory.
As this moves the last file being compiled to an object out
of arch/arm/plat-nomadik, we have to "turn off the light"
and delete the plat-nomadik directory, because it is not
allowed to have an empty Makefile in a plat-* directory.
This is probably also a desired side effect of depopulating
the arch/arm directory of drivers. Luckily we have just
deleted all the <plat/*> include files prior to this so
by moving the last one we may delete the directory.
After this all the Ux500 and Nomadik device drivers live
outside of the arch/arm hierarchy.
Cc: Alessandro Rubini <rubini@unipv.it>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Modify the device PM QoS core code to support PM QoS flags requests.
First, add a new field of type struct pm_qos_flags called "flags"
to struct dev_pm_qos for representing the list of PM QoS flags
requests for the given device. Accordingly, add a new "type" field
to struct dev_pm_qos_request (along with an enum for representing
request types) and a new member called "flr" to its data union for
representig flags requests.
Second, modify dev_pm_qos_add_request(), dev_pm_qos_update_request(),
the internal routine apply_constraint() used by them and their
existing callers to cover flags requests as well as latency
requests. In particular, dev_pm_qos_add_request() gets a new
argument called "type" for specifying the type of a request to be
added.
Finally, introduce two routines, __dev_pm_qos_flags() and
dev_pm_qos_flags(), allowing their callers to check which PM QoS
flags have been requested for the given device (the caller is
supposed to pass the mask of flags to check as the routine's
second argument and examine its return value for the result).
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Reviewed-by: mark gross <markgross@thegnar.org>
Move plat/dma.h to plat-omap/dma-omap.h as part of single
zImage work
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Similar to omap1, some of the omap2+ dma channel definitions are
used by some drivers. For moving omap2+ dma channel definitions
to mach-omap2/, the used ones should be defined locally to driver.
Drivers can eliminate it using DT, platform data, or IORESOURCE_DMA
And moving omap2+ DMA channel definitions to mach-omap2
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
gpmc-nand bch registers are now available in driver,
make use of it to handle bch[48] instead of relying
on gpmc exported functions.
And so nand driver no longer needs gpmc header, remove it.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Bring onto driver the macros defined in gpmc.h that are
not necessary outside driver, helps in removing inclusion
of gpmc.h too. Also remove GPMC prefix on those macros to
make clear it's independence with gpmc header.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Now that gpmc-nand registers are available in driver, use it
to read nand data.
"65b97cf mtd: nand: omap2: handle nand on gpmc" modified all
other instances. After initial versions of that patch, a new
change added reading nand data using gpmc exposed function.
In the final version this change was not taken care.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
memory as is now obtained via resource, upon freeing use
resource size. This also helps get rid of one macro.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
It changes the driver to use platform_device_id rather than cpu_is_xxx
to determine the controller type, and updates the platform code
accordingly.
As the result, mach/hardware.h inclusion gets removed from the driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Cc: linux-mtd@lists.infradead.org
Pull powerpc updates from Benjamin Herrenschmidt:
"Some highlights in addition to the usual batch of fixes:
- 64TB address space support for 64-bit processes by Aneesh Kumar
- Gavin Shan did a major cleanup & re-organization of our EEH support
code (IBM fancy PCI error handling & recovery infrastructure) which
paves the way for supporting different platform backends, along
with some rework of the PCIe code for the PowerNV platform in order
to remove home made resource allocations and instead use the
generic code (which is possible after some small improvements to it
done by Gavin).
- Uprobes support by Ananth N Mavinakayanahalli
- A pile of embedded updates from Freescale folks, including new SoC
and board supports, more KVM stuff including preparing for 64-bit
BookE KVM support, ePAPR 1.1 updates, etc..."
Fixup trivial conflicts in drivers/scsi/ipr.c
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (146 commits)
powerpc/iommu: Fix multiple issues with IOMMU pools code
powerpc: Fix VMX fix for memcpy case
driver/mtd:IFC NAND:Initialise internal SRAM before any write
powerpc/fsl-pci: use 'Header Type' to identify PCIE mode
powerpc/eeh: Don't release eeh_mutex in eeh_phb_pe_get
powerpc: Remove tlb batching hack for nighthawk
powerpc: Set paca->data_offset = 0 for boot cpu
powerpc/perf: Sample only if SIAR-Valid bit is set in P7+
powerpc/fsl-pci: fix warning when CONFIG_SWIOTLB is disabled
powerpc/mpc85xx: Update interrupt handling for IFC controller
powerpc/85xx: Enable USB support in p1023rds_defconfig
powerpc/smp: Do not disable IPI interrupts during suspend
powerpc/eeh: Fix crash on converting OF node to edev
powerpc/eeh: Lock module while handling EEH event
powerpc/kprobe: Don't emulate store when kprobe stwu r1
powerpc/kprobe: Complete kprobe and migrate exception frame
powerpc/kprobe: Introduce a new thread flag
powerpc: Remove unused __get_user64() and __put_user64()
powerpc/eeh: Global mutex to protect PE tree
powerpc/eeh: Remove EEH PE for normal PCI hotplug
...
This is a pretty significant branch. It's the introduction of the
first multiplatform support on ARM, and with this (and the later
branch) merged, it is now possible to build one kernel that contains
support for highbank, vexpress, mvebu, socfpga, and picoxcell. More
platforms will be convered over in the next few releases.
Two critical last things had to be done for this to be practical and
possible:
* Today each platform has its own include directory under
mach-<mach>/include/mach/*, and traditionally that is where a lot of
driver/platform shared definitions have gone, such as platform data
structures. They now need to move out to a common location instead,
and this branch moves a large number of those out to
include/linux/platform_data.
* Each platform used to list the device trees to compile for its
boards in mach-<mach>/Makefile.boot.
Both of the above changes will mean that there are some merge
conflicts to come (and some to resolve here). It's a one-time move and
once it settles in, we should be good for quite a while. Sorry for the
overhead.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJQaO7aAAoJEIwa5zzehBx3bUIP/02U8PhkHJJrrowyIsWRBOql
7LPJ53PRRgrpBdmEGzFD3TO3zaNyrjQRbYgNDvzHMO6NAMNvdRFouuWYjO11/tuB
i32zssXCC+eUOEgbAo/U/lYq+UOvqw9gv6mU+3+i3OcGEhdKOaoT/DSLPQC4hoDm
222TeLfFB3HJXu5n720dEQ9V3fO6TS1+bbh8TU3cjHqzceXsOrffZqOA5CQxUcRr
KWwOjA0nALDwWcqgv45GJNwY3GTyAQ/hPMQavnuWK0voJ+qUYk5HftKocAK7C+py
0T0OFOAHTwtyhvzJBxLC84M6Ox465BYXyeNjIB+2nG/Um9+mDoP0dnWpGy4c7DMU
P5hyqbeLGeqjUXQuYtRmgMMc3UeHKoUGAfXW9eMsjLa6/M4NLGv//7E7LbZPpgMZ
obkjwuesmcaYn/FRyj/yFmC35YlF4oCLziVzEtURZw3eKHHSUlhkTDSMNnkcZ0kZ
Vv7kFxnD2Y46ixiwSJv30ErQnVkgI3MdqDlDxkE8r5+phYuK4gCrNaJtiwRh/oNw
cFhpPxKuA0sJ9b6YRTzjC45eT/XZomEEr/uifCFeRNaCquyjYP00Mm8F0flSqwx9
zi+emzPAwNmk1bvxMUM/idGnaj0V4p+BAYUAvkbSoqU1p1flzyhU88fGTSIyKOt6
K5TCDS2v5hrVykK9TDwl
=Tc6y
-----END PGP SIGNATURE-----
Merge tag 'multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM soc multiplatform enablement from Olof Johansson:
"This is a pretty significant branch. It's the introduction of the
first multiplatform support on ARM, and with this (and the later
branch) merged, it is now possible to build one kernel that contains
support for highbank, vexpress, mvebu, socfpga, and picoxcell. More
platforms will be convered over in the next few releases.
Two critical last things had to be done for this to be practical and
possible:
* Today each platform has its own include directory under
mach-<mach>/include/mach/*, and traditionally that is where a lot
of driver/platform shared definitions have gone, such as platform
data structures. They now need to move out to a common location
instead, and this branch moves a large number of those out to
include/linux/platform_data.
* Each platform used to list the device trees to compile for its
boards in mach-<mach>/Makefile.boot.
Both of the above changes will mean that there are some merge
conflicts to come (and some to resolve here). It's a one-time move
and once it settles in, we should be good for quite a while. Sorry
for the overhead."
Fix conflicts as per Olof.
* tag 'multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (51 commits)
ARM: add v7 multi-platform defconfig
ARM: msm: Move core.h contents into common.h
ARM: highbank: call highbank_pm_init from .init_machine
ARM: dtb: move all dtb targets to common Makefile
ARM: spear: move platform_data definitions
ARM: samsung: move platform_data definitions
ARM: orion: move platform_data definitions
ARM: vexpress: convert to multi-platform
ARM: initial multiplatform support
ARM: mvebu: move armada-370-xp.h in mach dir
ARM: vexpress: remove dependency on mach/* headers
ARM: picoxcell: remove dependency on mach/* headers
ARM: move all dtb targets out of Makefile.boot
ARM: picoxcell: move debug macros to include/debug
ARM: socfpga: move debug macros to include/debug
ARM: mvebu: move debug macros to include/debug
ARM: vexpress: move debug macros to include/debug
ARM: highbank: move debug macros to include/debug
ARM: move debug macros to common location
ARM: make mach/gpio.h headers optional
...
- A long-coming conversion of various platforms to a common LED
infrastructure
- AT91 is moved over to use the newer MCI driver for MMC
- Pincontrol conversions for samsung platforms
- DT bindings for gscaler on samsung
- i2c driver fixes for tegra, acked by i2c maintainer
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJQaO48AAoJEIwa5zzehBx3excP/ieEkRhvfnWxdYST6ekvGIQr
nEyskOh2rVjgYKmSXUJyKSbvG+7bZ8VIxvPvojeAJ/R84pTFMzbR2F0CaPKzAuSW
inDt6c0Bnx1NZlfUTAoXcz7feyq9zHYNs9BCLoPU0bYNchCCqcWSKzqnpXk2ph/P
LFnmNa0j6a4E3QJYAjM2zFvc3Tgk+MWTq1fWwNFvsWTh2WbQtmB/iGnzT5Xs4XQh
u1SSx5tz0lcF5zQRGmJhXgL5+nnIP4sRwRUBAkpe3Gv5cM6WBVEBRDANa5QpbUL2
RXK5YyCTIln2Me4bPk32zEBLjiZ/WXbmiA2uwoqVgy6XToubemDXd0PtKmjj5tZ1
BkTD1DND7BKBEQnJj/GBECEdvx2FbrKfruoPcJHvXPZ7Svn5Dt/MWYJQIkRFkuhL
zlVNoDGWlU8nScGrgmTM56UvWmGWC3UFsWSgdVQNfW9yEva+G1FvRUwUH02Ip5Ad
4r28JFIn6zyjtM99ZHipU6C6Rze2ordC7fl5X5LBLkVOobioblxCAhIhcqkhfKsk
rFriNsdfYs7SrJA7mK7GzvaMEJgp/5o1noJKXI7ZBcLI8yYagzbQbPu/vGi6G6d3
0xC7NaTEJbtoXoDAtmtilLRxmw0YCXgVBBGua0K2YKpcRwnzCHNbV4gsLMnDuOXS
HP4M96LxLHJlLGCxhEme
=ck7M
-----END PGP SIGNATURE-----
Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM soc driver specific changes from Olof Johansson:
- A long-coming conversion of various platforms to a common LED
infrastructure
- AT91 is moved over to use the newer MCI driver for MMC
- Pincontrol conversions for samsung platforms
- DT bindings for gscaler on samsung
- i2c driver fixes for tegra, acked by i2c maintainer
Fix up conflicts as per Olof.
* tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
drivers: bus: omap_l3: use resources instead of hardcoded irqs
pinctrl: exynos: Fix wakeup IRQ domain registration check
pinctrl: samsung: Uninline samsung_pinctrl_get_soc_data
pinctrl: exynos: Correct the detection of wakeup-eint node
pinctrl: exynos: Mark exynos_irq_demux_eint as inline
pinctrl: exynos: Handle only unmasked wakeup interrupts
pinctrl: exynos: Fix typos in gpio/wkup _irq_mask
pinctrl: exynos: Set pin function to EINT in irq_set_type of GPIO EINTa
drivers: bus: Move the OMAP interconnect driver to drivers/bus/
i2c: tegra: dynamically control fast clk
i2c: tegra: I2_M_NOSTART functionality not supported in Tegra20
ARM: tegra: clock: remove unused clock entry for i2c
ARM: tegra: clock: add connection name in i2c clock entry
i2c: tegra: pass proper name for getting clock
ARM: tegra: clock: add i2c fast clock entry in clock table
ARM: EXYNOS: Adds G-Scaler device from Device Tree
ARM: EXYNOS: Add clock support for G-Scaler
ARM: EXYNOS: Enable pinctrl driver support for EXYNOS4 device tree enabled platform
ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoC
ARM: EXYNOS: skip wakeup interrupt setup if pinctrl driver is used
...
Device tree conversion and enablement branch. Mostly a bunch of new
bindings and setup for various platforms, but the Via/Winchip VT8500
platform is also converted over from being 100% legacy to now use
device tree for probing. More of that will come for 3.8.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJQaiKNAAoJEIwa5zzehBx329AP/1TwJk1dTHaAA7vDxyz2mq1E
F0MBL9p32R1SczrFGjbmb9ouVW5tTjbK1zted5zBrGBXDIX9Kdz3Dmm7x6b2/JvZ
8yMrdiBNpF3r8au6IaMuMlOq5yAaN+F4SxbC2rE0a9y3YmMZ6ug5dgoZ4O8orAC4
il3eq1sb+rTTPCf7C5cGlKzdRQi2KYdAycpa7ChQCYSamxJjdM7cXR7pohVv9vhd
9sF+h1I0ArxcVYn/mUOoCin8MyIWXlBQvbUnF+3aYO8CO9erhKH/owPngVBWGKZH
+X6dk0ChUJfjzaWr2HPZIYUqLUnIoO8TsRhQVmLp1rPrSzSXMG3iDq0M4WEwL4Xo
bMbAZ1KWYg53HRqbIOEQk5q9Mg7HUgtbJuOE7WLgBO5ubdKFFWLmDUJ+WVcoWzSW
qyWaWpECSptlQjFyqZJd9MjizIDhuYjog2EWaSWXETQ+1XRmCSsqx8AX6n1MVdhP
6jDLnYHYiJoOtGiaDpYxsXgMXdOVsrTegecNduqH/XhdEL1iwy3fwgK1DjoclYoj
iFbn0/Tw3N5SvJlG4xitl12DQ7MeCCbfzJGRKenVh9/O4U+qrTbFRmsNaaZw5dA1
bt+iEZ3aU8YBaKj02LexunAevpZJ2rfGNX2tBjQrIzzZK6CZibPWg42qfKJfdn7w
etXVVApw5jQjAImY64kh
=q7ZY
-----END PGP SIGNATURE-----
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM soc device tree updates from Olof Johansson:
"Device tree conversion and enablement branch. Mostly a bunch of new
bindings and setup for various platforms, but the Via/Winchip VT8500
platform is also converted over from being 100% legacy to now use
device tree for probing. More of that will come for 3.8."
Trivial conflicts due to removal of vt8500 files, and one documentation
file that was added with slightly different contents both here and in
the USb tree.
* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (212 commits)
arm: vt8500: Fixup for missing gpio.h
ARM: LPC32xx: LED fix in PHY3250 DTS file
ARM: dt: mmp-dma: add binding file
arm: vt8500: Update arch-vt8500 to devicetree support.
arm: vt8500: gpio: Devicetree support for arch-vt8500
arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices
arm: vt8500: clk: Add Common Clock Framework support
video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb
serial: vt8500: Add devicetree support for vt8500-serial
rtc: vt8500: Add devicetree support for vt8500-rtc
arm: vt8500: Add device tree files for VIA/Wondermedia SoC's
ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support
ARM: tegra: Add Avionic Design Medcom-Wide support
ARM: tegra: Add Avionic Design Plutux support
ARM: tegra: Add Avionic Design Tamonten support
ARM: tegra: dts: Add pwm label
ARM: ux500: Fix SSP register address format
ARM: ux500: Apply tc3589x's GPIO/IRQ properties to HREF's DT
ARM: ux500: Remove redundant #gpio-cell properties from Snowball DT
ARM: ux500: Add all encompassing sound node to the HREF Device Tree
...
Datasheets for the following Samsung NAND parts (both MLC and SLC) describe
extensions to the Samsung 6-byte extended ID decoding table:
K9GBG08U0A (MLC, 6-byte ID)
K9GAG08U0F (MLC, 6-byte ID)
K9FAG08U0M (SLC, 6-byte ID)
The table found in K9GAG08U0F, p.44, contains a superset of the information
found in other previous datasheets.
This patch adds support for all of these chips, with 512B and 640B OOB sizes.
It also changes the detection pattern such that this table applies to all
Samsung 6-byte ID NAND, not just MLC. This is safe, according to the NAND
parameter data I have collected:
Note that nand_base.c does not yet support the bad block marker scheme defined
for these chips (i.e., scan 1st and last page for BB markers).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Hynix has introduced a new ID decoding scheme for their newer MLC, some of
which don't support ONFI. The following devices all follow the pattern given in
the datasheet for Hynix H27UBG8T2B, p.22:
Hynix H27UAG8T2A
Hynix H27UBG8T2A
Hynix H27UBG8T2B
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When decoding the extended ID bytes of a NAND chip, we have to calculate the ID
length according to some heuristic patterns (e.g., Does the ID wrap around?
Does it end in trailing zeros?). Currently, these heuristics are built into
complicated if/else blocks that can be hard to understand.
Now, these checks can be done generically in a function, making them more
robust and reusable. In fact, this sort of calculation is needed in future
additions to nand_base.c. And with this advancement, we get the added benefit
of a more readable "extended ID decode".
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When detecting NAND parameters, the code gets a little ugly so that the
logic is obscured. Try to remedy that by moving code to separate functions
that have well-defined purposes.
This patch splits out the simple ID decode functionality, where all the
information regarding NAND size/blocksize/pagesize/oobsize/busw is encoded in
the first two bytes of the ID string.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When detecting NAND parameters, the code gets a little ugly so that the
logic is obscured. Try to remedy that by moving code to separate functions
that have well-defined purposes.
This patch splits out the extended ID decode functionality, which handles
decoding the 3rd-8th ID bytes to determine NAND device parameters.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When detecting NAND parameters, the code gets a little ugly so that the
logic is obscured. Try to remedy that by moving code to separate functions
that have well-defined purposes.
This patch splits the bad block marker options detection into its own function,
away from the other parameters (e.g., chip size, page size, etc.).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Instead of reading 2 bytes then later 8 bytes, we can simply read all 8
bytes from the start.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
We don't actually use the 'ret' variable; we set it, test it, and then it dies.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
While building an allyesconfig for UML I received this error message(s):
drivers/mtd/nand/docg4.c: In function 'probe_docg4':
drivers/mtd/nand/docg4.c:1272:2: error: implicit declaration of function
'ioremap' [-Werror=implicit-function-declaration]
drivers/mtd/nand/docg4.c:1272:10: warning: assignment makes pointer from
integer without a cast [enabled by default]
drivers/mtd/nand/docg4.c:1327:2: error: implicit declaration of function
'iounmap' [-Werror=implicit-function-declaration]
which is caused by the missing implementations on UML.
This patch adds this missing HAS_IOMEM dependency and prevents the driver from
being build on platforms with no HAS_IOMEM
Signed-off-by: Peter Huewe <peterhuewe@gmx.de>
Acked-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The current code initializes the timing registers at very time
we call the gpmi_begin(). This really wastes the cpu cycles.
Add a new flag to let the gpmi driver initializes the timing registers
only one time.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When the frequency on the nand chip pins is above 33MHz,
the nand EDO(extended Data Out) timing could be applied.
The GPMI implements a Feedback read strobe to sample the read data in
the EDO timing mode.
This patch adds the EDO feature for the gpmi-nand driver.
For some onfi nand chips, the mode 4 is the fastest;
while for other onfi nand chips, the mode 5 is the fastest.
This patch only adds the support for the fastest asynchronous timing mode.
So this patch only supports the mode 4 and mode 5.
I tested several Micron's ONFI nand chips with EDO enabled,
take Micron MT29F32G08MAA for example (in mode 5, 100MHz):
1) The test result BEFORE we add the EDO feature:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
page size 4096, count of eraseblocks 400,
pages per eraseblock 128, OOB size 218
.......................................
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 3632 KiB/s
.......................................
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 3554 KiB/s
.......................................
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 3592 KiB/s
.......................................
=================================================
2) The test result AFTER we add the EDO feature:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
page size 4096, count of eraseblocks 400,
pages per eraseblock 128, OOB size 218
.......................................
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 19555 KiB/s
.......................................
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 17319 KiB/s
.......................................
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 18339 KiB/s
.......................................
=================================================
3) The read data performance is much improved by more then 5 times.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The default frequencies of the extra clocks are 200MHz.
The current code sets the extra clocks to 44.5MHz.
When i add the EDO feature to gpmi, i have to revert the extra clocks
to 200MHz.
So it is better that we do not set the default values for the extra
clocks. The driver runs well even when we do not set the default values for
extra clocks.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The setting DLL code is a little mess.
Just simplify the code and the comments.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
add the WRN_DLY_SEL field for HW_GPMI_CTRL1.
This field is used as delay for gpmi write strobe.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The current code will gets the clock frequency which is used by
gpmi_nfc_compute_hardware_timing(). It makes the code a little mess.
So move the `get clock frequency` code to the
gpmi_nfc_compute_hardware_timing() itself. This makes the code tidy
and clean.
This patch also uses the macro NSEC_PER_SEC to replace the `1000000000`.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The gpmi_nfc_compute_hardware_timing{} should contains all the
fields setting for gpmi timing registers. It already contains the fields
for HW_GPMI_TIMING0 and HW_GPMI_CTRL1.
So it is better to add a new field setting for HW_GPMI_TIMING1 in
this data structure. This makes the code more clear in logic.
This patch also changes some comments to make the code more readable.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Add the set-features(0xef)/get-features(0xee) helpers for ONFI nand.
Also add the necessary macros.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
If override size is too big, the module was actually loaded instead of
failing, because retval was not set.
This lead to memory corruption with the use of the freed structs nandsim
and nand_chip.
Cc: stable@vger.kernel.org
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Currently the docg4's ecc.read_page() method returns -EBADMSG when
uncorrectable bitflips occur. This is wrong; 0 should be returned in
this case. An error code should only be returned by this method in the
case of a hardware error (probably -EIO).
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
In nand_bbt.c, a hardcoded value was used instead of the define meant
for that, so we use the define.
There's no functional change.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This driver is being removed as part of the cleanup of the bcmring
SoC from mainline as it is no longer maintained.
Signed-off-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Jiandong Zheng <jdzheng@broadcom.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
As a first step towards migrating davinci platforms to use common clock
framework, replace all instances of clk_enable() with clk_prepare_enable()
and clk_disable() with clk_disable_unprepare(). Until the platform is
switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
adds a might_sleep() call and would work without any issues.
This will make it easy later to switch to common clk based implementation
of clk driver from DaVinci specific driver.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
With the new i.mx clock framework the mxc_nand clock is registered as:
clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");0")
So we do not need to pass "nfc" string and can use NULL instead.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Using module_platform_driver() makes the code smaller and cleaner.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Using module_platform_driver() makes the code smaller and cleaner.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Unloading the omap2 nand driver missed to release the memory region which will
result in not being able to request it again if one want to load the driver
later on.
This patch fixes following error when loading omap2 module after unloading:
---8<---
~ $ rmmod omap2
~ $ modprobe omap2
[ 37.420928] omap2-nand: probe of omap2-nand.0 failed with error -16
~ $
--->8---
This error was introduced in 67ce04bf27 which
was the first commit of this driver.
Signed-off-by: Andreas Bießmann <andreas@biessmann.de>
Cc: stable@vger.kernel.org
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Added a NAND device flag for subpage read support. Previously this was
hard coded based on large page and soft ECC.
Updated base NAND driver to use the new subpage read flag if the NAND is
large page and soft ECC.
Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
Reviewed-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Commit abcda1dc ('arm: plat-orion: introduce PLAT_ORION_LEGACY hidden
config option') currently pending in linux-next will make the ARCH_MVEBU
platform select PLAT_ORION, which means that now all Orion drivers can
be enabled on ARCH_MVEBU. This works fine for most drivers, except for
orion_nand, because it includes <mach/hardware.h>, but mach-mvebu does
not have a mach/hardware.h header (it is considered as a deprecated
practice).
It turns out that the <mach/hardware.h> include in orion_nand is not
necessary: the driver builds perfectly fine without it, so we simply
get rid of it.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The LPC32xx's DT-only conversion of the MLC NAND driver makes NAND config via
platform_data obsolete. Dropped by this patch.
Further, the driver really needs CONFIG_OF, which is already reflected by the
dependency on ARCH_LPC32XX which depends on CONFIG_OF. So also dropping
CONFIG_OF ifdefs.
There is still platform_data necessary to supply the dma_filter callback for
the dma engine. This is a completely different data structure than the old
platform_data for NAND config, so renaming some old "pdata" variable to "ncfg"
to prevent confusion with the new platform data.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The LPC32xx's DT-only conversion of the SLC NAND driver makes NAND config via
platform_data obsolete. Dropped by this patch.
Further, the driver really needs CONFIG_OF, which is already reflected by the
dependency on ARCH_LPC32XX which depends on CONFIG_OF. So also dropping
CONFIG_OF ifdefs.
There is still platform_data necessary to supply the dma_filter callback for
the dma engine. This is a completely different data structure than the old
platform_data for NAND config, so renaming some old "pdata" variable to "ncfg"
to prevent confusion with the new platform data.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Allow MTD_NAND_GPMI_NAND to be built as module.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When building MTD_NAND_GPMI_NAND as module, the following error shows up:
ERROR: "nand_update_bbt" [drivers/mtd/nand/gpmi-nand/gpmi_nand.ko] undefined!
Export nand_update_bbt to fix it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Rename 'len' variable of create_bbt/scan_block_fast/scan_block_full to
'numpages', since it really means number of pages to scan when
searching for the BBM (and not the byte length of the scan).
Signed-off-by: Shmulik Ladkani <shmulik.ladkani@gmail.com>
Reviewed-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Fixes the following warnings:
‘s3c2410_nand_correct_data’ defined but not used [-Wunused-function]
‘s3c2410_nand_enable_hwecc’ defined but not used [-Wunused-function]
‘s3c2412_nand_enable_hwecc’ defined but not used [-Wunused-function]
‘s3c2440_nand_enable_hwecc’ defined but not used [-Wunused-function]
‘s3c2410_nand_calculate_ecc’ defined but not used [-Wunused-function]
‘s3c2412_nand_calculate_ecc’ defined but not used [-Wunused-function]
‘s3c2440_nand_calculate_ecc’ defined but not used [-Wunused-function]
The above functions are called only when CONFIG_MTD_NAND_S3C2410_HWECC
is defined. Thus making them conditional.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
devm_* functions are device managed functions and make cleanup code
simpler and smaller.
devm_kzalloc, devm_clk_get and devm_request_and_ioremap functions
are used.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The driver uses plat_nand. As the platform_device is loaded from DT, we need
to lookup the node and attach our xway specific "struct platform_nand_data"
to it.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
If plat_nand loads and the platform_data is not properly set it will segfault.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Just as Artem suggested:
"Both UBI and JFFS2 are able to read verify what they wrote already.
There are also MTD tests which do this verification. So I think there
is no reason to keep this in the NAND layer, let alone wasting RAM in
the driver to support this feature. Besides, it does not work for sub-pages
and many drivers have it broken. It hurts more than it provides benefits."
So kill MTD_NAND_VERIFY_WRITE entirely.
Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
There is new format specified that helps to dump small buffers. It makes the
code simpler and nicer.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
add OF support for the davinci nand controller.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Fixes the following checkpatch warnings:
WARNING: line over 80 characters
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Fixes checkpatch warnings and errors related to whitespaces.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Fixes the following checkpatch errors:
ERROR: do not initialise statics to 0 or NULL
+static int hardware_ecc = 0;
ERROR: do not initialise statics to 0 or NULL
+static const int clock_stop = 0;
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Fixes the following checkpatch warning:
WARNING: Use #include <linux/io.h> instead of <asm/io.h>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This makes the code simpler by eliminating module_init() and
module_exit().
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Include IMX6 in the list of supported SoCs.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It
silently masks off at least one flag that might be set by the driver
(NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly
others.
Really, as long as driver writers exercise a small amount of care with
NAND_* options, this mask is not necessary at all; it was only here to
prevent certain options from accidentally being set by the driver. But the
original thought turns out to be a bad idea occasionally. Thus, kill it.
Note, this patch fixes some major gpmi-nand breakage.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Huang Shijie <shijie8@gmail.com>
Cc: stable@vger.kernel.org
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
without this the gpio will not be muxed as a gpio by the current custom pinmux
or later by the pinctrl
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch does two closely related things:
(1) Currently the ecc.read_page() method does not fill the nand->oob_poi buffer
with the oob data, but instead reads oob into a local buffer. Fix this by
filling the oob_poi buffer instead of a local buffer. The 'oob_required'
argument is quietly ignored; the device must always read oob after the page
data, and it is presumed that there's no harm in filling oob_poi, even when not
explicitly requested.
(2) Always read oob from the device in ecc.read_oob(), instead of copying it
from a local buffer under some circumstances.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch makes the MLC NAND driver independent of the single AMBA DMA engine
driver by using the platform data provided dma_filter callback.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch makes the SLC NAND driver independent of the single AMBA DMA engine
driver by using the platform data provided dma_filter callback.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
None of these scanning functions use MTD_OPS_RAW mode any more, so there's
really nothing 'raw' about them. Rename them to (hopefully) make the code
a little clearer.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
scan_read_raw_oob() is used in only in places where the MTD_OPS_PLACE_OOB mode
is preferable to MTD_OPS_RAW mode, so use MTD_OPS_PLACE_OOB instead.
MTD_OPS_PLACE_OOB provides the same functionality with the potential[1] added
bonus of error correction.
This brings scan_block_full() in line with scan_block_fast() so that they
both read bad block markers with MTD_OPS_PLACE_OOB. This can help in
preventing 0xff markers (in good blocks) from being interpreted as bad
block indicators in the presence of a single bitflip.
Note that ECC error codes (EUCLEAN or EBADMSG) are already silently
ignored in all users of scan_read_raw_oob().
[1] Few drivers perform proper error correction on OOB data. In those
cases, the use of MTD_OPS_RAW vs. MTD_OPS_PLACE_OOB is not
significant.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Some nand_bbt code can be shortened by using memcmp() and memchr_inv().
As an added bonus, there is a possible performance benefit.
Borrowed some code from Akinobu Mita.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The return codes for read_abs_bbts() and search_read_bbts() are always
non-zero, and so don't have much meaning. Just remove them.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Shmulik Ladkani <shmulik.ladkani@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
The gpmi nand driver may needs several clocks(MX6Q needs five clocks).
In the old clock framework, all these clocks are chained together,
all you need is to manipulate the first clock.
But the kernel uses the common clk framework now, which forces us to
get the clocks one by one. When we use them, we have to enable them
one by one too.
Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Check the new oob_required flag and only copy the OOB data to the internal
buffer if needed.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Elements have been copied "manually" in a loop. Better use memcpy().
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Reviewed-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
implemented in IFC for any "system side write" into sram buffer. Reading an
uninitialized memory results in ECC Error from sram wrapper.
Hence we must initialize/prefill SRAM buffer by any data before writing
anything in SRAM from system side. To initialize SRAM user can use "READID"
NAND command with read bytes equal to SRAM size. It will be a one time
activity post boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This is only used by omap1.
And to fix things properly, this should not be included
from the drivers at all.
Acked-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: linux-fbdev@vger.kernel.org
Cc: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com>
Cc: linux-mtd@lists.infradead.org
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: linux-input@vger.kernel.org
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Liam Girdwood <lrg@ti.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: alsa-devel@alsa-project.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
Note that this branch is based on omap-cleanup-sparseirq-for-v3.7
to avoid merge conflicts with the sparseirq changes for gpio-twl4030
driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQVlRgAAoJEBvUPslcq6VzbSwP/RNdw33WTv7slY8v2x9C+jfe
fzpJltqtWf1xLQ5ixAMwzBxc4/I+m/fz3ZhxG15amqD1sQuwDNNVwI6D5F4pIH4K
ZfyaeA8jteH487f7PxMlurtVYgPRqLrMXBahxKgcM6WwJ0tFspGuXQeKMhjhRnYJ
4+0GQ/R60UmexyAF4Ish4YfVfe0Iy8deVuGjOO7xIdsKrC1uymXbT7HB0o7Tz4tj
btsEUXs4UMCh2VoYzqVxaP1uMumOnuVOFOuWjcNOni3TMdjmllPpoApsXE27rNKC
0D/MzCyutFEO7q7/8TSUs3TOy+my18Z6Fz9hEkw7fUOOXQ3iUDqI79FbvMv9mWe+
nW2BFZZCeuTqErGNakgluGtasLOfvqOqzSO7U68XGgHp86G42N2EDs4raTDAeKTN
YXzLSiPYvV5QOUFbP5uagiKFcFUbcfNYZytTPwZ8hBk4hXtDmwqhSEgzxhAKGtgx
y0ljt3iQNxk3EVhIv7oi0FxCFX2ioikYPTOlHkpvNwkXa7ruvvU1CudIGSdZ/Nn3
SoEkRDwx6CpA37aAusfWioYKWhrctfDBl9Nt0IXwZy1b0MO1QIUaL0RY3Y5FsES+
25MP+5Ns6nkmzzTs72Gu+W9bL6E3eHAkAoaDb9JPH2Jix8vXRMgIISyu9Fzze504
ypeFe5TtLc/uYkviZhi6
=fzT6
-----END PGP SIGNATURE-----
Merge tag 'omap-devel-dt-merged-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Device tree related changes for omaps.
Note that this branch is based on omap-cleanup-sparseirq-for-v3.7
to avoid merge conflicts with the sparseirq changes for gpio-twl4030
driver.
* tag 'omap-devel-dt-merged-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
arm/dts: Mux uart pins for omap4-sdp
ARM: OMAP2+: select PINCTRL in Kconfig
arm/dts: Add pinctrl driver entries for omap2/3/4
arm/dts: Add omap36xx.dtsi file and rename omap3-beagle to omap3-beagle-xm
ARM: dts: omap3-overo: Add support for the blue LED
Documentation: dt: Update the OMAP documentation with Overo/Toby
ARM: dts: OMAP3: Add support for Gumstix Overo with Tobi expansion board
ARM: dts: OMAP4: Add reg and interrupts for every nodes
ARM: dts: AM33XX: Specify reg and interrupt property for all nodes
ARM: dts: AM33XX: Convert all hex numbers to lower-case
ARM: dts: omap3-beagle: Enable audio support
ARM: dts: omap5: Add McPDM and DMIC section to the dtsi file
ARM: dts: omap5: Add McBSP entries
ARM: dts: omap4: Add reg-names for McPDM and DMIC
ARM: dts: omap4: Add McBSP entries
ARM: dts: omap3: Add McBSP entries
ARM: dts: omap2420-h4: Include omap2420.dtsi file instead the common omap2
ARM: dts: omap2: Add McBSP entries for OMAP2420 and OMAP2430 SoC
ARM: dts: omap3-beagle: Add heartbeat and mmc LEDs support
ARM: dts: omap3: Add gpio-twl4030 properties for BeagleBoard and omap3-EVM
...
Platform data for device drivers should be defined in
include/linux/platform_data/*.h, not in the architecture
and platform specific directories.
This moves such data out of the samsung include directories
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Jeff Garzik <jgarzik@pobox.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: "Wolfram Sang (embedded platforms)" <w.sang@pengutronix.de>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Bryan Wu <bryan.wu@canonical.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Chris Ball <cjb@laptop.org>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Sangbeom Kim <sbkim73@samsung.com>
Cc: Liam Girdwood <lrg@ti.com>
Cc: linux-samsung-soc@vger.kernel.org
Platform data for device drivers should be defined in
include/linux/platform_data/*.h, not in the architecture
and platform specific directories.
This moves such data out of the orion include directories
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Dan Williams <djbw@fb.com>
Cc: Bryan Wu <bryan.wu@canonical.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Chris Ball <cjb@laptop.org>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Liam Girdwood <lrg@ti.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.de>
Platform data for device drivers should be defined in
include/linux/platform_data/*.h, not in the architecture
and platform specific directories.
This moves such data out of the omap include directories
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: "Benoît Cousson" <b-cousson@ti.com>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Ohad Ben-Cohen <ohad@wizery.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Omar Ramirez Luna <omar.ramirez@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Jarkko Nikula <jarkko.nikula@bitmer.com>
Cc: Liam Girdwood <lrg@ti.com>
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Cc: Jean Pihet <j-pihet@ti.com>
Cc: J Keerthy <j-keerthy@ti.com>
Cc: linux-omap@vger.kernel.org
work properly with sparse IRQ. It also removes
dependencies to mach/hardware.h. These help moving
things towards ARM single zImage support.
This branch is based on a commit in tty-next
branch with omap-devel-gpmc-fixed-for-v3.7 and
cleanup-omap-tags-for-v3.7 merged in to keep things
compiling and sort out some merge conflicts.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJQUUgbAAoJEBvUPslcq6VzsEgQANbHSsPDajdFnaCn3goS16M3
Nwmnvqd3Ay4VqhLpJuiF9SWzPtCno0gu/9caUKhodYDrHDVttdMKQWKLsmkSPFOD
uHnKToA3y0J5O/KQJB+bubinZvcHNnBwCgP6YFposFwH561aCRhp4DiCIlqAiqlV
g6jyEtTkOrIyHULokgFSmWrLDcTxvx4lWyZbmeltju4KXzzfPojc6m4daVN9Z3cQ
VP9+6mLuJcF/aIbdyGnxg7pgsfy6+roHI1+vHfufVEyTt1funm1Mt1Wq+kUFC0XW
YRQILq82tr3OgvcB3xmXllE3XcklN4Vv922Up0fQ+8OV36jA2q6N5vTsk8fctuD4
8O+j4kmomCEavj2JEIB5SFfsZ+Cdycx79+1pvOtDSYOM7svFpQs6kdhq+JXGRSql
W00xgLQj82tmXpaLV36pXPGoc7ZXQolQbc6SYFQn8oHTTvHDdFiQkG5TKafj7r5u
ayaV/VqytSy+Hiq8XWNpEjfxn467fQ5UmHXQoVAIZnpk323SpPbLQ5aDOMk/9+DT
u0mDnIP4k6w8ViTnalLPEBOqqpZZo358t+cRD1kD55X4IR2YPSFhrhJTq23Z9Rv3
EW9ZUQYrK6WDuYO8/4SZ1J/HTx5MFb1Na6dKAXwO3v0S7CBzIbN9gqbU7IxfQ8ZA
qKT726r923PHKL2x8VZc
=GLSh
-----END PGP SIGNATURE-----
Merge tag 'omap-cleanup-sparseirq-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
From Tony Lindgren:
This branch contains changes needed to make omap2+
work properly with sparse IRQ. It also removes
dependencies to mach/hardware.h. These help moving
things towards ARM single zImage support.
This branch is based on a commit in tty-next
branch with omap-devel-gpmc-fixed-for-v3.7 and
cleanup-omap-tags-for-v3.7 merged in to keep things
compiling and sort out some merge conflicts.
* tag 'omap-cleanup-sparseirq-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP1: Move SoC specific headers from plat to mach for omap1
ARM: OMAP2+ Move SoC specific headers to be local to mach-omap2
ARM: OMAP: Split plat/hardware.h, use local soc.h for omap2+
ARM: OMAP: Remove unused old gpio-switch.h
ARM: OMAP1: Move plat/irqs.h to mach/irqs.h
ARM: OMAP2+: Remove hardcoded IRQs and enable SPARSE_IRQ
ARM: OMAP2+: Prepare for irqs.h removal
W1: OMAP HDQ1W: Remove dependencies to mach/hardware.h
Input: omap-keypad: Remove dependencies to mach includes
ARM: OMAP: Move gpio.h to include/linux/platform_data
ARM: OMAP2+: Remove hardcoded twl4030 gpio_base, irq_base and irq_end
ARM: OMAP2+: Remove unused nand_irq for GPMC
ARM: OMAP2+: Make INTCPS_NR_IRQS local for mach-omap2/irq.c
ARM: OMAP1: Define OMAP1_INT_I2C locally
ARM: OMAP1: Move define of OMAP_LCD_DMA to dma.h
This branch contains a number of fixes and cleanups to the Tegra I2C
driver related to clocks. These are based on the common clock conversion
in order to avoid duplicating the clock driver changes before and after
the conversion. Finally, a bug-fix related to I2C_M_NOSTART is included.
This branch is based on previous pull request tegra-for-3.7-common-clk.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJQU4B/AAoJEMzrak5tbycx+3gQALBx5JjQ+k16znW4iTSJKtWr
3wm5npiu9mk60b1vk5n0jRWpF532gkghdLDYs5AcXDxBhC6hq+LvHUXiEEY7oEya
bsIuYMw0WKGrRXEGBvxDaOJ69XCyMOpaDCS9mQyy/iT40eskYBykvSsdDMP86LxS
GS/Dk+Vj59A2wWXBV0IrS9PbS1tHp7W8yxrKw0yUF8vZk5wFFga9LnDp8xUOqSrE
3kBygS2TtrMuIu85ZkO3n/I62xkAQih9KU1WvKLciw5mAKxWsNVMGA59CyY4Qu7Q
0Dr+TIrelbJYBagmSnAciEnegNbxNVYOoKja/dWNs+hZPDO/YVz55vrLecD2sEHe
/jlo0c2GfS10SakrTnzFdWMfmcEHpDLMnPaBmCluh9ivBQ/wKsqrJQIMQV8tUU50
+0vBfx5/aXfrUrzQNLSZncW2MvywFuM5Rt5ODKziNTunnbSTYnbNby07SJLGllVf
OlCWdpS5agkbio/50BiunnMwBkDmmCrga2gVdMbBOx5hiktMDHW7rWe6q9XqY7yW
3fYaaSmsS3WpIVRSqkL3kd2BY4hEoG5Mk0G+/a/kF9DOb9BQSu4HxEC6U1+Jy+Dy
ewvAZPsYnUiI+kq2RdqJN8QDv8CKbySM3iUNG55/JUkQNC8rcoBC0OVh6XAM5fXd
QVPCiYngnSE5LS0CTCC+
=6+9B
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.7-drivers-i2c' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers
From Stephen Warren:
ARM: tegra: i2c driver enhancements mostly related to clocking
This branch contains a number of fixes and cleanups to the Tegra I2C
driver related to clocks. These are based on the common clock conversion
in order to avoid duplicating the clock driver changes before and after
the conversion. Finally, a bug-fix related to I2C_M_NOSTART is included.
This branch is based on previous pull request tegra-for-3.7-common-clk.
* tag 'tegra-for-3.7-drivers-i2c' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
i2c: tegra: dynamically control fast clk
i2c: tegra: I2_M_NOSTART functionality not supported in Tegra20
ARM: tegra: clock: remove unused clock entry for i2c
ARM: tegra: clock: add connection name in i2c clock entry
i2c: tegra: pass proper name for getting clock
ARM: tegra: clock: add i2c fast clock entry in clock table
ARM: Tegra: Add smp_twd clock for Tegra20
ARM: tegra: cpu-tegra: explicitly manage re-parenting
ARM: tegra: fix overflow in tegra20_pll_clk_round_rate()
ARM: tegra: Fix data type for io address
ARM: tegra: remove tegra_timer from tegra_list_clks
ARM: tegra30: clocks: fix the wrong tegra_audio_sync_clk_ops name
ARM: tegra: clocks: separate tegra_clk_32k_ops from Tegra20 and Tegra30
ARM: tegra: Remove duplicate code
ARM: tegra: Port tegra to generic clock framework
ARM: tegra: Add clk_tegra structure and helper functions
ARM: tegra: Rename tegra20 clock file
ARM: tegra20: Separate out clk ops and clk data
ARM: tegra30: Separate out clk ops and clk data
ARM: tegra: fix U16 divider range check
...
+ sync to v3.6-rc4
Resolved remove/modify conflict in arch/arm/mach-sa1100/leds-hackkit.c
caused by the sync with v3.6-rc4.
Signed-off-by: Olof Johansson <olof@lixom.net>
Platform data for device drivers should be defined in
include/linux/platform_data/*.h, not in the architecture
and platform specific directories.
This moves such data out of the nomadik include directories
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Felipe Balbi <balbi@ti.com>
Acked-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: STEricsson <STEricsson_nomadik_linux@list.st.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Andreas Westin <andreas.westin@stericsson.com>
Platform data for device drivers should be defined in
include/linux/platform_data/*.h, not in the architecture
and platform specific directories.
This moves such data out of the pxa include directories
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Jeff Garzik <jgarzik@redhat.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Paul Parsons <lost.distance@yahoo.com>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Acked-By: Stefan Schmidt <stefan@openezx.org>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Cc: Daniel Ribeiro <drwyrm@gmail.com>
Cc: Harald Welte <laforge@openezx.org>
Cc: Philipp Zabel <philipp.zabel@gmail.com>
Cc: Tomas Cech <sleep_walker@suse.cz>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Jonathan Cameron <jic23@cam.ac.uk>
Cc: Dan Williams <djbw@fb.com>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Chris Ball <cjb@laptop.org>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Samuel Ortiz <samuel@sortiz.org>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Liam Girdwood <lrg@ti.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Cc: openezx-devel@lists.openezx.org
Platform data for device drivers should be defined in
include/linux/platform_data/*.h, not in the architecture
and platform specific directories.
This moves such data out of the imx include directories
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Acked-by: Sascha Hauer <kernel@pengutronix.de>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Dan Williams <djbw@fb.com>
Cc: "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>
Cc: "Wolfram Sang (embedded platforms)" <w.sang@pengutronix.de>
Cc: Chris Ball <cjb@laptop.org>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: Liam Girdwood <lrg@ti.com>
Cc: Javier Martin <javier.martin@vista-silicon.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Platform data for device drivers should be defined in
include/linux/platform_data/*.h, not in the architecture
and platform specific directories.
This moves such data out of the davinci include directories
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: "Ben Dooks" <ben-linux@fluff.org>
Cc: "Wolfram Sang" <w.sang@pengutronix.de>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Chris Ball <cjb@laptop.org>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Liam Girdwood <lrg@ti.com>
Cc: davinci-linux-open-source@linux.davincidsp.com
This way we can remove includes of plat/gpio.h which won't work
with the single zImage support.
Note that we also remove the cpu_class_is_omap2() check
in gpio-omap.c as the drivers should not call it as we need to
make it local to arch/arm/mach-omap2 for single zImage support.
While at it, arrange the related includes in the standard way.
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: linux-mtd@lists.infradead.org
Cc: alsa-devel@alsa-project.org
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
* 'soc-core' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: mach-shmobile: Add compilation support for dtbs using 'make dtbs'
+ sync to 3.6-rc3
The io-pci series has gained a merge to resolve a nontrivial
conflict.
* cleanup/io-pci:
ARM: Fix ioremap() of address zero
Also includes an update to Linux 3.6-rc3
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
GPMC platform initialization provides it's clients
with interrupts that can be used through struct
resource. Make use of it for irq mode functionality.
Also now write protect disable is done by GPMC,
hence remove it.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
[tony@atomide.com: updated to fix new warnings introduced]
Signed-off-by: Tony Lindgren <tony@atomide.com>
gpmc initialization done by platform code now updates struct resource
with the address space alloted for nand. Use this interface to obtain
memory rather than relying on platform data field - phys_base.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPMC platform initialization has been modified to fill NAND
platform data with GPMC NAND register details. As these
registers are accessible in NAND driver itself, configure
NAND in GPMC by itself.
Modified prefetch and ecc functions are logically same as
the corresponding exported symbols from GPMC code.
Note: Verfying that other CS have not yet enabled for
prefetch & ecc has to be incorporated. Currently this
causes no issues as there are no boards that use NAND
on multiple CS. With ongoing GPMC driver migration,
perhaps it would be better to consider NAND connected
on multiple CS as a single peripheral using multiple CS.
This would make handling multiple CS issues easier.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.18 (GNU/Linux)
iQEcBAABAgAGBQJQLWtvAAoJEHm+PkMAQRiG/DYH+wd0FqfEuYkYk4KPyAPuhKpX
zX7HYfLvyJE/ZYIdrhjq1E6Xm2KNr7gtX7/Rdzi2W38M9sjbYzwG1UGIw51qnxWy
yZJH9BGkfyQgQPeuDGohfB6DkDy2JWr2eqMDvakjOwgBsIzji0PQD/f3UvndhtUa
c+tTj/kjavHE1Yr2Wy6OnRZz3Uc0hIMn/Q0JqtbCs3LUgEV1KA4OEAe56XNz4Ku4
WE+FFaGFPvtriQsQON+ohPS5IC8jzQGK/0vbrJ4lWjFnZy4gvZXnborTOwD0WSQG
fbsNuxp1AaM2/pqfMwXm1w0ADvwOITHNiwwXf9id6DoK81QwTFpUdvKpn6yB6gQ=
=rurr
-----END PGP SIGNATURE-----
Merge tag 'v3.6-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux
Having missed the merge window, update to 3.6-rc2 to avoid conflicts with
new patches.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This patch contains a hack to get the DMA resources of the device when
probed from a devicetree node. This can be removed once a generic DMA
controller framework lands.
A mtd_part_parser_data is passed mtd_device_parse_register which
contains a reference to the device node, so MTD partitions can be
added as children.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
AT91 SoC related code modifications: a cleanup in defconfigs and
a one liner in a board file.
The most important is the move to atmel-mci driver in AT91 SoC & boards.
The old at91_mci (marked as deprecated) will be removed in 3.7. So all
platform data for this old driver are erased and replace by information
needed by atmel-mci driver.
* tag 'at91-for-next-soc' of git://github.com/at91linux/linux-at91:
ARM: at91: add atmel-mci support for chips and boards which can use it
ARM: at91/defconfig: change the MCI driver to use in defconfigs
ARM: at91: set i2c_board_info.type to "ds1339" directly
ARM: at91/defconfig: Remove unaffected config option
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This attempts to get the bcmring platform better in line with the
other platforms. Moving the header files below mach/ helps with
the future reorganization for multiplatform kernels, and using
MMIO accessors is generally the right thing.
* testing/bcmring:
ARM: bcmring: use proper MMIO accessors
ARM: bcmring: remove include/csp/ subdir
ARM: bcmring: move cfg_global header to mach/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
These patches all fix bugs that were newly introduced in v3.6-rc1
and found because they cause a gcc warning with one of the ARM
defconfigs. Most of them are harmless, but since we're trying
to get rid of all warnings eventually, we can start with the ones
that were not there before.
* testing/new-warnings:
omap-rng: fix use of SIMPLE_DEV_PM_OPS
spi/s3c64xx: improve error handling
mtd/omap2: fix dmaengine_slave_config error handling
gpio: em: do not discard em_gio_irq_domain_cleanup
ARM: exynos: exynos_pm_add_dev_to_genpd may be unused
usb/ohci-omap: remove unused variable
mfd/asic3: fix asic3_mfd_probe return value
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The newly added dmaengine support in the omap2 nand driver
potentially causes an undefined return value from the
omap_nand_probe function when dmaengine_slave_config
reports an error. Let's handle this by returning the
same error back to the caller.
Without this patch, building omap2plus_defconfig results in:
drivers/mtd/nand/omap2.c: In function 'omap_nand_probe':
drivers/mtd/nand/omap2.c:1154:6: warning: 'err' may be used uninitialized in this function [-Wuninitialized]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Grazvydas Ignotas <notasas@gmail.com>
It is not currently possible to build the gpmi-nand driver without
also building the mxs-dma driver. Clarify this Kconfig and enable
both in the defconfig file so we can build it again with both enabled.
drivers/built-in.o: In function `gpmi_dma_filter':
clk-fixed-factor.c:(.text+0xafc18): undefined reference to `mxs_dma_is_apbh'
make[1]: *** [vmlinux] Error 1
make: *** [sub-make] Error 2
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Pull ARM DMA engine updates from Russell King:
"This looks scary at first glance, but what it is is:
- a rework of the sa11x0 DMA engine driver merged during the previous
cycle, to extract a common set of helper functions for DMA engine
implementations.
- conversion of amba-pl08x.c to use these helper functions.
- addition of OMAP DMA engine driver (using these helper functions),
and conversion of some of the OMAP DMA users to use DMA engine.
Nothing in the helper functions is ARM specific, so I hope that other
implementations can consolidate some of their code by making use of
these helpers.
This has been sitting in linux-next most of the merge cycle, and has
been tested by several OMAP folk. I've tested it on sa11x0 platforms,
and given it my best shot on my broken platforms which have the
amba-pl08x controller.
The last point is the addition to feature-removal-schedule.txt, which
will have a merge conflict. Between myself and TI, we're planning to
remove the old TI DMA implementation next year."
Fix up trivial add/add conflicts in Documentation/feature-removal-schedule.txt
and drivers/dma/{Kconfig,Makefile}
* 'dmaengine' of git://git.linaro.org/people/rmk/linux-arm: (53 commits)
ARM: 7481/1: OMAP2+: omap2plus_defconfig: enable OMAP DMA engine
ARM: 7464/1: mmc: omap_hsmmc: ensure probe returns error if DMA channel request fails
Add feature removal of old OMAP private DMA implementation
mtd: omap2: remove private DMA API implementation
mtd: omap2: add DMA engine support
spi: omap2-mcspi: remove private DMA API implementation
spi: omap2-mcspi: add DMA engine support
ARM: omap: remove mmc platform data dma_mask and initialization
mmc: omap: remove private DMA API implementation
mmc: omap: add DMA engine support
mmc: omap_hsmmc: remove private DMA API implementation
mmc: omap_hsmmc: add DMA engine support
dmaengine: omap: add support for cyclic DMA
dmaengine: omap: add support for setting fi
dmaengine: omap: add support for returning residue in tx_state method
dmaengine: add OMAP DMA engine driver
dmaengine: sa11x0-dma: add cyclic DMA support
dmaengine: sa11x0-dma: fix DMA residue support
dmaengine: PL08x: ensure all descriptors are freed when channel is released
dmaengine: PL08x: get rid of write only pool_ctr and free_txd locking
...
Remove the private DMA API implementation from nand/omap2.c
making it use entirely the DMA engine API.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add DMA engine support to the OMAP2 NAND driver. This supplements the
private DMA API implementation contained within this driver, and the
driver can be independently switched at build time between using DMA
engine and the private DMA API.
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Pull MIPS updates from Ralf Baechle:
"More hardware support across the field including a bunch of device
drivers. The highlight however really are further steps towards
device tree.
This has been sitting in -next for ages. All MIPS _defconfigs have
been tested to boot or where I don't have hardware available, to at
least build fine."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (77 commits)
MIPS: Loongson 1B: Add defconfig
MIPS: Loongson 1B: Add board support
MIPS: Netlogic: early console fix
MIPS: Netlogic: Fix indentation of smpboot.S
MIPS: Netlogic: remove cpu_has_dc_aliases define for XLP
MIPS: Netlogic: Remove unused pcibios_fixups
MIPS: Netlogic: Add XLP SoC devices in FDT
MIPS: Netlogic: Add IRQ mappings for more devices
MIPS: Netlogic: USB support for XLP
MIPS: Netlogic: XLP PCIe controller support.
MIPS: Netlogic: Platform changes for XLR/XLS I2C
MIPS: Netlogic: Platform NAND/NOR flash support
MIPS: Netlogic: Platform changes for XLS USB
MIPS: Netlogic: Remove NETLOGIC_ prefix
MIPS: Netlogic: SMP wakeup code update
MIPS: Netlogic: Update comments in smpboot.S
MIPS: BCM63XX: Add 96328avng reference board
MIPS: Expose PCIe drivers for MIPS
MIPS: BCM63XX: Add PCIe Support for BCM6328
MIPS: BCM63XX: Move the PCI initialization into its own function
...
The clk patches added code to get and enable clocks in the
respective driver probe functions. If the probe function failed
for some reason after enabling the clock, the clock was not
disabled again in many cases.
Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
Signed-off-by: Andrew Lumm <andrew@lunn.ch>
The platform data can now specify which external memory banks to probe
for NAND chips, and in which order. Banks that contain a NAND are used
and the other banks are freed.
Squashed version of development done in jz-2.6.38 branch.
Original patch by Lars-Peter Clausen with some bug fixes from me.
Thanks to Paul Cercueil for the initial autodetection patch.
Signed-off-by: Maarten ter Huurne <maarten@treewalker.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3560/
Acked-By: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The origin code misses to update the bitflip_threshold when
we have already get the right ecc_strength.
The patch fixes it.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
add the on flash bbt support for gpmi nand driver.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
