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339 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Linus Torvalds
|
498574970f |
RISC-V Patches for the 6.1 Merge Window, Part 2
* A handful of DT updates for the PolarFire SOC.
* A fix to correct the handling of write-only mappings.
* m{vetndor,arcd,imp}id is now in /proc/cpuinfo
* The SiFive L2 cache controller support has been refactored to also
support L3 caches.
There's also a handful of fixes, cleanups and improvements throughout
the tree.
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Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Palmer Dabbelt:
- DT updates for the PolarFire SOC
- a fix to correct the handling of write-only mappings
- m{vetndor,arcd,imp}id is now in /proc/cpuinfo
- the SiFive L2 cache controller support has been refactored to also
support L3 caches
- misc fixes, cleanups and improvements throughout the tree
* tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits)
MAINTAINERS: add RISC-V's patchwork
RISC-V: Make port I/O string accessors actually work
riscv: enable software resend of irqs
RISC-V: Re-enable counter access from userspace
riscv: vdso: fix NULL deference in vdso_join_timens() when vfork
riscv: Add cache information in AUX vector
soc: sifive: ccache: define the macro for the register shifts
soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes
soc: sifive: ccache: reduce printing on init
soc: sifive: ccache: determine the cache level from dts
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache
riscv: check for kernel config option in t-head memory types errata
riscv: use BIT() marco for cpufeature probing
riscv: use BIT() macros in t-head errata init
riscv: drop some idefs from CMO initialization
riscv: cleanup svpbmt cpufeature probing
riscv: Pass -mno-relax only on lld < 15.0.0
RISC-V: Avoid dereferening NULL regs in die()
dt-bindings: riscv: add new riscv,isa strings for emulators
...
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Conor Dooley
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8262499426
|
dt-bindings: timer: sifive,clint: add legacy riscv compatible
While "real" hardware might not use the compatible string "riscv,clint0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint'] Reported-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220823183319.3314940-2-mail@conchuod.ie Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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Linus Torvalds
|
706eacadd5 |
Devicetree updates for v6.1:
DT core:
- Fix node refcounting in of_find_last_cache_level()
- Constify device_node in of_device_compatible_match()
- Fix 'dma-ranges' handling in bus controller nodes
- Fix handling of initrd start > end
- Improve error reporting in of_irq_init()
- Taint kernel on DT unittest running
- Use strscpy instead of strlcpy
- Add a build target, dt_compatible_check, to check for
compatible strings used in kernel sources against compatible strings
in DT schemas.
- Handle DT_SCHEMA_FILES changes when rebuilding
DT bindings:
- LED bindings for MT6370 PMIC
- Convert Mediatek mtk-gce mailbox, MIPS CPU interrupt controller,
mt7621 I2C, virtio,pci-iommu, nxp,tda998x, QCom fastrpc, qcom,pdc,
and arm,versatile-sysreg to DT schema format
- Add nvmem cells to u-boot,env schema
- Add more LED_COLOR_ID definitions
- Require 'opp-table' uses to be a node
- Various schema fixes to match QEMU 'virt' DT usage
- Tree wide dropping of redundant 'Device Tree Binding' in schema titles
- More (unevaluated|additional)Properties fixes in schema child nodes
- Drop various redundant minItems equal to maxItems
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Merge tag 'devicetree-for-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT core:
- Fix node refcounting in of_find_last_cache_level()
- Constify device_node in of_device_compatible_match()
- Fix 'dma-ranges' handling in bus controller nodes
- Fix handling of initrd start > end
- Improve error reporting in of_irq_init()
- Taint kernel on DT unittest running
- Use strscpy instead of strlcpy
- Add a build target, dt_compatible_check, to check for compatible
strings used in kernel sources against compatible strings in DT
schemas.
- Handle DT_SCHEMA_FILES changes when rebuilding
DT bindings:
- LED bindings for MT6370 PMIC
- Convert Mediatek mtk-gce mailbox, MIPS CPU interrupt controller,
mt7621 I2C, virtio,pci-iommu, nxp,tda998x, QCom fastrpc, qcom,pdc,
and arm,versatile-sysreg to DT schema format
- Add nvmem cells to u-boot,env schema
- Add more LED_COLOR_ID definitions
- Require 'opp-table' uses to be a node
- Various schema fixes to match QEMU 'virt' DT usage
- Tree wide dropping of redundant 'Device Tree Binding' in schema
titles
- More (unevaluated|additional)Properties fixes in schema child nodes
- Drop various redundant minItems equal to maxItems"
* tag 'devicetree-for-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (62 commits)
of: base: Shift refcount decrement in of_find_last_cache_level()
dt-bindings: leds: Add MediaTek MT6370 flashlight
dt-bindings: leds: mt6370: Add MediaTek MT6370 current sink type LED indicator
dt-bindings: mailbox: Convert mtk-gce to DT schema
of: base: make of_device_compatible_match() accept const device node
of: Fix "dma-ranges" handling for bus controllers
of: fdt: Remove unused struct fdt_scan_status
dt-bindings: display: st,stm32-dsi: Handle data-lanes in DSI port node
dt-bindings: timer: Add power-domains for TI timer-dm on K3
dt: Add a check for undocumented compatible strings in kernel
kbuild: take into account DT_SCHEMA_FILES changes while checking dtbs
dt-bindings: interrupt-controller: migrate MIPS CPU interrupt controller text bindings to YAML
dt-bindings: i2c: migrate mt7621 text bindings to YAML
dt-bindings: power: gpcv2: correct patternProperties
dt-bindings: virtio: Convert virtio,pci-iommu to DT schema
dt-bindings: timer: arm,arch_timer: Allow dual compatible string
dt-bindings: arm: cpus: Add kryo240 compatible
dt-bindings: display: bridge: nxp,tda998x: Convert to json-schema
dt-bindings: nvmem: u-boot,env: add basic NVMEM cells
dt-bindings: remoteproc: qcom,adsp: enforce smd-edge schema
...
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Linus Torvalds
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55be6084c8 |
A boring time, timekeeping, timers update:
- No core code changes - No new clocksource/event driver - Cleanup of the TI DM clocksource/event driver - The usual set of device tree binding updates - Small improvement, fixes and cleanups all over the place -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmM9dgsTHHRnbHhAbGlu dXRyb25peC5kZQAKCRCmGPVMDXSYoeg4D/9rJefRINQRwSQuoLfky42SLy5OZXlA OwAZn0waUNwAXyp8pJd+WO5ZD4lcOmBlgPWNDKW3cLo8+uGzZpHTuTQMBnnHzyek ny4y4haRySPR8KQF9Jr+JLmMZtQhUESVTUDZYSwtbka1zM3ys6rJOGBDV/fwCCK+ gSdvRjNCN3TtIkNtxWWsAF/Sk8ucK22shztsIRiqL2eCPuKmJ0gZUChnCs69ue+D K98B7qH/IPMMtVtgX/yTEpSZxyjGVXakW1IvL3Y4Zxwc7G6OGEiDLSmIEj0pGtYr Vt4yTvauIY7PL212J7agL1EcG7wwFy1pANaeZAIHgpewjc959b0q41Ht2bAMYH1Q hgNgRCn47v7Iz5Ko/QycTK4NoEqqEZtfwvLMEo55bi0RxcOGDpexQOtaLM1BCtJy EFOsdQr2NMQguKcn5qvOVW3+HJuLnYsvbHSGCIAoXHB93UtDM/edg8BCNJHGyTtH 9u/iv2hiKPYBjUG95NPo+mictuL5CmSaYNMlSdzDR5L/Eeke3Qp1zMPAxFK6FjTU eVi6C472n83C/EpGMpfi+ms2UK3E3Dy8QgwNEJN0mTzEHXPUCjdXFWEI72jeYyHy dV8rSzDg6B82iaZ17eVqCTL4GGyo+kT2a3j3qaUC/rp0MDys7yYkBI6csRTvETdQ ARwPYYQYkuEEeQ== =n458 -----END PGP SIGNATURE----- Merge tag 'timers-core-2022-10-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer updates from Thomas Gleixner: "A boring time, timekeeping, timers update: - No core code changes - No new clocksource/event driver - Cleanup of the TI DM clocksource/event driver - The usual set of device tree binding updates - Small improvement, fixes and cleanups all over the place" * tag 'timers-core-2022-10-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value clocksource/drivers/imx-sysctr: handle nxp,no-divider property dt-bindings: timer: nxp,sysctr-timer: add nxp,no-divider property clocksource/drivers/timer-ti-dm: Get clock in probe with devm_clk_get() clocksource/drivers/timer-ti-dm: Add flag to detect omap1 clocksource/drivers/timer-ti-dm: Move struct omap_dm_timer fields to driver clocksource/drivers/timer-ti-dm: Use runtime PM directly and check errors clocksource/drivers/timer-ti-dm: Move private defines to the driver clocksource/drivers/timer-ti-dm: Simplify register access further clocksource/drivers/timer-ti-dm: Simplify register writes with dmtimer_write() clocksource/drivers/timer-ti-dm: Simplify register reads with dmtimer_read() clocksource/drivers/timer-ti-dm: Drop unused functions clocksource/drivers/timer-gxp: Add missing error handling in gxp_timer_probe clocksource/drivers/arm_arch_timer: Fix handling of ARM erratum 858921 clocksource/drivers/exynos_mct: Enable building on ARTPEC clocksource/drivers/exynos_mct: Support local-timers property clocksource/drivers/exynos_mct: Support frc-shared property dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support clocksource/drivers/sun4i: Add definition of clear interrupt clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC ... |
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Tony Lindgren
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3b684d0467 |
dt-bindings: timer: Add power-domains for TI timer-dm on K3
On K3 SoCs, the power-domains property is needed. On the earlier SoCs, the power-domains property is handled by the interconnect target module parent device. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220919112357.64997-1-tony@atomide.com Signed-off-by: Rob Herring <robh@kernel.org> |
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Jean-Philippe Brucker
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90c46d12ba |
dt-bindings: timer: arm,arch_timer: Allow dual compatible string
Since the Armv7 and Armv8 architected timers are compatible, it is valid to expose a devicetree node with compatible string "arm,armv8-timer" followed by "arm,armv7-timer". For example a 32-bit guest running on a 64-bit machine may look for the v7 string even though the hardware is v8. VMMs such as QEMU and kvmtool have been using this compatible string for some time. Clean up the compatible list a little and add the dual option. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220922161149.371565-1-jean-philippe@linaro.org Signed-off-by: Rob Herring <robh@kernel.org> |
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Peng Fan
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061f42748d |
dt-bindings: timer: nxp,sysctr-timer: add nxp,no-divider property
The base clock input to system counter is internally divided by 3 in previous design, but there is change that no divider now. So add a property to indicate that. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220902111207.2902493-2-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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Vincent Whitchurch
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99b701fd27 |
dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support
The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global free-running counter and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots (via the A53), it should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this hardware, add a compatible for the MCT as well as two new properties to describe the hardware-mandated sharing of the FRC and dedicating local timers to specific processors. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220609112738.359385-2-vincent.whitchurch@axis.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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Rob Herring
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d2153e4cdf |
dt-bindings: timer: Add missing (unevaluated|additional)Properties on child nodes
In order to ensure only documented properties are present, node schemas must have unevaluatedProperties or additionalProperties set to false (typically). Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220823145649.3118479-16-robh@kernel.org |
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Andrew Lunn
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dd3cb467eb |
dt-bindings: Remove 'Device Tree Bindings' from end of title:
As indicated in link: https://lore.kernel.org/all/20220822204945.GA808626-robh@kernel.org/ DT schema files should not have 'Device Tree Binding' as part of there title: line. Remove this in most .yaml files, so hopefully preventing developers copying it into new .yaml files, and being asked to remove it. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20220825020427.3460650-1-andrew@lunn.ch Signed-off-by: Rob Herring <robh@kernel.org> |
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Wolfram Sang
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fa7fc5243f |
dt-bindings: timer: renesas,tmu: Add r8a779f0 support
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220726205858.1199-1-wsa+renesas@sang-engineering.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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Johnson Wang
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b830774c7e |
dt-bindings: timer: Add compatible for MediaTek MT8188
Add dt-binding documentation of timer for MediaTek MT8188 SoC platform. Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220818124602.20394-1-johnson.wang@mediatek.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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Linus Torvalds
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dd65b96492 |
ARM: new SoC support for 6.0
This adds initial support for two SoC families that have been under review for a while. In both cases, the origonal idea was to have a minimally functional version, but we ended up leaving out the clk drivers that are still under review and will be merged through the corresponding subsystem tree. The Nuvoton NPCM8xx is a 64-bit Baseboard Management Controller and based on the 32-bit NPCM7xx family but is now getting added to arch/arm64 as well. Sunplus SP7021, also known as Plus1, is a general-purpose System-in-Package design based on the 32-bit Cortex-A7 SoC on the main chip, plus an I/O chip and memory in the same -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLo+24ACgkQmmx57+YA GNkPVw//XAC/uK7WR4oz1D1YaPPNhEvFa6hV1gjGB7Iif72SzyDJmC+36MATU/AY neQjCOLJMhxI0hpDGY9nLYe+aP1C6vD32zsjffjt/+s9em+YZZCUkRJuQ5xO3fID Uk8ZAnCIcOqX9sjXr9ChW8irlcWFbKzhgWXnPqwQmycIaE7QVz1wx32dbc64YuAK S+290U8wbj8bukr33TyZPMdYlfqNU3c1W+dCaeVsQlX1juoHEV3stmIjslRefd6X Jre22YJE41VlPufZej76nHXuVnjKf54Oi347TcbPOWNDtEAIESt3mzKy+zICBT2p v01rNBf0SogyOtSbWDPTFCAH9W9hujSOJIUOWpbOLaPdfElXxcoTBwj2e2LMoW0k ke7YR1m6FKDam5GFU9Oe98CWIiVm/GnTA5mnhhETU1QTXQ3KeZ+Z8X779YuSWPv9 kJuOPRSk9NdcfRtxZz1vpCvhv/2hBbeBuz+GZi3bisMWdvVqS3lFqVbr6kziQbJZ kE6KJH48FdL0VLVvuy+aNSF2umLT42b+5+cmQFuP2zePQgo1DEMKEtFXpZjQJbha 3iu3sHnieOFMLcbNzbqSz2im3yYNBjl1M5qoGEXaw3Rkzqiht0kMNvAa4LmAejbh E+5BIczwWNbaUKgToV1ij65O4a78Bw98m2SIS7awEZC5MW/nXYA= =7Id+ -----END PGP SIGNATURE----- Merge tag 'arm-newsoc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM new SoC support from Arnd Bergmann: "This adds initial support for two SoC families that have been under review for a while. In both cases, the origonal idea was to have a minimally functional version, but we ended up leaving out the clk drivers that are still under review and will be merged through the corresponding subsystem tree. The Nuvoton NPCM8xx is a 64-bit Baseboard Management Controller and based on the 32-bit NPCM7xx family but is now getting added to arch/arm64 as well. Sunplus SP7021, also known as Plus1, is a general-purpose System-in-Package design based on the 32-bit Cortex-A7 SoC on the main chip, plus an I/O chip and memory in the same" * tag 'arm-newsoc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits) MAINTAINERS: rectify entry for ARM/NUVOTON NPCM ARCHITECTURE arm64: defconfig: Add Nuvoton NPCM family support arm64: dts: nuvoton: Add initial NPCM845 EVB device tree arm64: dts: nuvoton: Add initial NPCM8XX device tree arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string dt-bindings: arm: npcm: Add maintainer reset: npcm: Add NPCM8XX support dt-bindings: reset: npcm: Add support for NPCM8XX reset: npcm: using syscon instead of device data ARM: dts: nuvoton: add reset syscon property dt-bindings: reset: npcm: add GCR syscon property dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock dt-bindings: watchdog: npcm: Add npcm845 compatible string dt-bindings: timer: npcm: Add npcm845 compatible string ARM: dts: Add Sunplus SP7021-Demo-V3 board device tree ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig ARM: sunplus: Add initial support for Sunplus SP7021 SoC irqchip: Add Sunplus SP7021 interrupt controller driver ... |
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Linus Torvalds
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3976d758e0 |
ARM: DT changes for 6.0
As usual, the bulk of the changes for the SoC tree are devicetree file
updates, and most of these changes are for 64-bit embedded machines.
As before, there are a ton of style cleanups, and additional hardware
support for existing machines.
Looking only at the new SoC, the notable additions are:
- A whole family of Broadcom broadband SoCs, both 32-bit and 64-bit:
BCM63178, BCM63158, BCM4912, BCM6858, BCM6878, BCM6846, BCM63146,
BCM6856, BCM6855, BCM6756, BCM63148, and BCM6813.
Each SoC comes with a corresponding reference board.
- The new NXP i.MX93 SoC, the follow-up to the popular i.MX6 and
i.MX8 embedded SoCs, now using Cortex-A55 cores and the
Ethos-U65 NPU.
- Qualcomm Snapdragon 8cx Gen3 (SC8280XP), the current high end
of Arm based Laptop SoCs, and its automotive cousin, the
SA8540P. The SC8280XP is used in the Lenovo Thinkpad X13s
laptop that also gets added here in addition to the reference
boards.
- Allwinner H616, a newer version of the H6 SoC, targeted at
Set-top-box applications. It comes with dts files for the
Orange Pi zero2 single-board computer and the X96 Mate
set-top-box
- Marvell Prestera 98DX2530 (AlleyCat5), a network switch chip
in the Armada SoC family based on the Cortex-A55 core.
New machines based on previously supported SoCs include:
- Several new machines on NXP i.MX platforms: multiple Toradex
Colibri boards using the "Iris" and "Ixora" carriers,
DH electronics i.MX8M Plus DHCOM and PDK2, TQ-Systems
TQMa8MPQL, and phytech phyBOARD-Polis-i.MX8MM.
- Google Chameleon v3 FPGA board based on Intel Arria10 and
Stratix 10 Software Virtual platform, both in the SoCFPGA
platform.
- Two new wireless devices based on Broadcom SoCs:
The Asus GT-AX6000 Router and the Cisco Meraki MR26 access point
- Improved Chromebook support for both the Mediatek and Qualcomm
SoC families brought added machines: Acer Chromebook 514 (MT8192),
Acer Chromebook Spin 513 (MT8195) and a couple of SC7180 based
machines including the Lenovo IdeaPad Chromebook Duet 3.
- Xiaomi Mi Mix2s, LG G7 and LG V35 are mobile phones based on
Qualcomm SDM845, while Mi 5s Plus is based on MSM8996.
- Finally, there are a few development board on other chips:
PCB8309 (Microchip lan966x), Radxa Rock Pi S (Rockchips RK3308)
DH DRC Compact (ST STM32MP1) and Inforce IFC6560 (Qualcomm
SDM660)
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Merge tag 'arm-dt-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM DT updates from Arnd Bergmann:
"As usual, the bulk of the changes for the SoC tree are devicetree file
updates, and most of these changes are for 64-bit embedded machines.
As before, there are a ton of style cleanups, and additional hardware
support for existing machines.
Looking only at the new SoC, the notable additions are:
- A whole family of Broadcom broadband SoCs, both 32-bit and 64-bit:
BCM63178, BCM63158, BCM4912, BCM6858, BCM6878, BCM6846, BCM63146,
BCM6856, BCM6855, BCM6756, BCM63148, and BCM6813. Each SoC comes
with a corresponding reference board.
- The new NXP i.MX93 SoC, the follow-up to the popular i.MX6 and
i.MX8 embedded SoCs, now using Cortex-A55 cores and the Ethos-U65
NPU.
- Qualcomm Snapdragon 8cx Gen3 (SC8280XP), the current high end of
Arm based Laptop SoCs, and its automotive cousin, the SA8540P. The
SC8280XP is used in the Lenovo Thinkpad X13s laptop that also gets
added here in addition to the reference boards.
- Allwinner H616, a newer version of the H6 SoC, targeted at
Set-top-box applications. It comes with dts files for the Orange Pi
zero2 single-board computer and the X96 Mate set-top-box
- Marvell Prestera 98DX2530 (AlleyCat5), a network switch chip in the
Armada SoC family based on the Cortex-A55 core.
New machines based on previously supported SoCs include:
- Several new machines on NXP i.MX platforms: multiple Toradex
Colibri boards using the "Iris" and "Ixora" carriers, DH
electronics i.MX8M Plus DHCOM and PDK2, TQ-Systems TQMa8MPQL, and
phytech phyBOARD-Polis-i.MX8MM.
- Google Chameleon v3 FPGA board based on Intel Arria10 and Stratix
10 Software Virtual platform, both in the SoCFPGA platform.
- Two new wireless devices based on Broadcom SoCs: The Asus GT-AX6000
Router and the Cisco Meraki MR26 access point
- Improved Chromebook support for both the Mediatek and Qualcomm SoC
families brought added machines: Acer Chromebook 514 (MT8192), Acer
Chromebook Spin 513 (MT8195) and a couple of SC7180 based machines
including the Lenovo IdeaPad Chromebook Duet 3.
- Xiaomi Mi Mix2s, LG G7 and LG V35 are mobile phones based on
Qualcomm SDM845, while Mi 5s Plus is based on MSM8996.
- Finally, there are a few development board on other chips: PCB8309
(Microchip lan966x), Radxa Rock Pi S (Rockchips RK3308) DH DRC
Compact (ST STM32MP1) and Inforce IFC6560 (Qualcomm SDM660)"
* tag 'arm-dt-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (829 commits)
dt-bindings: soc: bcm: use absolute path to other schema
dt-bindings: soc: bcm: drop quotes when not needed
dt-bindings: soc: microchip: use absolute path to other schema
dt-bindings: soc: microchip: drop quotes when not needed
ARM: dts: lan966x: keep lan966 entries alphabetically sorted
ARM: dts: lan966x: add support for pcb8309
dt-bindings: arm: at91: add lan966 pcb8309 board
ARM: dts: lan966x: Enable network driver on pcb8291
ARM: dts: lan966x: Disable can0 on pcb8291
ARM: dts: lan966x: Add gpio-restart
dt-bindings: arm: aspeed: add Aspeed Evaluation boards
arm64: dts: qcom: Add support for Xiaomi Mi Mix2s
dt-bindings: arm: qcom: Add Xiaomi Mi Mix2s bindings
dt-bindings: arm: qcom: Document lg,judyln and lg,judyp devices
dt-bindings: arm: qcom: add missing SM6350 board compatibles
dt-bindings: arm: qcom: add missing SM6125 board compatibles
dt-bindings: arm: qcom: add missing SDM845 board compatibles
dt-bindings: arm: qcom: add missing SDM636 board compatibles
dt-bindings: arm: qcom: add missing SDM630 board compatibles
dt-bindings: arm: qcom: add missing QCS404 board compatibles
...
|
||
|
Thomas Gleixner
|
75fed76ebc |
- Add the missing DT bindings for the MTU nomadik timer (Linus
Walleij) - Fix grammar typo in the ARM global timer Kconfig option (Randy Dunlap) - Add the tegra186 timer and use it on the tegra234 board (Thierry Reding) - Add the 'CPUXGPT' CPU timer for Mediatek MT6795 and implement a workaround to overcome an ATF bug where the timer is not correctly initialized (AngeloGioacchino Del Regno) - Rework the suspend/resume approach to enable the feature on the timer even it is not an active clock and fix a compilation warning (Claudiu Beznea) - Add the Add R-Car Gen4 timer support along with the DT bindings (Wolfram Sang) - Add compatible for ti,am654-timer to support AM6 SoC (Tony Lindgren) - Fix Kconfig option to put it back to 'bool' instead of 'tristate' for the tegra186 (Daniel Lezcano) - Sort 'family,type' DT bindings for the Renesas timers (Geert Uytterhoeven) - Add compatible 'allwinner,sun20i-d1-timer' for Allwinner D1 (Samuel Holland) - Remove unnecessary (void*) conversions for sun4i (XU pengfei) - Remove unnecessary (void*) conversions for sun5i (Li zeming) -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEGn3N4YVz0WNVyHskqDIjiipP6E8FAmLhWF0ACgkQqDIjiipP 6E+ziAgArY8BJ/09w4rt63LDO5nynorr0+Uuf0E9hCmc0KzRsSF3hO39EcuLj1zD ubKKSXwaOucAcRYj7gCeqaSk/IOs9EmwESRVtLLIwEwYsg44iC1vmq4pJ8cX66qN h5TqkOiq77fPIY3BR/nSFxddmlU2farO8oSUqdLNsVrqoIq2rttaQYADdYGa4LYn dvQHEmh6jvJRoZM3aR6It0EWM7pyHKxAWFChWv+SbikheDCgIcugz+FUTy9lyhmf 39wLm2srmrCLbjaGdJnyc38/y/UPIJ0aqeSf7XSiHTWQ+dfNBfdbrmPTSJHiyIt+ iPrlx0ShvrMXeOxgbSxse53e+9Q88w== =ApcN -----END PGP SIGNATURE----- Merge tag 'timers-v5.20-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clockevent/source updates from Daniel Lezcano: - Add the missing DT bindings for the MTU nomadik timer (Linus Walleij) - Fix grammar typo in the ARM global timer Kconfig option (Randy Dunlap) - Add the tegra186 timer and use it on the tegra234 board (Thierry Reding) - Add the 'CPUXGPT' CPU timer for Mediatek MT6795 and implement a workaround to overcome an ATF bug where the timer is not correctly initialized (AngeloGioacchino Del Regno) - Rework the suspend/resume approach to enable the feature on the timer even it is not an active clock and fix a compilation warning (Claudiu Beznea) - Add the Add R-Car Gen4 timer support along with the DT bindings (Wolfram Sang) - Add compatible for ti,am654-timer to support AM6 SoC (Tony Lindgren) - Fix Kconfig option to put it back to 'bool' instead of 'tristate' for the tegra186 (Daniel Lezcano) - Sort 'family,type' DT bindings for the Renesas timers (Geert Uytterhoeven) - Add compatible 'allwinner,sun20i-d1-timer' for Allwinner D1 (Samuel Holland) - Remove unnecessary (void*) conversions for sun4i (XU pengfei) - Remove unnecessary (void*) conversions for sun5i (Li zeming) Link: https://lore.kernel.org/all/7472984e-f502-5f27-82bf-070127dd85a5@linaro.org |
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Samuel Holland
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c329fb5318 |
dt-bindings: timer: allwinner,sun4i-a10-timer: Add D1 compatible
Allwinner D1 contains the usual sun4i MMIO timer device. It contains two timers like other recent SoCs, so it is compatible with the A23 variant. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220725051715.56427-1-samuel@sholland.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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Krzysztof Kozlowski
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561a084618 |
dt-bindings: timer: ingenic,tcu: use absolute path to other schema
Absolute path to other DT schema is preferred over relative one. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220726115937.101432-1-krzysztof.kozlowski@linaro.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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Geert Uytterhoeven
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4abb38595b |
dt-bindings: timer: renesas,cmt: Fix R-Car Gen4 fall-out
Restore sort order (by family, followed by type).
Update the conditional sections specifying the number of interrupts.
Fixes:
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Tomer Maimon
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6762d688a1 |
dt-bindings: timer: npcm: Add npcm845 compatible string
Add a compatible string for Nuvoton BMC NPCM845 timer. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Wolfram Sang
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bd0ed737d5 |
dt-bindings: timer: renesas,cmt: R-Car V3U is R-Car Gen4
Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence move its compatible value to the R-Car Gen4 section. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220713100603.3391-3-wsa+renesas@sang-engineering.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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Wolfram Sang
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525b296185 |
dt-bindings: timer: renesas,cmt: Add r8a779f0 and generic Gen4 CMT support
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220713100603.3391-2-wsa+renesas@sang-engineering.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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AngeloGioacchino Del Regno
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13b917a585 |
dt-bindings: timer: mediatek: Add CPUX System Timer and MT6795 compatible
Document the "CPUXGPT" CPU General Purpose Timer, used as ARM/ARM64 System Timer on MediaTek platforms and add the MT6795 compatible for it. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20220613133819.35318-2-angelogioacchino.delregno@collabora.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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Kartik
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dd92b16cbc |
dt-bindings: timer: Add Tegra186 & Tegra234 Timer
The Tegra186 timer provides ten 29-bit timer counters and one 32-bit timestamp counter. The Tegra234 timer provides sixteen 29-bit timer counters and one 32-bit timestamp counter. Each NV timer selects its timing reference signal from the 1 MHz reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be programmed to generate one-shot, periodic, or watchdog interrupts. Signed-off-by: Kartik <kkartik@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
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Linus Walleij
|
d6513a3492 |
dt-bindings: timer: Add Nomadik MTU binding
The Nomadik MTU timer has been used in devicetrees forever but somehow we missed to add a binding for it. Fix it by simply adding it. Cc: Lee Jones <lee.jones@linaro.org> Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220526213621.373727-1-linus.walleij@linaro.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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Linus Torvalds
|
c049ecc523 |
Clockevent/clocksource updates:
- Device tree bindings for MT8186
- Tell the kernel that the RISC-V SBI timer stops in deeper power states
- Make device tree parsing in sp804 more robust
- Dead code removal and tiny fixes here and there
- Add the missing SPDX identifiers
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Merge tag 'timers-core-2022-06-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull clockevent/clocksource updates from Thomas Gleixner:
- Device tree bindings for MT8186
- Tell the kernel that the RISC-V SBI timer stops in deeper power
states
- Make device tree parsing in sp804 more robust
- Dead code removal and tiny fixes here and there
- Add the missing SPDX identifiers
* tag 'timers-core-2022-06-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
clocksource/drivers/oxnas-rps: Fix irq_of_parse_and_map() return value
clocksource/drivers/timer-ti-dm: Remove unnecessary NULL check
clocksource/drivers/timer-sun5i: Convert to SPDX identifier
clocksource/drivers/timer-sun4i: Convert to SPDX identifier
clocksource/drivers/pistachio: Convert to SPDX identifier
clocksource/drivers/orion: Convert to SPDX identifier
clocksource/drivers/lpc32xx: Convert to SPDX identifier
clocksource/drivers/digicolor: Convert to SPDX identifier
clocksource/drivers/armada-370-xp: Convert to SPDX identifier
clocksource/drivers/mips-gic-timer: Convert to SPDX identifier
clocksource/drivers/jcore: Convert to SPDX identifier
clocksource/drivers/bcm_kona: Convert to SPDX identifier
clocksource/drivers/sp804: Avoid error on multiple instances
clocksource/drivers/riscv: Events are stopped during CPU suspend
clocksource/drivers/ixp4xx: Drop boardfile probe path
dt-bindings: timer: Add compatible for Mediatek MT8186
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||
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Linus Torvalds
|
09a018176b |
ARM: SoC changes, part 2
This is the second part of the general SoC updates, containing
everything that did not make it in the initial pull request,
or that came in as a bugfix later.
- Devicetree updates for SoCFPGA, ASPEED, AT91 and Rockchip, including
a new machine using an ASPEED BMC.
- More DT fixes from Krzysztof Kozlowski across platforms
- A new SoC platform for the GXP baseboard management controller,
used in current server products from HPE.
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Merge tag 'arm-late-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more ARM SoC updates from Arnd Bergmann:
"This is the second part of the general SoC updates, containing
everything that did not make it in the initial pull request, or that
came in as a bugfix later.
- Devicetree updates for SoCFPGA, ASPEED, AT91 and Rockchip,
including a new machine using an ASPEED BMC.
- More DT fixes from Krzysztof Kozlowski across platforms
- A new SoC platform for the GXP baseboard management controller,
used in current server products from HPE"
* tag 'arm-late-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (56 commits)
ARM: configs: Enable more audio support for i.MX
tee: optee: Pass a pointer to virt_addr_valid()
arm64: dts: rockchip: rename Quartz64-A bluetooth gpios
arm64: dts: rockchip: add clocks property to cru node rk3368
arm64: dts: rockchip: add clocks property to cru node rk3308
arm64: dts: rockchip: add clocks to rk356x cru
ARM: dts: rockchip: add clocks property to cru node rk3228
ARM: dts: rockchip: add clocks property to cru node rk3036
ARM: dts: rockchip: add clocks property to cru node rk3066a/rk3188
ARM: dts: rockchip: add clocks property to cru node rk3288
ARM: dts: rockchip: Remove "amba" bus nodes from rv1108
ARM: dts: rockchip: add clocks property to cru node rv1108
arm64: dts: sprd: use new 'dma-channels' property
ARM: dts: da850: use new 'dma-channels' property
ARM: dts: pxa: use new 'dma-channels/requests' properties
soc: ixp4xx/qmgr: Fix unused match warning
ARM: ep93xx: Make ts72xx_register_flash() static
ARM: configs: enable support for Kontron KSwitch D10
ep93xx: clock: Do not return the address of the freed memory
arm64: dts: intel: add device tree for n6000
...
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||
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Linus Torvalds
|
8eca6b0a64 |
pwm: Changes for v5.19-rc1
Quite a large number of conversions this time around, courtesy of Uwe who has been working tirelessly on these. No drivers of the legacy API are left at this point, so as a next step the old API can be removed. Support is added for a few new devices such as the Xilinx AXI timer- based PWMs and the PWM IP found on Sunplus SoCs. Other than that, there's a number of fixes, cleanups and optimizations. -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmKXeUoZHHRoaWVycnku cmVkaW5nQGdtYWlsLmNvbQAKCRDdI6zXfz6zoQ44D/9ZtpQ30tKUQS4o55iiQZBy 7cfeHK++6oCrcIp57j5TEJaMh+DRz23ga+5/Sp2YeqCCswifrM/Lxm/ys34045oa YVHF1Yz9NbyE7d5W+Jzoo3cFBcne6lFgwcN8qVfpc2O35PwmzWSbU3iBlIq0qxbC etWbDxBzFbsNsvH6TSNP7xYxfRVct+KYBIl4ySswqryHry2Bl9mTV2P9wS3CkZne 4y6RWyYeaNBmqLxCOiw98pXr70uJKRAy1qoEUvFBZGzYsb9kwOG9J7RQJxgtwVFK YJ+l/c/cq1U3LtQQImcPhx8y+jdRpFK3RlcA6cRBHP3PWuTUsKPKYf2DFEee3bYv NhNxkuJhuXhvqpB3Bb5xrnOE34tjF4tLPz74UxaU/DlLqeveyvaqsVuGK7IVbxcU YVsceNJHdTJdkKaomB/OkmNrKEf8XNmCmF+x2FPAMKBnJ+E43jKuPk7TTUJrJLn0 O57VjKmiA3ZsztgWudSOiOvTxmsfRnlHTcPvMO8MbYO9tXVFOBGuzV3RgxKvwpDT EWp5VAQp8JMoLvG3fdB4wbZ8isVooYdYYw/jiUG5MA3MGxW+4zmRR/+BglsKpMU7 AujYBUeInXg1bwezBUW4EieslFVQ/8ctsXj84bbIg3gA5SRSgp/ccH/2ollnAsPU Dw6E+STJiQM95NqfUUb8IQ== =CwnJ -----END PGP SIGNATURE----- Merge tag 'pwm/for-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "Quite a large number of conversions this time around, courtesy of Uwe who has been working tirelessly on these. No drivers of the legacy API are left at this point, so as a next step the old API can be removed. Support is added for a few new devices such as the Xilinx AXI timer- based PWMs and the PWM IP found on Sunplus SoCs. Other than that, there's a number of fixes, cleanups and optimizations" * tag 'pwm/for-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (43 commits) pwm: pwm-cros-ec: Add channel type support dt-bindings: google,cros-ec-pwm: Add the new -type compatible dt-bindings: Add mfd/cros_ec definitions pwm: Document that the pinstate of a disabled PWM isn't reliable pwm: twl-led: Implement .apply() callback pwm: lpc18xx: Implement .apply() callback pwm: mediatek: Implement .apply() callback pwm: lpc32xx: Implement .apply() callback pwm: tegra: Implement .apply() callback pwm: stmpe: Implement .apply() callback pwm: sti: Implement .apply() callback pwm: pwm-mediatek: Add support for MediaTek Helio X10 MT6795 dt-bindings: pwm: pwm-mediatek: Add documentation for MT6795 SoC pwm: tegra: Optimize period calculation pwm: renesas-tpu: Improve precision of period and duty_cycle calculation pwm: renesas-tpu: Improve maths to compute register settings pwm: renesas-tpu: Rename variables to match the usual naming pwm: renesas-tpu: Implement .apply() callback pwm: renesas-tpu: Make use of devm functions pwm: renesas-tpu: Make use of dev_err_probe() ... |
||
|
Arnd Bergmann
|
3e11194631
|
Merge branch 'hpe/gxp-soc' into arm/late
Patch series from Nick Hawkins: "The GXP is the HPE BMC SoC that is used in the majority of HPE current generation servers. Traditionally the asic will last multiple generations of server before being replaced. Info about SoC: HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC features at HPE. It supports ARMv7 architecture based on the Cortex A9 core. It is capable of using an AXI bus to which a memory controller is attached. It has multiple SPI interfaces to connect boot flash and BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple i2c engines to drive connectivity with a host infrastructure. The initial patches enable the watchdog and timer enabling the host to be able to boot." * hpe/gxp-soc: MAINTAINERS: Introduce HPE GXP Architecture ARM: dts: Introduce HPE GXP Device tree dt-bindings: arm: hpe: add GXP Support dt-bindings: timer: hpe,gxp-timer: Add HPE GXP Timer and Watchdog clocksource/drivers/timer-gxp: Add HPE GXP Timer watchdog: hpe-wdt: Introduce HPE GXP Watchdog ARM: configs: multi_v7_defconfig: Add HPE GXP ARCH ARM: hpe: Introduce the HPE GXP architecture Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Linus Torvalds
|
16477cdfef |
asm-generic changes for 5.19
The asm-generic tree contains three separate changes for linux-5.19:
- The h8300 architecture is retired after it has been effectively
unmaintained for a number of years. This is the last architecture we
supported that has no MMU implementation, but there are still a few
architectures (arm, m68k, riscv, sh and xtensa) that support CPUs with
and without an MMU.
- A series to add a generic ticket spinlock that can be shared by most
architectures with a working cmpxchg or ll/sc type atomic, including
the conversion of riscv, csky and openrisc. This series is also a
prerequisite for the loongarch64 architecture port that will come as
a separate pull request.
- A cleanup of some exported uapi header files to ensure they can be
included from user space without relying on other kernel headers.
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Merge tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic
Pull asm-generic updates from Arnd Bergmann:
"The asm-generic tree contains three separate changes for linux-5.19:
- The h8300 architecture is retired after it has been effectively
unmaintained for a number of years. This is the last architecture
we supported that has no MMU implementation, but there are still a
few architectures (arm, m68k, riscv, sh and xtensa) that support
CPUs with and without an MMU.
- A series to add a generic ticket spinlock that can be shared by
most architectures with a working cmpxchg or ll/sc type atomic,
including the conversion of riscv, csky and openrisc. This series
is also a prerequisite for the loongarch64 architecture port that
will come as a separate pull request.
- A cleanup of some exported uapi header files to ensure they can be
included from user space without relying on other kernel headers"
* tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic:
h8300: remove stale bindings and symlink
sparc: add asm/stat.h to UAPI compile-test coverage
powerpc: add asm/stat.h to UAPI compile-test coverage
mips: add asm/stat.h to UAPI compile-test coverage
riscv: add linux/bpf_perf_event.h to UAPI compile-test coverage
kbuild: prevent exported headers from including <stdlib.h>, <stdbool.h>
agpgart.h: do not include <stdlib.h> from exported header
csky: Move to generic ticket-spinlock
RISC-V: Move to queued RW locks
RISC-V: Move to generic spinlocks
openrisc: Move to ticket-spinlock
asm-generic: qrwlock: Document the spinlock fairness requirements
asm-generic: qspinlock: Indicate the use of mixed-size atomics
asm-generic: ticket-lock: New generic ticket-based spinlock
remove the h8300 architecture
|
||
|
Linus Torvalds
|
cc3c470ae4 |
ARM: driver changes for 5.19
There are minor updates to SoC specific drivers for chips by Rockchip,
Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom. Noteworthy
driver changes include:
- Several conversions of DT bindings to yaml format.
- Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.
- Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
and support for more chips in the RPMh power domains and the soc-id.
- NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.
- Apple M1 gains support for the on-chip NVMe controller, making it
possible to finally use the internal disks. This also includes SoC
drivers for their RTKit IPC and for the SART DMA address filter.
For other subsystems that merge their drivers through the SoC tree,
we have
- Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
now has a cache for firmware argument structures as an optimization,
and SCMI now supports the 3.1 version of the specification.
- Reset controller updates to Amlogic, ASpeed, Renesas and ACPI drivers
- Memory controller updates for Tegra, and a few updates for other
platforms.
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Merge tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM driver updates from Arnd Bergmann:
"There are minor updates to SoC specific drivers for chips by Rockchip,
Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom.
Noteworthy driver changes include:
- Several conversions of DT bindings to yaml format.
- Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.
- Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
and support for more chips in the RPMh power domains and the
soc-id.
- NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.
- Apple M1 gains support for the on-chip NVMe controller, making it
possible to finally use the internal disks. This also includes SoC
drivers for their RTKit IPC and for the SART DMA address filter.
For other subsystems that merge their drivers through the SoC tree, we
have
- Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
now has a cache for firmware argument structures as an
optimization, and SCMI now supports the 3.1 version of the
specification.
- Reset controller updates to Amlogic, ASpeed, Renesas and ACPI
drivers
- Memory controller updates for Tegra, and a few updates for other
platforms"
* tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits)
memory: tegra: Add MC error logging on Tegra186 onward
memory: tegra: Add memory controller channels support
memory: tegra: Add APE memory clients for Tegra234
memory: tegra: Add Tegra234 support
nvme-apple: fix sparse endianess warnings
soc/tegra: pmc: Document core domain fields
soc: qcom: pdr: use static for servreg_* variables
soc: imx: fix semicolon.cocci warnings
soc: renesas: R-Car V3U is R-Car Gen4
soc: imx: add i.MX8MP HDMI blk-ctrl
soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
soc: imx: add i.MX8MP HSIO blk-ctrl
soc: imx: imx8m-blk-ctrl: set power device name
soc: qcom: llcc: Add sc8180x and sc8280xp configurations
dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles
soc/tegra: pmc: Select REGMAP
dt-bindings: reset: st,sti-powerdown: Convert to yaml
dt-bindings: reset: st,sti-picophyreset: Convert to yaml
dt-bindings: reset: socfpga: Convert to yaml
dt-bindings: reset: snps,axs10x-reset: Convert to yaml
...
|
||
|
Arnd Bergmann
|
b2441b3bdc |
h8300: remove stale bindings and symlink
These four files are left over from the h8300 removal. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
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Krzysztof Kozlowski
|
ee77ef0d09 |
dt-bindings: timer: samsung,exynos4210-mct: define strict clock order
The DTS should always have fixed clock order, even if it comes with clock-names property. Drop the pattern to make the order strict. Existing DTS already match this. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220424150333.75172-3-krzysztof.kozlowski@linaro.org |
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Krzysztof Kozlowski
|
60854ba8e3 |
dt-bindings: timer: samsung,exynos4210-mct: drop unneeded minItems
There is no need to add minItems when it is equal to maxItems. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220424150333.75172-2-krzysztof.kozlowski@linaro.org |
||
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Krzysztof Kozlowski
|
1084ab9e3b |
dt-bindings: timer: cdns,ttc: drop unneeded minItems
There is no need to add minItems when it is equal to maxItems. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220424150333.75172-1-krzysztof.kozlowski@linaro.org |
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Nick Hawkins
|
ea526e21a8 |
dt-bindings: timer: hpe,gxp-timer: Add HPE GXP Timer and Watchdog
Add support for the HPE GXP Timer and Watchdog. There are multiple timers on the SoC but only one is enabled at this time. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> |
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|
Allen-KH Cheng
|
b8b1ab133e |
dt-bindings: timer: Add compatible for Mediatek MT8186
This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC Platform. Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220311130732.22706-2-allen-kh.cheng@mediatek.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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Stanislav Jakubek
|
fa2024c315 |
dt-bindings: timer: Convert rda,8810pl-timer to YAML
Convert RDA Micro Timer bindings to DT schema format. Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220504175502.GA2573@standask-GA-A55M-S2HP |
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Tony Lindgren
|
c4f3f823c2 |
dt-bindings: timer: Add compatible for am6 for TI timer-dm
Let's add compatible for ti,am654-timer for TI am64, am65 and j72 SoCs. As the timer hardware is the same between am64, am65 and j72 we use the compatible name for the earliest SoC with this timer. The timer interrupts are not routable for the operating system for some timers on am6. Let's make sure the interrupts are configured for the timers on all other SoCs. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220414085807.7389-3-tony@atomide.com |
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Tony Lindgren
|
82b9a6bb4b |
dt-bindings: timer: Update TI timer to yaml
Let's update the TI timer binding to use yaml. As this binding is specific to the TI dual-mode timers also known as dm-timers, let's use file name ti,timer-dm.yaml to avoid confusion with other timers. We add checks for the deprecated ti,hwmods property as done for other TI device driver bindings earlier. We also correct the issue with the old binding that was out of date for several properties. The am43 related timers are undocumented, but compatible with the am3 timers. Let's add the am43 timers too. The dm814 and dm816 timers are missing, let's add them. Some timers on some SoCs are dual mapped, like the ABE timers on omap4 and 5. The reg property maxItems must be updated to 2. The timer clocks can be managed by the parent interconnect target module with no clocks assigned for the timer node. And in some cases, the SoC may need to configure additional system clock for the timer in addition to the functional clock. The clock names are optional and not specific to the comptible property. For example, dra7 timers on l3 interconnect do not need clock-names, while the timers on dra7 l4 interconnect need them with both being compatible with ti,omap5430-timer. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220414085807.7389-2-tony@atomide.com |
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Biju Das
|
f14eb061fe |
dt-bindings: timer: renesas: ostm: Document Renesas RZ/G2UL OSTM
Document the General Timer Module(a.k.a OSTM) found on the RZ/G2UL SoC. OSTM module is identical to one found RZ/G2L SoC. No driver changes are required as generic compatible string "renesas,ostm" will be used as a fallback. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220425141828.197321-1-biju.das.jz@bp.renesas.com |
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Krzysztof Kozlowski
|
5fe580196d |
dt-bindings: timer: exynos4210-mct: describe known hardware and its interrupts
Most of the Samsung Exynos SoCs use almost the same Multi-Core Timer block, so only two compatibles were used so far (for Exynos4210 and Exynos4412 flavors) with Exynos4210-one being used in most of the SoCs. However the Exynos4210 flavor actually differs by number of interrupts. Add new compatibles, maintaining backward compatibility with Exynos4210, and constraints for number of interrupts. This allows to exactly match the Exynos MCT hardware. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220407194127.19004-1-krzysztof.kozlowski@linaro.org |
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Sean Anderson
|
f643490e1b |
dt-bindings: pwm: Add Xilinx AXI Timer
This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a "soft" block, so it has some parameters which would not be configurable in most hardware. This binding is usually automatically generated by Xilinx's tools, so the names and values of some properties should be kept as they are, if possible. In addition, this binding is already in the kernel at arch/microblaze/boot/dts/system.dts, and in user software such as QEMU. The existing driver uses the clock-frequency property, or alternatively the /cpus/timebase-frequency property as its frequency input. Because these properties are deprecated, they have not been included with this schema. All new bindings should use the clocks/clock-names properties to specify the parent clock. Because we need to init timer devices so early in boot, we determine if we should use the PWM driver or the clocksource/clockevent driver by the presence/absence, respectively, of #pwm-cells. Because both counters are used by the PWM, there is no need for a separate property specifying which counters are to be used for the PWM. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com> |
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Linus Torvalds
|
74164d284b |
pwm: Changes for v5.18-rc1
Contains conversions of some more drivers to the atomic API as well as the addition of new chip support for some existing drivers. There are also various minor fixes and cleanups across the board, from drivers to device tree bindings. -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmJESlMZHHRoaWVycnku cmVkaW5nQGdtYWlsLmNvbQAKCRDdI6zXfz6zoWlXD/4o913wJIR1GPTQBD9ps3bd CrWlbg4v7OL1tsikMweJBj63+cq8ucBhXe6PBbiM3NEo/ztwo1Km5nTs0Fv+a+9L q3CzJn/RxgGeq/bA8ejG1LswOooNQXUKx3klEEYQyy1TGhea4/TucTRAjF3890Sj SyiyDtAs+n2OyFflnAdz43PeYLpX6n4jibXURD2UTHda8bi4U/1SCLFt4w50lVnI FHtY/aP7PhvmZ5AJRAAbhYwo/YkTbavX01GPXiVkKQaUyHz+iA5VWdvIgwfo/uKP UM9YiPgZxa2J+qOYfGf+B++90Bzen54cNFTaAWrXkIQqq1oQvu8IKl3bkWBlLYGI lT56RtpB4sO63CJKj979GOfTtP/8Byann+KLMPL+N9LaFLUrmvsbSJ+tuz6ZcI1v s8qPZZg/qsnjPBVAmDQPezxmWjPwGVRUrUAgHoKc5ymrA/k2Gs9eD5gc8qo6QG2R 5t1cmb3DEhHPYiZGVHUMOwWOemBU4eX1a7BLPjZpgXGmK4whxFizloG45RfxCN1l mspETpOhxSm+zocdEcjAkbf+WWWIY26HLnz7iUlirMUvWVblYqlMP1S8q/wQIEX4 mp+iKBCFocN4YGd2/xac65twldkXaEewltsAdHNiUiMi6gmh3tMQZOt6m0eyZH2G sy0T7mlx/4FmQsurkIHHbQ== =a1Ta -----END PGP SIGNATURE----- Merge tag 'pwm/for-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "This contains conversions of some more drivers to the atomic API as well as the addition of new chip support for some existing drivers. There are also various minor fixes and cleanups across the board, from drivers to device tree bindings" * tag 'pwm/for-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (45 commits) pwm: rcar: Simplify multiplication/shift logic dt-bindings: pwm: renesas,tpu: Do not require pwm-cells twice dt-bindings: pwm: tiehrpwm: Do not require pwm-cells twice dt-bindings: pwm: tiecap: Do not require pwm-cells twice dt-bindings: pwm: samsung: Do not require pwm-cells twice dt-bindings: pwm: intel,keembay: Do not require pwm-cells twice dt-bindings: pwm: brcm,bcm7038: Do not require pwm-cells twice dt-bindings: pwm: toshiba,visconti: Include generic PWM schema dt-bindings: pwm: renesas,pwm: Include generic PWM schema dt-bindings: pwm: sifive: Include generic PWM schema dt-bindings: pwm: rockchip: Include generic PWM schema dt-bindings: pwm: mxs: Include generic PWM schema dt-bindings: pwm: iqs620a: Include generic PWM schema dt-bindings: pwm: intel,lgm: Include generic PWM schema dt-bindings: pwm: imx: Include generic PWM schema dt-bindings: pwm: allwinner,sun4i-a10: Include generic PWM schema pwm: pwm-mediatek: Beautify error messages text pwm: pwm-mediatek: Allocate clk_pwms with devm_kmalloc_array pwm: pwm-mediatek: Simplify error handling with dev_err_probe() pwm: brcmstb: Remove useless locking ... |
||
|
Linus Torvalds
|
9bf3fc5007 |
Devicetree updates for v5.18:
- Add Krzysztof Kozlowski as co-maintainer for DT bindings providing much needed help. - DT schema validation now takes DTB files as input rather than intermediate YAML files. This decouples the validation from the source level syntax information. There's a bunch of schema fixes as a result of switching to DTB based validation which exposed some errors and incomplete schemas and examples. - Kbuild improvements to explicitly warn users running 'make dt_binding_check' on missing yamllint - Expand DT_SCHEMA_FILES kbuild variable to take just a partial filename or path instead of the full path to 1 file. - Convert various bindings to schema format: mscc,vsc7514-switch, multiple GNSS bindings, ahci-platform, i2c-at91, multiple UFS bindings, cortina,gemini-sata-bridge, cortina,gemini-ethernet, Atmel SHA, Atmel TDES, Atmel AES, armv7m-systick, Samsung Exynos display subsystem, nuvoton,npcm7xx-timer, samsung,s3c2410-i2c, zynqmp_dma, msm/mdp4, rda,8810pl-uart - New schemas for u-boot environment variable partition, TI clksel - New compatible strings for Renesas RZ/V2L SoC - Vendor prefixes for Xen, HPE, deprecated Synopsys, deprecated HiSilicon - Add/fix schemas for QEMU Arm 'virt' machine - Drop unused of_alias_get_alias_list() function - Add a script to check DT unittest EXPECT message output. Pass messages also now print by default at PR_INFO level to help test automation. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmI8s64QHHJvYmhAa2Vy bmVsLm9yZwAKCRD6+121jbxhwx3tD/4j56NE+aLkL636+I8tGFm3r+r6uLLT4SWh zDuiX3MP9OKfhJw43TjjURLwX5adBnG3nn505IXcAeiMRgEiciOpSa12w0mXyjMX QgVOcoaI3H2GBMEddJRo1PLTM/K5sYzZxAKLB827xoOk4mGNA0ZBAHvlB3W+yLE5 CE5yTaFoL4EMXuhWMtMrMlG1PQrbO3FpQ2DHBKrpxHPJmnHLk3c0YtMSTHGQnWbN AxT3S6RSsOLwLzZAXi2AlswqY82n5KtUf/RBrYi8rdr/xnIsCfMeXxafkP2Hyxkq L9RfKVn05c0LRtO1Eh8kYr+lmYmcWz/SIdJZXzpviIgE9MJapCAk0blBZ4S/FH0B EVGB1JkwCZFck6DBmkNJxAwR0iQOGWkJIkn6iBPNF0dHp58eE6adaXjhFH3uBEHk dXFaxPlvZ3P/Q2I/vmQ//m5tZMyjeCY2BlVYpkUJMOFfN26MIGHUmUlLnovLDqu4 lYgZG4V244uYzALLbURpbp+5dlPH/PL2gxvJJNqTS+/hXktQx1XnML4wD+xfJ4nT OY5DD7Z+KGBrdsMtxkFtIFvKD63E2gtAR5RZO0J/txlzhW7Wg6fJbhJZeRFhZKmN GAfud2s6rliyygByBL4ea50DSLLQpc/9HZtFmZ3NTILM6NbUR74sHt+1EZ1hee+M LaNsSscHuQ== =g1li -----END PGP SIGNATURE----- Merge tag 'devicetree-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: - Add Krzysztof Kozlowski as co-maintainer for DT bindings providing much needed help. - DT schema validation now takes DTB files as input rather than intermediate YAML files. This decouples the validation from the source level syntax information. There's a bunch of schema fixes as a result of switching to DTB based validation which exposed some errors and incomplete schemas and examples. - Kbuild improvements to explicitly warn users running 'make dt_binding_check' on missing yamllint - Expand DT_SCHEMA_FILES kbuild variable to take just a partial filename or path instead of the full path to 1 file. - Convert various bindings to schema format: mscc,vsc7514-switch, multiple GNSS bindings, ahci-platform, i2c-at91, multiple UFS bindings, cortina,gemini-sata-bridge, cortina,gemini-ethernet, Atmel SHA, Atmel TDES, Atmel AES, armv7m-systick, Samsung Exynos display subsystem, nuvoton,npcm7xx-timer, samsung,s3c2410-i2c, zynqmp_dma, msm/mdp4, rda,8810pl-uart - New schemas for u-boot environment variable partition, TI clksel - New compatible strings for Renesas RZ/V2L SoC - Vendor prefixes for Xen, HPE, deprecated Synopsys, deprecated HiSilicon - Add/fix schemas for QEMU Arm 'virt' machine - Drop unused of_alias_get_alias_list() function - Add a script to check DT unittest EXPECT message output. Pass messages also now print by default at PR_INFO level to help test automation. * tag 'devicetree-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (96 commits) dt-bindings: kbuild: Make DT_SCHEMA_LINT a recursive variable dt-bindings: nvmem: add U-Boot environment variables binding dt-bindings: ufs: qcom: Add SM6350 compatible string dt-bindings: dmaengine: sifive,fu540-c000: include generic schema dt-bindings: gpio: pca95xx: drop useless consumer example Revert "of: base: Introduce of_alias_get_alias_list() to check alias IDs" dt-bindings: virtio,mmio: Allow setting devices 'dma-coherent' dt-bindings: gnss: Add two more chips dt-bindings: gnss: Rewrite sirfstar binding in YAML dt-bindings: gnss: Modify u-blox to use common bindings dt-bindings: gnss: Rewrite common bindings in YAML dt-bindings: ata: ahci-platform: Add rk3568-dwc-ahci compatible dt-bindings: ata: ahci-platform: Add power-domains property dt-bindings: ata: ahci-platform: Convert DT bindings to yaml dt-bindings: kbuild: Use DTB files for validation dt-bindings: kbuild: Pass DT_SCHEMA_FILES to dt-validate dt-bindings: Add QEMU virt machine compatible dt-bindings: arm: Convert QEMU fw-cfg to DT schema dt-bindings: i2c: at91: Add SAMA7G5 compatible strings list dt-bindings: i2c: convert i2c-at91 to json-schema ... |
||
|
Linus Torvalds
|
ed4643521e |
ARM: DT updates for 5.18
After a somewhat quiet 5.17 release, the size of the DT changes
is a bit larger again. There are nine new SoC that get added,
all of them related to existing platforms:
- Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB
- Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G tablet
- Microchip Lan966 networking SoC and it evaluation board
- Qualcomm Snapdragon 625/632 midrange phone SoCs, with the
LG Nexus 5X and Fairphone FP3 phones
- Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs,
along with their evaluation boards
- Samsung Exynos 850 phone SoC and reference board
- Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone
- Tesla FSD (Fully Self-Driving), an automotive SoC losely derived
from the Samsung Exynos family.
- TI K3/AM62 SoC and reference board
Support for additional functionality in existing dts files is added all
over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91, Allwinner,
i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and Broadcom.
Samsung has a rework for its pinctrl schema that is a bit tricky and
requires driver changes to be included here.
A few more platforms only have smaller cleanups and DT Schema fixes,
this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno.
The new machines are really too many to list, but I'll do it anyway:
Allwinner:
- A20-Marsboard development board
Amlogic
- Amediatek X96-AIR (Amlogic S905X3)
- CYX A95XF3-AIR (Amlogic S905X3)
- Haochuangy H96-Max (Amlogic S905X3)
- Amlogic AQ222 (Amlogic S4)
- OSMC Vero 4K+ (Amlogic S905D)
Arm Juno
- Separate DT depending on SCMI firmware version
Aspeed:
- Quanta S6Q BMC (AST2600)
- ASRock ROMED8HM3 (AST2500)
Broadcom:
- Raspberry Pi Zero 2 W
Marvell MVEBU/Armada:
- Ctera C200 V1 NAS (kirkwood)
- Ctera C200 V2 NAS (armada-370)
Mstar
- DongShanPiOne, a low-end embedded board
- Miyoo Mini handheld game console
NXP i.MX:
- Numerous i.MX8M Mini based boards in even more variations, but
none based on other SoCs this time:
Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and
Gateworks GW7903
Qualcomm:
- Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3)
- SHIFT6mq phone (Snapdragon 845)
- Samsung Galaxy Book2 (Snapdragon 850)
- Snapdragon 8 Gen 1 Hardware Development Kit
TI OMAP:
- SanCloud BeagleBone Enhanced WiFi
Rockchip:
- Pine64 PineNote ereader tablet (rk356x)
- Bananapi-R2-Pro (rk356x)
STM32:
- emtrion emSBS-Argon embedded board (stm32mp157c)
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Merge tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Arnd Bergmann:
"After a somewhat quiet 5.17 release, the size of the DT changes is a
bit larger again. There are nine new SoC that get added, all of them
related to existing platforms:
- Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB
- Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G
tablet
- Microchip Lan966 networking SoC and it evaluation board
- Qualcomm Snapdragon 625/632 midrange phone SoCs, with the LG Nexus
5X and Fairphone FP3 phones
- Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs, along
with their evaluation boards
- Samsung Exynos 850 phone SoC and reference board
- Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone
- Tesla FSD (Fully Self-Driving), an automotive SoC loosely derived
from the Samsung Exynos family.
- TI K3/AM62 SoC and reference board
Support for additional functionality in existing dts files is added
all over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91,
Allwinner, i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and
Broadcom.
Samsung has a rework for its pinctrl schema that is a bit tricky and
requires driver changes to be included here.
A few more platforms only have smaller cleanups and DT Schema fixes,
this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno.
The new machines are really too many to list, but I'll do it anyway:
Allwinner:
- A20-Marsboard development board
Amlogic:
- Amediatek X96-AIR (Amlogic S905X3)
- CYX A95XF3-AIR (Amlogic S905X3)
- Haochuangy H96-Max (Amlogic S905X3)
- Amlogic AQ222 (Amlogic S4)
- OSMC Vero 4K+ (Amlogic S905D)
Arm Juno:
- Separate DT depending on SCMI firmware version
Aspeed:
- Quanta S6Q BMC (AST2600)
- ASRock ROMED8HM3 (AST2500)
Broadcom:
- Raspberry Pi Zero 2 W
Marvell MVEBU/Armada:
- Ctera C200 V1 NAS (kirkwood)
- Ctera C200 V2 NAS (armada-370)
Mstar:
- DongShanPiOne, a low-end embedded board
- Miyoo Mini handheld game console
NXP i.MX:
- Numerous i.MX8M Mini based boards in even more variations, but
none based on other SoCs this time:
Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and
Gateworks GW7903
Qualcomm:
- Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3)
- SHIFT6mq phone (Snapdragon 845)
- Samsung Galaxy Book2 (Snapdragon 850)
- Snapdragon 8 Gen 1 Hardware Development Kit
TI OMAP:
- SanCloud BeagleBone Enhanced WiFi
Rockchip:
- Pine64 PineNote ereader tablet (rk356x)
- Bananapi-R2-Pro (rk356x)
STM32:
- emtrion emSBS-Argon embedded board (stm32mp157c)"
* tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (627 commits)
arm64: dts: n5x: drop invalid property and fix edac node name
arm64: dts: fsd: Add the MCT support
arm64: dts: stingray: Fix spi clock name
arm64: dts: ns2: Fix spi clock name
ARM: dts: rockchip: Update regulator name for PX3
ARM: dts: rockchip: Add #clock-cells value for rk805
arm64: dts: rockchip: Add #clock-cells value for rk805
arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808
arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly
ARM: dts: at91: sama7g5: Add NAND support
ARM: dts: at91: sama7g5: add eic node
ARM: dts: at91: sama7g5: Remove unused properties in i2c nodes
ARM: dts: at91: sam9x60ek: modify vdd_1v5 regulator to vdd_1v15
arm64: dts: lg: align pl330 node name with dtschema
arm64: dts: lg: add dma-cells to pl330 node
arm64: dts: juno: align pl330 node name with dtschema
arm64: dts: broadcom: Fix sata nodename
arm64: dts: n5x: add sdr edac support
arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node
dt-bindings: usb: dwc2: add disable-over-current
...
|
||
|
Linus Torvalds
|
194dfe88d6 |
asm-generic updates for 5.18
There are three sets of updates for 5.18 in the asm-generic tree:
- The set_fs()/get_fs() infrastructure gets removed for good. This
was already gone from all major architectures, but now we can
finally remove it everywhere, which loses some particularly
tricky and error-prone code.
There is a small merge conflict against a parisc cleanup, the
solution is to use their new version.
- The nds32 architecture ends its tenure in the Linux kernel. The
hardware is still used and the code is in reasonable shape, but
the mainline port is not actively maintained any more, as all
remaining users are thought to run vendor kernels that would never
be updated to a future release.
There are some obvious conflicts against changes to the removed
files.
- A series from Masahiro Yamada cleans up some of the uapi header
files to pass the compile-time checks.
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Merge tag 'asm-generic-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic
Pull asm-generic updates from Arnd Bergmann:
"There are three sets of updates for 5.18 in the asm-generic tree:
- The set_fs()/get_fs() infrastructure gets removed for good.
This was already gone from all major architectures, but now we can
finally remove it everywhere, which loses some particularly tricky
and error-prone code. There is a small merge conflict against a
parisc cleanup, the solution is to use their new version.
- The nds32 architecture ends its tenure in the Linux kernel.
The hardware is still used and the code is in reasonable shape, but
the mainline port is not actively maintained any more, as all
remaining users are thought to run vendor kernels that would never
be updated to a future release.
- A series from Masahiro Yamada cleans up some of the uapi header
files to pass the compile-time checks"
* tag 'asm-generic-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (27 commits)
nds32: Remove the architecture
uaccess: remove CONFIG_SET_FS
ia64: remove CONFIG_SET_FS support
sh: remove CONFIG_SET_FS support
sparc64: remove CONFIG_SET_FS support
lib/test_lockup: fix kernel pointer check for separate address spaces
uaccess: generalize access_ok()
uaccess: fix type mismatch warnings from access_ok()
arm64: simplify access_ok()
m68k: fix access_ok for coldfire
MIPS: use simpler access_ok()
MIPS: Handle address errors for accesses above CPU max virtual user address
uaccess: add generic __{get,put}_kernel_nofault
nios2: drop access_ok() check from __put_user()
x86: use more conventional access_ok() definition
x86: remove __range_not_ok()
sparc64: add __{get,put}_kernel_nofault()
nds32: fix access_ok() checks in get/put_user
uaccess: fix nios2 and microblaze get_user_8()
sparc64: fix building assembly files
...
|
||
|
Thomas Gleixner
|
b166e52541 |
- Fix return error code check for the timer-of layer when getting
the base address (Guillaume Ranquet) - Remove MMIO dependency, add notrace annotation for sched_clock and increase the timer resolution for the Microchip PIT64b (Claudiu Beznea) - Convert DT bindings to yaml for the Tegra timer (David Heidelberg) - Fix compilation error on architecture other than ARM for the i.MX TPM (Nathan Chancellor) - Add support for the event stream scaling for 1GHz counter on the arch ARM timer (Marc Zyngier) - Support a higher number of interrupts by the Exynos MCT timer driver (Alim Akhtar) - Detect and prevent memory corruption when the specified number of interrupts in the DTS is greater than the array size in the code for the Exynos MCT timer (Krzysztof Kozlowski) - Fix regression from a previous errata fix on the TI DM timer (Drew Fustini) - Several fixes and code improvements for the i.MX TPM driver (Peng Fan) -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEGn3N4YVz0WNVyHskqDIjiipP6E8FAmInK5IACgkQqDIjiipP 6E8RGwf+MD5KDipAWvPgpcwt5+8lO22AfUmBjDWbWWfw65UsTT0rvRFXX+nr3aO8 ETJrEyMMZMSX5ZrAiI5JYqc/Bdmxu67ycSll1z4NIjG3taZ+chxfSusa0vX63wQ1 lIGKVZu2BzU7I66Ni3UvWVag4Gsxoe9Xhmss7Y/9kZdKZT+XWgYYhttAYxKSs/a/ MnG1w3/IBsG2ZiQRwWivPdFAnkkcyRpkLy0JDRuet2W97rx6LjzGfE+6VtcjoMjy FZ0AYg9h3yA7F0IaloVL5c6FXPLeWky7O6c4GddHPiJnw0SqnMvo0fGP5Etcjk0I MDCMZO+3dfEu95irGIiNbS3ALDqD0Q== =YoAx -----END PGP SIGNATURE----- Merge tag 'timers-v5.18-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clocksource/events updates from Daniel Lezcano: - Fix return error code check for the timer-of layer when getting the base address (Guillaume Ranquet) - Remove MMIO dependency, add notrace annotation for sched_clock and increase the timer resolution for the Microchip PIT64b (Claudiu Beznea) - Convert DT bindings to yaml for the Tegra timer (David Heidelberg) - Fix compilation error on architecture other than ARM for the i.MX TPM (Nathan Chancellor) - Add support for the event stream scaling for 1GHz counter on the arch ARM timer (Marc Zyngier) - Support a higher number of interrupts by the Exynos MCT timer driver (Alim Akhtar) - Detect and prevent memory corruption when the specified number of interrupts in the DTS is greater than the array size in the code for the Exynos MCT timer (Krzysztof Kozlowski) - Fix regression from a previous errata fix on the TI DM timer (Drew Fustini) - Several fixes and code improvements for the i.MX TPM driver (Peng Fan) Link: https://lore.kernel.org/all/a8cd9be9-7d70-80df-2b74-1a8226a215e1@linaro.org |
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David Heidelberg
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cea9ffe009 |
dt-bindings: timer: Tegra: Convert text bindings to yaml
Convert Tegra timer binding into yaml format. This commit also merge 3 text bindings with almost identical content (differens in number of registers). Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20220303233307.61753-1-david@ixit.cz Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
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Alan Kao
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aec499c75c |
nds32: Remove the architecture
The nds32 architecture, also known as AndeStar V3, is a custom 32-bit RISC target designed by Andes Technologies. Support was added to the kernel in 2016 as the replacement RISC-V based V5 processors were already announced, and maintained by (current or former) Andes employees. As explained by Alan Kao, new customers are now all using RISC-V, and all known nds32 users are already on longterm stable kernels provided by Andes, with no development work going into mainline support any more. While the port is still in a reasonably good shape, it only gets worse over time without active maintainers, so it seems best to remove it before it becomes unusable. As always, if it turns out that there are mainline users after all, and they volunteer to maintain the port in the future, the removal can be reverted. Link: https://lore.kernel.org/linux-mm/YhdWNLUhk+x9RAzU@yamatobi.andestech.com/ Link: https://lore.kernel.org/lkml/20220302065213.82702-1-alankao@andestech.com/ Link: https://www.andestech.com/en/products-solutions/andestar-architecture/ Signed-off-by: Alan Kao <alankao@andestech.com> [arnd: rewrite changelog to provide more background] Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Lad Prabhakar
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7419553d03 |
dt-bindings: timer: renesas: ostm: Document Renesas RZ/V2L OSTM
Document the General Timer Module(a.k.a OSTM) found on the RZ/V2L SoC. OSTM module is identical to one found RZ/G2L SoC. No driver changes are required as generic compatible string "renesas,ostm" will be used as a fallback. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220227224845.27348-1-prabhakar.mahadev-lad.rj@bp.renesas.com |