mirror of
https://git.proxmox.com/git/mirror_ubuntu-kernels.git
synced 2025-11-30 21:23:57 +00:00
dt-bindings: arm-smmu: Add bindings for qcom,smmu-v2
Add bindings doc for Qcom's smmu-v2 implementation. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
parent
655e364374
commit
f1518cd84b
@ -17,10 +17,16 @@ conditions.
|
|||||||
"arm,mmu-401"
|
"arm,mmu-401"
|
||||||
"arm,mmu-500"
|
"arm,mmu-500"
|
||||||
"cavium,smmu-v2"
|
"cavium,smmu-v2"
|
||||||
|
"qcom,smmu-v2"
|
||||||
|
|
||||||
depending on the particular implementation and/or the
|
depending on the particular implementation and/or the
|
||||||
version of the architecture implemented.
|
version of the architecture implemented.
|
||||||
|
|
||||||
|
Qcom SoCs must contain, as below, SoC-specific compatibles
|
||||||
|
along with "qcom,smmu-v2":
|
||||||
|
"qcom,msm8996-smmu-v2", "qcom,smmu-v2",
|
||||||
|
"qcom,sdm845-smmu-v2", "qcom,smmu-v2".
|
||||||
|
|
||||||
- reg : Base address and size of the SMMU.
|
- reg : Base address and size of the SMMU.
|
||||||
|
|
||||||
- #global-interrupts : The number of global interrupts exposed by the
|
- #global-interrupts : The number of global interrupts exposed by the
|
||||||
@ -71,6 +77,22 @@ conditions.
|
|||||||
or using stream matching with #iommu-cells = <2>, and
|
or using stream matching with #iommu-cells = <2>, and
|
||||||
may be ignored if present in such cases.
|
may be ignored if present in such cases.
|
||||||
|
|
||||||
|
- clock-names: List of the names of clocks input to the device. The
|
||||||
|
required list depends on particular implementation and
|
||||||
|
is as follows:
|
||||||
|
- for "qcom,smmu-v2":
|
||||||
|
- "bus": clock required for downstream bus access and
|
||||||
|
for the smmu ptw,
|
||||||
|
- "iface": clock required to access smmu's registers
|
||||||
|
through the TCU's programming interface.
|
||||||
|
- unspecified for other implementations.
|
||||||
|
|
||||||
|
- clocks: Specifiers for all clocks listed in the clock-names property,
|
||||||
|
as per generic clock bindings.
|
||||||
|
|
||||||
|
- power-domains: Specifiers for power domains required to be powered on for
|
||||||
|
the SMMU to operate, as per generic power domain bindings.
|
||||||
|
|
||||||
** Deprecated properties:
|
** Deprecated properties:
|
||||||
|
|
||||||
- mmu-masters (deprecated in favour of the generic "iommus" binding) :
|
- mmu-masters (deprecated in favour of the generic "iommus" binding) :
|
||||||
@ -137,3 +159,20 @@ conditions.
|
|||||||
iommu-map = <0 &smmu3 0 0x400>;
|
iommu-map = <0 &smmu3 0 0x400>;
|
||||||
...
|
...
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* Qcom's arm,smmu-v2 implementation */
|
||||||
|
smmu4: iommu@d00000 {
|
||||||
|
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
|
||||||
|
reg = <0xd00000 0x10000>;
|
||||||
|
|
||||||
|
#global-interrupts = <1>;
|
||||||
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#iommu-cells = <1>;
|
||||||
|
power-domains = <&mmcc MDSS_GDSC>;
|
||||||
|
|
||||||
|
clocks = <&mmcc SMMU_MDP_AXI_CLK>,
|
||||||
|
<&mmcc SMMU_MDP_AHB_CLK>;
|
||||||
|
clock-names = "bus", "iface";
|
||||||
|
};
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user