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arm64: dts: qcom: sm8450: add PCIe0 PHY node

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Add device tree node for the first PCIe PHY device found on the Qualcomm
SM8450 platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220301061500.2110569-2-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov 2022-03-01 09:14:54 +03:00 committed by Bjorn Andersson
parent 9499240d15
commit d41a72c24c
1 changed files with 40 additions and 2 deletions
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42
arch/arm64/boot/dts/qcom/sm8450.dtsi
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@ -683,8 +683,12 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "bi_tcxo", "sleep_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&pcie0_lane>,
<&sleep_clk>;
clock-names = "bi_tcxo",
"pcie_0_pipe_clk",
"sleep_clk";
};
qupv3_id_0: geniqup@9c0000 {
@ -750,6 +754,40 @@
};
};
pcie0_phy: phy@1c06000 {
compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
reg = <0 0x01c06000 0 0x200>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
status = "disabled";
pcie0_lane: lanes@1c06200 {
reg = <0 0x1c06e00 0 0x200>, /* tx */
<0 0x1c07000 0 0x200>, /* rx */
<0 0x1c06200 0 0x200>, /* pcs */
<0 0x1c06600 0 0x200>; /* pcs_pcie */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
#clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
};
};
config_noc: interconnect@1500000 {
compatible = "qcom,sm8450-config-noc";
reg = <0 0x01500000 0 0x1c000>;