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x86/apic: Consolidate wait_icr_idle() implementations

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Two copies and also needlessly public. Move it into ipi.c so it can be
inlined. Rename it to apic_mem_wait_icr_idle().

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Sohil Mehta <sohil.mehta@intel.com>
Tested-by: Juergen Gross <jgross@suse.com> # Xen PV (dom0 and unpriv. guest)
This commit is contained in:
Thomas Gleixner 2023-08-08 15:04:04 -07:00 committed by Dave Hansen
parent 01363d4f76
commit cfebd0077f
7 changed files with 9 additions and 14 deletions
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1
arch/x86/include/asm/apic.h
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@ -98,7 +98,6 @@ static inline u32 native_apic_mem_read(u32 reg)
return *((volatile u32 *)(APIC_BASE + reg));
}
extern void native_apic_wait_icr_idle(void);
extern u32 native_safe_apic_wait_icr_idle(void);
extern void native_apic_icr_write(u32 low, u32 id);
extern u64 native_apic_icr_read(void);

6
arch/x86/kernel/apic/apic.c
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@ -240,12 +240,6 @@ static void __init apic_disable(void)
apic = &apic_noop;
}
void native_apic_wait_icr_idle(void)
{
while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
cpu_relax();
}
u32 native_safe_apic_wait_icr_idle(void)
{
u32 send_status;

4
arch/x86/kernel/apic/apic_flat_64.c
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@ -111,7 +111,7 @@ static struct apic apic_flat __ro_after_init = {
.eoi_write = native_apic_mem_write,
.icr_read = native_apic_icr_read,
.icr_write = native_apic_icr_write,
.wait_icr_idle = native_apic_wait_icr_idle,
.wait_icr_idle = apic_mem_wait_icr_idle,
.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
};
@ -187,7 +187,7 @@ static struct apic apic_physflat __ro_after_init = {
.eoi_write = native_apic_mem_write,
.icr_read = native_apic_icr_read,
.icr_write = native_apic_icr_write,
.wait_icr_idle = native_apic_wait_icr_idle,
.wait_icr_idle = apic_mem_wait_icr_idle,
.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
};

2
arch/x86/kernel/apic/bigsmp_32.c
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@ -108,7 +108,7 @@ static struct apic apic_bigsmp __ro_after_init = {
.eoi_write = native_apic_mem_write,
.icr_read = native_apic_icr_read,
.icr_write = native_apic_icr_write,
.wait_icr_idle = native_apic_wait_icr_idle,
.wait_icr_idle = apic_mem_wait_icr_idle,
.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
};

6
arch/x86/kernel/apic/ipi.c
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@ -102,7 +102,7 @@ static inline int __prepare_ICR2(unsigned int mask)
return SET_XAPIC_DEST_FIELD(mask);
}
static inline void __xapic_wait_icr_idle(void)
void apic_mem_wait_icr_idle(void)
{
while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY)
cpu_relax();
@ -137,7 +137,7 @@ static void __default_send_IPI_shortcut(unsigned int shortcut, int vector)
if (unlikely(vector == NMI_VECTOR))
safe_apic_wait_icr_idle();
else
__xapic_wait_icr_idle();
apic_mem_wait_icr_idle();
/* Destination field (ICR2) and the destination mode are ignored */
native_apic_mem_write(APIC_ICR, __prepare_ICR(shortcut, vector, 0));
@ -154,7 +154,7 @@ void __default_send_IPI_dest_field(unsigned int dest_mask, int vector,
if (unlikely(vector == NMI_VECTOR))
safe_apic_wait_icr_idle();
else
__xapic_wait_icr_idle();
apic_mem_wait_icr_idle();
/* Set the IPI destination field in the ICR */
native_apic_mem_write(APIC_ICR2, __prepare_ICR2(dest_mask));

2
arch/x86/kernel/apic/local.h
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@ -44,6 +44,8 @@ static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector,
void default_init_apic_ldr(void);
void apic_mem_wait_icr_idle(void);
/*
* This is used to send an IPI with no shorthand notation (the destination is
* specified in bits 56 to 63 of the ICR).

2
arch/x86/kernel/apic/probe_32.c
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@ -64,7 +64,7 @@ static struct apic apic_default __ro_after_init = {
.eoi_write = native_apic_mem_write,
.icr_read = native_apic_icr_read,
.icr_write = native_apic_icr_write,
.wait_icr_idle = native_apic_wait_icr_idle,
.wait_icr_idle = apic_mem_wait_icr_idle,
.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
};