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rtw89: 8852c: add BB initial and reset functions
chip_ops::bb_sethw is to initialize BB settings out of BB parameters tables. Once switching channel or initialing, we do chip_ops::bb_reset to reset hardware counters and states to make things in expectation. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220414062027.62638-6-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
Kalle Valo
parent
c7845551bf
commit
cc99eefa61
@ -3280,6 +3280,10 @@
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#define B_ANAPAR_FLTRST BIT(22)
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#define B_ANAPAR_CRXBB GENMASK(18, 16)
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#define B_ANAPAR_14 GENMASK(15, 0)
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#define R_RFE_E_A2 0x0334
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#define R_RFE_O_SEL_A2 0x0338
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#define R_RFE_SEL0_A2 0x033C
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#define R_RFE_SEL32_A2 0x0340
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#define R_SWSI_DATA_V1 0x0370
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#define B_SWSI_DATA_VAL_V1 GENMASK(19, 0)
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#define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20)
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@ -3340,6 +3344,8 @@
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#define B_PMAC_PTX_EN BIT(4)
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#define R_PMAC_TX_CNT 0x09C8
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#define B_PMAC_TX_CNT_MSK GENMASK(31, 0)
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#define R_DBCC_80P80_SEL_EVM_RPT 0x0A10
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#define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0)
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#define R_CCX 0x0C00
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#define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4)
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#define B_MEASUREMENT_TRIG_MSK BIT(2)
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@ -3380,6 +3386,8 @@
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#define R_BRK_ASYNC_RST_EN_1 0x0DC0
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#define R_BRK_ASYNC_RST_EN_2 0x0DC4
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#define R_BRK_ASYNC_RST_EN_3 0x0DC8
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#define R_S0_HW_SI_DIS 0x1200
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#define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
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#define R_P0_RXCK 0x12A0
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#define B_P0_RXCK_VAL GENMASK(18, 16)
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#define B_P0_RXCK_ON BIT(19)
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@ -3460,16 +3468,24 @@
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#define B_TXFIR_CCD GENMASK(23, 0)
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#define R_TXFIRE 0x231c
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#define B_TXFIR_CEF GENMASK(23, 0)
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#define R_11B_RX_V1 0x2320
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#define B_11B_RXCCA_DIS_V1 BIT(0)
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#define R_RXCCA 0x2344
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#define B_RXCCA_DIS BIT(31)
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#define R_RXCCA_V1 0x2320
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#define B_RXCCA_DIS_V1 BIT(0)
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#define R_RXSC 0x237C
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#define B_RXSC_EN BIT(0)
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#define R_RXSCOBC 0x23B0
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#define B_RXSCOBC_TH GENMASK(18, 0)
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#define R_RXSCOCCK 0x23B4
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#define B_RXSCOCCK_TH GENMASK(18, 0)
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#define R_DBCC_80P80_SEL_EVM_RPT2 0x2A10
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#define B_DBCC_80P80_SEL_EVM_RPT2_EN BIT(0)
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#define R_P1_EN_SOUND_WO_NDP 0x2D7C
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#define B_P1_EN_SOUND_WO_NDP BIT(1)
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#define R_S1_HW_SI_DIS 0x3200
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#define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
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#define R_P1_DBGMOD 0x32B8
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#define B_P1_DBGMOD_ON BIT(30)
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#define R_S1_RXDC 0x32D4
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@ -3614,6 +3630,16 @@
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#define R_P0_RFCTM 0x5864
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#define B_P0_RFCTM_VAL GENMASK(25, 20)
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#define R_P0_RFCTM_RDY BIT(26)
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#define R_P0_TRSW 0x5868
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#define B_P0_TRSW_B BIT(0)
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#define B_P0_TRSW_A BIT(1)
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#define B_P0_TRSW_X BIT(2)
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#define B_P0_TRSW_SO_A2 GENMASK(7, 5)
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#define R_P0_RFM 0x5894
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#define B_P0_RFM_DIS_WL BIT(7)
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#define B_P0_RFM_TX_OPT BIT(6)
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#define B_P0_RFM_BT_EN BIT(5)
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#define B_P0_RFM_OUT GENMASK(4, 0)
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#define R_P0_TXDPD 0x58D4
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#define B_P0_TXDPD GENMASK(31, 28)
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#define R_P0_TXPW_RSTB 0x58DC
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@ -495,6 +495,186 @@ static void rtw8852c_power_trim(struct rtw89_dev *rtwdev)
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rtw8852c_pa_bias_trim(rtwdev);
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}
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static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx)
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{
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/*HW SI reset*/
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rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
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0x7);
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rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
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0x7);
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udelay(1);
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rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
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phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
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phy_idx);
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/*HW SI reset*/
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rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
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0x0);
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rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
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0x0);
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rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
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phy_idx);
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}
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static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx, bool en)
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{
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struct rtw89_hal *hal = &rtwdev->hal;
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if (en) {
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rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
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B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
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B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
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phy_idx);
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if (hal->current_band_type == RTW89_BAND_2G)
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rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0);
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rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
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} else {
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rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1);
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rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
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rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
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B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
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rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
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B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
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fsleep(1);
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rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
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phy_idx);
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}
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}
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static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx)
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{
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rtw8852c_bb_reset_all(rtwdev, phy_idx);
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}
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static
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void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
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u8 tx_path_en, u8 trsw_tx,
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u8 trsw_rx, u8 trsw, u8 trsw_b)
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{
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static const u32 path_cr_bases[] = {0x5868, 0x7868};
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u32 mask_ofst = 16;
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u32 cr;
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u32 val;
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if (path >= ARRAY_SIZE(path_cr_bases))
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return;
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cr = path_cr_bases[path];
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mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;
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val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b);
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rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
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}
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enum rtw8852c_rfe_src {
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PAPE_RFM,
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TRSW_RFM,
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LNAON_RFM,
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};
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static
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void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
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enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl,
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u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val)
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{
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static const u32 path_cr_bases[] = {0x5894, 0x7894};
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static const u32 masks[] = {0, 8, 16};
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u32 mask, mask_ofst;
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u32 cr;
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u32 val;
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if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases))
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return;
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mask_ofst = masks[src];
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cr = path_cr_bases[path];
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val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) |
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FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) |
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FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) |
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FIELD_PREP(B_P0_RFM_OUT, rfm_output_val);
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mask = 0xff << mask_ofst;
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rtw89_phy_write32_mask(rtwdev, cr, mask, val);
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}
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static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev)
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{
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static const u32 cr_bases[] = {0x5800, 0x7800};
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u32 addr;
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u8 i;
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for (i = 0; i < ARRAY_SIZE(cr_bases); i++) {
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addr = cr_bases[i];
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rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A);
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rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X);
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rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2);
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rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777);
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rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777);
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}
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rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
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rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
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rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
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rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0);
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rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0);
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rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0);
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rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4);
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rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8);
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rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0);
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rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4);
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rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8);
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}
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static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx)
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{
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u32 addr;
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for (addr = R_AX_PWR_MACID_LMT_TABLE0;
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addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
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rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
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}
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static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev)
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{
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rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT,
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B_DBCC_80P80_SEL_EVM_RPT_EN);
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rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2,
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B_DBCC_80P80_SEL_EVM_RPT2_EN);
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rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
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rtw8852c_bb_gpio_init(rtwdev);
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}
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static
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void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
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s8 pw_ofst, enum rtw89_mac_idx mac_idx)
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@ -632,6 +812,8 @@ static void rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
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static const struct rtw89_chip_ops rtw8852c_chip_ops = {
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.enable_bb_rf = rtw8852c_mac_enable_bb_rf,
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.disable_bb_rf = rtw8852c_mac_disable_bb_rf,
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.bb_reset = rtw8852c_bb_reset,
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.bb_sethw = rtw8852c_bb_sethw,
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.read_efuse = rtw8852c_read_efuse,
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.read_phycap = rtw8852c_read_phycap,
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.power_trim = rtw8852c_power_trim,
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