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KVM: riscv: selftests: Generate ISA extension reg_list using macros
Various ISA extension reg_list have common pattern so let us generate these using macros. We define two macros for the above purpose: 1) KVM_ISA_EXT_SIMPLE_CONFIG - Macro to generate reg_list for ISA extension without any additional ONE_REG registers 2) KVM_ISA_EXT_SUBLIST_CONFIG - Macro to generate reg_list for ISA extension with additional ONE_REG registers This patch also adds the missing config for svnapot. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Anup Patel
Anup Patel
parent
bcd08e9bae
commit
c19829ba1e
@ -583,10 +583,6 @@ static __u64 base_skips_set[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),
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};
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static __u64 h_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_H,
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};
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static __u64 zicbom_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size),
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM,
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@ -597,54 +593,6 @@ static __u64 zicboz_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ,
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};
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static __u64 svpbmt_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT,
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};
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static __u64 sstc_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC,
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};
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static __u64 svinval_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL,
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};
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static __u64 zihintpause_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
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};
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static __u64 zba_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA,
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};
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static __u64 zbb_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB,
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};
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static __u64 zbs_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS,
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};
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static __u64 zicntr_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR,
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};
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static __u64 zicond_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND,
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};
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static __u64 zicsr_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR,
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};
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static __u64 zifencei_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI,
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};
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static __u64 zihpm_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM,
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};
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static __u64 aia_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect),
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1),
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@ -735,221 +683,94 @@ static __u64 fp_d_regs[] = {
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D,
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};
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#define BASE_SUBLIST \
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#define SUBLIST_BASE \
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{"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \
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.skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),}
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#define H_REGS_SUBLIST \
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{"h", .feature = KVM_RISCV_ISA_EXT_H, .regs = h_regs, .regs_n = ARRAY_SIZE(h_regs),}
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#define ZICBOM_REGS_SUBLIST \
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#define SUBLIST_ZICBOM \
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{"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}
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#define ZICBOZ_REGS_SUBLIST \
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#define SUBLIST_ZICBOZ \
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{"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}
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#define SVPBMT_REGS_SUBLIST \
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{"svpbmt", .feature = KVM_RISCV_ISA_EXT_SVPBMT, .regs = svpbmt_regs, .regs_n = ARRAY_SIZE(svpbmt_regs),}
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#define SSTC_REGS_SUBLIST \
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{"sstc", .feature = KVM_RISCV_ISA_EXT_SSTC, .regs = sstc_regs, .regs_n = ARRAY_SIZE(sstc_regs),}
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#define SVINVAL_REGS_SUBLIST \
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{"svinval", .feature = KVM_RISCV_ISA_EXT_SVINVAL, .regs = svinval_regs, .regs_n = ARRAY_SIZE(svinval_regs),}
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#define ZIHINTPAUSE_REGS_SUBLIST \
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{"zihintpause", .feature = KVM_RISCV_ISA_EXT_ZIHINTPAUSE, .regs = zihintpause_regs, .regs_n = ARRAY_SIZE(zihintpause_regs),}
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#define ZBA_REGS_SUBLIST \
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{"zba", .feature = KVM_RISCV_ISA_EXT_ZBA, .regs = zba_regs, .regs_n = ARRAY_SIZE(zba_regs),}
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#define ZBB_REGS_SUBLIST \
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{"zbb", .feature = KVM_RISCV_ISA_EXT_ZBB, .regs = zbb_regs, .regs_n = ARRAY_SIZE(zbb_regs),}
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#define ZBS_REGS_SUBLIST \
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{"zbs", .feature = KVM_RISCV_ISA_EXT_ZBS, .regs = zbs_regs, .regs_n = ARRAY_SIZE(zbs_regs),}
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#define ZICNTR_REGS_SUBLIST \
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{"zicntr", .feature = KVM_RISCV_ISA_EXT_ZICNTR, .regs = zicntr_regs, .regs_n = ARRAY_SIZE(zicntr_regs),}
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#define ZICOND_REGS_SUBLIST \
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{"zicond", .feature = KVM_RISCV_ISA_EXT_ZICOND, .regs = zicond_regs, .regs_n = ARRAY_SIZE(zicond_regs),}
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#define ZICSR_REGS_SUBLIST \
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{"zicsr", .feature = KVM_RISCV_ISA_EXT_ZICSR, .regs = zicsr_regs, .regs_n = ARRAY_SIZE(zicsr_regs),}
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#define ZIFENCEI_REGS_SUBLIST \
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{"zifencei", .feature = KVM_RISCV_ISA_EXT_ZIFENCEI, .regs = zifencei_regs, .regs_n = ARRAY_SIZE(zifencei_regs),}
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#define ZIHPM_REGS_SUBLIST \
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{"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),}
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#define AIA_REGS_SUBLIST \
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#define SUBLIST_AIA \
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{"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}
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#define SMSTATEEN_REGS_SUBLIST \
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#define SUBLIST_SMSTATEEN \
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{"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}
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#define FP_F_REGS_SUBLIST \
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#define SUBLIST_FP_F \
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{"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \
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.regs_n = ARRAY_SIZE(fp_f_regs),}
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#define FP_D_REGS_SUBLIST \
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#define SUBLIST_FP_D \
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{"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \
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.regs_n = ARRAY_SIZE(fp_d_regs),}
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static struct vcpu_reg_list h_config = {
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.sublists = {
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BASE_SUBLIST,
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H_REGS_SUBLIST,
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{0},
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},
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};
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#define KVM_ISA_EXT_SIMPLE_CONFIG(ext, extu) \
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static __u64 regs_##ext[] = { \
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KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \
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KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_##extu, \
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}; \
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static struct vcpu_reg_list config_##ext = { \
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.sublists = { \
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SUBLIST_BASE, \
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{ \
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.name = #ext, \
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.feature = KVM_RISCV_ISA_EXT_##extu, \
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.regs = regs_##ext, \
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.regs_n = ARRAY_SIZE(regs_##ext), \
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}, \
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{0}, \
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}, \
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} \
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static struct vcpu_reg_list zicbom_config = {
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.sublists = {
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BASE_SUBLIST,
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ZICBOM_REGS_SUBLIST,
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{0},
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},
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};
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#define KVM_ISA_EXT_SUBLIST_CONFIG(ext, extu) \
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static struct vcpu_reg_list config_##ext = { \
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.sublists = { \
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SUBLIST_BASE, \
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SUBLIST_##extu, \
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{0}, \
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}, \
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} \
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static struct vcpu_reg_list zicboz_config = {
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.sublists = {
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BASE_SUBLIST,
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ZICBOZ_REGS_SUBLIST,
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{0},
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},
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};
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/* Note: The below list is alphabetically sorted. */
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static struct vcpu_reg_list svpbmt_config = {
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.sublists = {
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BASE_SUBLIST,
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SVPBMT_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list sstc_config = {
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.sublists = {
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BASE_SUBLIST,
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SSTC_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list svinval_config = {
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.sublists = {
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BASE_SUBLIST,
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SVINVAL_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list zihintpause_config = {
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.sublists = {
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BASE_SUBLIST,
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ZIHINTPAUSE_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list zba_config = {
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.sublists = {
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BASE_SUBLIST,
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ZBA_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list zbb_config = {
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.sublists = {
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BASE_SUBLIST,
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ZBB_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list zbs_config = {
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.sublists = {
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BASE_SUBLIST,
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ZBS_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list zicntr_config = {
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.sublists = {
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BASE_SUBLIST,
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ZICNTR_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list zicond_config = {
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.sublists = {
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BASE_SUBLIST,
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ZICOND_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list zicsr_config = {
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.sublists = {
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BASE_SUBLIST,
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ZICSR_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list zifencei_config = {
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.sublists = {
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BASE_SUBLIST,
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ZIFENCEI_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list zihpm_config = {
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.sublists = {
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BASE_SUBLIST,
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ZIHPM_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list aia_config = {
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.sublists = {
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BASE_SUBLIST,
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AIA_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list smstateen_config = {
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.sublists = {
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BASE_SUBLIST,
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SMSTATEEN_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list fp_f_config = {
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.sublists = {
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BASE_SUBLIST,
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FP_F_REGS_SUBLIST,
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{0},
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},
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};
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static struct vcpu_reg_list fp_d_config = {
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.sublists = {
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BASE_SUBLIST,
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FP_D_REGS_SUBLIST,
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{0},
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},
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};
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KVM_ISA_EXT_SUBLIST_CONFIG(aia, AIA);
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KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F);
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KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D);
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KVM_ISA_EXT_SIMPLE_CONFIG(h, H);
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KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN);
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KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);
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KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
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KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
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KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
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KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);
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KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB);
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KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS);
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KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
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KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
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KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
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KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);
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KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);
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KVM_ISA_EXT_SIMPLE_CONFIG(zifencei, ZIFENCEI);
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KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE);
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KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM);
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struct vcpu_reg_list *vcpu_configs[] = {
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&h_config,
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&zicbom_config,
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&zicboz_config,
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&svpbmt_config,
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&sstc_config,
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&svinval_config,
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&zihintpause_config,
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&zba_config,
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&zbb_config,
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&zbs_config,
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&zicntr_config,
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&zicond_config,
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&zicsr_config,
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&zifencei_config,
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&zihpm_config,
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&aia_config,
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&smstateen_config,
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&fp_f_config,
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&fp_d_config,
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&config_aia,
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&config_fp_f,
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&config_fp_d,
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&config_h,
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&config_smstateen,
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&config_sstc,
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&config_svinval,
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&config_svnapot,
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&config_svpbmt,
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&config_zba,
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&config_zbb,
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&config_zbs,
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&config_zicbom,
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&config_zicboz,
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&config_zicntr,
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&config_zicond,
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&config_zicsr,
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&config_zifencei,
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&config_zihintpause,
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&config_zihpm,
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};
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int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);
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