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drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2)

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Need to call the IP cg callbacks.

v2: fix gate logic

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2016-04-29 11:20:32 -04:00
parent ce90dbd9b8
commit bdf1ecea3c
1 changed files with 9 additions and 2 deletions
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11
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
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@ -47,10 +47,17 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
data->uvd_power_gated = bgate; data->uvd_power_gated = bgate;
if (bgate) if (bgate) {
cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE);
fiji_update_uvd_dpm(hwmgr, true); fiji_update_uvd_dpm(hwmgr, true);
else } else {
fiji_update_uvd_dpm(hwmgr, false); fiji_update_uvd_dpm(hwmgr, false);
cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_UNGATE);
}
return 0; return 0;
} }