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drm/amdgpu/gmc9: don't touch gfxhub registers during S0ix

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gfxhub registers are part of gfx IP and should not need to be
changed.  Doing so without disabling gfxoff can hang the gfx IP.

v2: add comments explaining why we can skip the interrupt
    control for S0i3

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2022-11-08 16:05:04 -05:00
parent 76a95b833a
commit b93df61dda
1 changed files with 30 additions and 6 deletions
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36
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
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@ -484,6 +484,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
for (i = 0; i < 16; i++) {
reg = hub->vm_context0_cntl + i;
/* This works because this interrupt is only
* enabled at init/resume and disabled in
* fini/suspend, so the overall state doesn't
* change over the course of suspend/resume.
*/
if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0))
continue;
if (j == AMDGPU_GFXHUB_0)
tmp = RREG32_SOC15_IP(GC, reg);
else
@ -504,6 +512,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
for (i = 0; i < 16; i++) {
reg = hub->vm_context0_cntl + i;
/* This works because this interrupt is only
* enabled at init/resume and disabled in
* fini/suspend, so the overall state doesn't
* change over the course of suspend/resume.
*/
if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0))
continue;
if (j == AMDGPU_GFXHUB_0)
tmp = RREG32_SOC15_IP(GC, reg);
else
@ -1862,9 +1878,12 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
}
amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
r = adev->gfxhub.funcs->gart_enable(adev);
if (r)
return r;
if (!adev->in_s0ix) {
r = adev->gfxhub.funcs->gart_enable(adev);
if (r)
return r;
}
r = adev->mmhub.funcs->gart_enable(adev);
if (r)
@ -1911,11 +1930,15 @@ static int gmc_v9_0_hw_init(void *handle)
value = true;
if (!amdgpu_sriov_vf(adev)) {
adev->gfxhub.funcs->set_fault_enable_default(adev, value);
if (!adev->in_s0ix)
adev->gfxhub.funcs->set_fault_enable_default(adev, value);
adev->mmhub.funcs->set_fault_enable_default(adev, value);
}
for (i = 0; i < adev->num_vmhubs; ++i)
for (i = 0; i < adev->num_vmhubs; ++i) {
if (adev->in_s0ix && (i == AMDGPU_GFXHUB_0))
continue;
gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
}
if (adev->umc.funcs && adev->umc.funcs->init_registers)
adev->umc.funcs->init_registers(adev);
@ -1939,7 +1962,8 @@ static int gmc_v9_0_hw_init(void *handle)
*/
static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
{
adev->gfxhub.funcs->gart_disable(adev);
if (!adev->in_s0ix)
adev->gfxhub.funcs->gart_disable(adev);
adev->mmhub.funcs->gart_disable(adev);
}