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drm/amd/display: disable clock gating logic reversed bug fix

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[Why]
disable clock gating logic reversed bug fix

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Muhammad Ahmed 2023-07-28 16:08:44 -04:00 committed by Alex Deucher
parent ad5594ad41
commit 97c2eba5d6
2 changed files with 4 additions and 4 deletions
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4
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
View File

@ -1018,8 +1018,8 @@ void hubbub31_init(struct hubbub *hubbub)
/*done in hwseq*/ /*done in hwseq*/
/*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/ /*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/
REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL, REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL,
DISPCLK_R_DCHUBBUB_GATE_DIS, 0, DISPCLK_R_DCHUBBUB_GATE_DIS, 1,
DCFCLK_R_DCHUBBUB_GATE_DIS, 0); DCFCLK_R_DCHUBBUB_GATE_DIS, 1);
} }
/* /*

4
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
View File

@ -955,8 +955,8 @@ void hubbub32_init(struct hubbub *hubbub)
/*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/ /*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/
REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL, REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL,
DISPCLK_R_DCHUBBUB_GATE_DIS, 0, DISPCLK_R_DCHUBBUB_GATE_DIS, 1,
DCFCLK_R_DCHUBBUB_GATE_DIS, 0); DCFCLK_R_DCHUBBUB_GATE_DIS, 1);
} }
/* /*
ignore the "df_pre_cstate_req" from the SDP port control. ignore the "df_pre_cstate_req" from the SDP port control.