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https://git.proxmox.com/git/mirror_ubuntu-kernels.git
synced 2025-12-09 18:26:58 +00:00
clk: renesas: Updates for v6.10 (take two)
- Miscellaneous fixes and improvements.
- Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on R-Car
V4M,
- Add interrupt controller (PLIC) clock and reset on RZ/Five,
- Prepare power domain support for RZ/G2L family members, and add
actual support on RZ/G3S SoC.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZitbAgAKCRCKwlD9ZEnx
cOv3AQCeITT+A5qog/T6uzT62sg04KTLSvuwbg/zKWaWZHVjMwEAlYF3OOw4UgBT
AvVQPfm6dth8xtmWdLT0ulPD5XYq7gc=
=mTx5
-----END PGP SIGNATURE-----
Merge tag 'renesas-clk-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Miscellaneous fixes and improvements
- Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on R-Car V4M
- Add interrupt controller (PLIC) clock and reset on RZ/Five
- Prepare power domain support for RZ/G2L family members, and add
actual support on RZ/G3S SoC
* tag 'renesas-clk-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a08g045: Add support for power domains
clk: renesas: rzg2l: Extend power domain support
dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S
dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
clk: renesas: r8a7740: Remove unused div4_clk.flags field
clk: renesas: r9a07g043: Add clock and reset entry for PLIC
clk: renesas: r8a779h0: Add INTC-EX clock
clk: renesas: r8a779h0: Add MSIOF clocks
clk: renesas: r8a779a0: Fix CANFD parent clock
This commit is contained in:
Stephen Boyd
commit
8beff78872
@ -57,7 +57,8 @@ properties:
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can be power-managed through Module Standby should refer to the CPG device
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node in their "power-domains" property, as documented by the generic PM
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Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
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const: 0
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The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
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be used to reference individual CPG power domains.
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'#reset-cells':
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description:
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@ -76,6 +77,21 @@ required:
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a08g045-cpg
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then:
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properties:
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'#power-domain-cells':
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const: 1
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else:
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properties:
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'#power-domain-cells':
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const: 0
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examples:
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- |
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cpg: clock-controller@11010000 {
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@ -30,8 +30,6 @@ struct r8a73a4_cpg {
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#define CPG_PLL2HCR 0xe4
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#define CPG_PLL2SCR 0xf4
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#define CLK_ENABLE_ON_INIT BIT(0)
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struct div4_clk {
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const char *name;
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unsigned int reg;
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@ -26,28 +26,25 @@ struct r8a7740_cpg {
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#define CPG_USBCKCR 0x8c
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#define CPG_FRQCRC 0xe0
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#define CLK_ENABLE_ON_INIT BIT(0)
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struct div4_clk {
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const char *name;
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unsigned int reg;
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unsigned int shift;
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int flags;
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};
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static struct div4_clk div4_clks[] = {
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{ "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
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{ "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
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{ "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
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{ "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
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{ "hp", CPG_FRQCRB, 4, 0 },
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{ "hpp", CPG_FRQCRC, 20, 0 },
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{ "usbp", CPG_FRQCRC, 16, 0 },
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{ "s", CPG_FRQCRC, 12, 0 },
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{ "zb", CPG_FRQCRC, 8, 0 },
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{ "m3", CPG_FRQCRC, 4, 0 },
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{ "cp", CPG_FRQCRC, 0, 0 },
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{ NULL, 0, 0, 0 },
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{ "i", CPG_FRQCRA, 20 },
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{ "zg", CPG_FRQCRA, 16 },
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{ "b", CPG_FRQCRA, 8 },
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{ "m1", CPG_FRQCRA, 4 },
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{ "hp", CPG_FRQCRB, 4 },
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{ "hpp", CPG_FRQCRC, 20 },
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{ "usbp", CPG_FRQCRC, 16 },
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{ "s", CPG_FRQCRC, 12 },
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{ "zb", CPG_FRQCRC, 8 },
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{ "m3", CPG_FRQCRC, 4 },
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{ "cp", CPG_FRQCRC, 0 },
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{ NULL, 0, 0 },
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};
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static const struct clk_div_table div4_div_table[] = {
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@ -34,8 +34,6 @@ struct sh73a0_cpg {
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#define CPG_DSI0PHYCR 0x6c
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#define CPG_DSI1PHYCR 0x70
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#define CLK_ENABLE_ON_INIT BIT(0)
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struct div4_clk {
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const char *name;
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const char *parent;
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@ -139,7 +139,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
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DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
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DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
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DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
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DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD),
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DEF_MOD("canfd0", 328, R8A779A0_CLK_S3D2),
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DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
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DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
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DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
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@ -184,6 +184,13 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
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DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER),
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DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
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DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
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DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M),
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DEF_MOD("msi0", 618, R8A779H0_CLK_MSO),
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DEF_MOD("msi1", 619, R8A779H0_CLK_MSO),
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DEF_MOD("msi2", 620, R8A779H0_CLK_MSO),
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DEF_MOD("msi3", 621, R8A779H0_CLK_MSO),
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DEF_MOD("msi4", 622, R8A779H0_CLK_MSO),
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DEF_MOD("msi5", 623, R8A779H0_CLK_MSO),
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DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
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DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4),
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DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4),
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@ -280,6 +280,10 @@ static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
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0x5a8, 1),
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DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
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0x5ac, 0),
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#ifdef CONFIG_RISCV
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DEF_MOD("nceplic_aclk", R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1,
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0x608, 0),
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#endif
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};
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static const struct rzg2l_reset r9a07g043_resets[] = {
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@ -338,6 +342,10 @@ static const struct rzg2l_reset r9a07g043_resets[] = {
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DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
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DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
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DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
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#ifdef CONFIG_RISCV
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DEF_RST(R9A07G043_NCEPLIC_ARESETN, 0x908, 0),
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#endif
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};
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static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
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@ -347,6 +355,7 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
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#endif
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#ifdef CONFIG_RISCV
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MOD_CLK_BASE + R9A07G043_IAX45_CLK,
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MOD_CLK_BASE + R9A07G043_NCEPLIC_ACLK,
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#endif
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MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
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};
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@ -240,6 +240,43 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
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MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
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};
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static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
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/* Keep always-on domain on the first position for proper domains registration. */
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DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
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DEF_REG_CONF(0, 0),
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RZG2L_PD_F_ALWAYS_ON),
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DEF_PD("gic", R9A08G045_PD_GIC,
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DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
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RZG2L_PD_F_ALWAYS_ON),
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DEF_PD("ia55", R9A08G045_PD_IA55,
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DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
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RZG2L_PD_F_ALWAYS_ON),
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DEF_PD("dmac", R9A08G045_PD_DMAC,
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DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
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RZG2L_PD_F_ALWAYS_ON),
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DEF_PD("wdt0", R9A08G045_PD_WDT0,
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DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),
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RZG2L_PD_F_NONE),
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DEF_PD("sdhi0", R9A08G045_PD_SDHI0,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),
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RZG2L_PD_F_NONE),
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DEF_PD("sdhi1", R9A08G045_PD_SDHI1,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),
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RZG2L_PD_F_NONE),
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DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
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RZG2L_PD_F_NONE),
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DEF_PD("eth0", R9A08G045_PD_ETHER0,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
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RZG2L_PD_F_NONE),
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DEF_PD("eth1", R9A08G045_PD_ETHER1,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
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RZG2L_PD_F_NONE),
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DEF_PD("scif0", R9A08G045_PD_SCIF0,
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DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
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RZG2L_PD_F_NONE),
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};
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const struct rzg2l_cpg_info r9a08g045_cpg_info = {
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/* Core Clocks */
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.core_clks = r9a08g045_core_clks,
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@ -260,5 +297,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
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.resets = r9a08g045_resets,
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.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
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/* Power domains */
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.pm_domains = r9a08g045_pm_domains,
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.num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
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.has_clk_mon_regs = true,
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};
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@ -139,7 +139,6 @@ struct rzg2l_pll5_mux_dsi_div_param {
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* @num_resets: Number of Module Resets in info->resets[]
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* @last_dt_core_clk: ID of the last Core Clock exported to DT
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* @info: Pointer to platform data
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* @genpd: PM domain
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* @mux_dsi_div_params: pll5 mux and dsi div parameters
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*/
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struct rzg2l_cpg_priv {
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@ -156,8 +155,6 @@ struct rzg2l_cpg_priv {
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const struct rzg2l_cpg_info *info;
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struct generic_pm_domain genpd;
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struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
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};
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@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
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return true;
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}
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/**
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* struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure
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* @onecell_data: cell data
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* @domains: generic PM domains
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*/
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struct rzg2l_cpg_pm_domains {
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struct genpd_onecell_data onecell_data;
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struct generic_pm_domain *domains[];
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};
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/**
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* struct rzg2l_cpg_pd - RZ/G2L power domain data structure
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* @genpd: generic PM domain
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* @priv: pointer to CPG private data structure
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* @conf: CPG PM domain configuration info
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* @id: RZ/G2L power domain ID
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*/
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struct rzg2l_cpg_pd {
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struct generic_pm_domain genpd;
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struct rzg2l_cpg_priv *priv;
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struct rzg2l_cpg_pm_domain_conf conf;
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u16 id;
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};
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static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
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{
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struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
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struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
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struct rzg2l_cpg_priv *priv = pd->priv;
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struct device_node *np = dev->of_node;
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struct of_phandle_args clkspec;
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bool once = true;
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@ -1617,31 +1639,180 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device
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}
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static void rzg2l_cpg_genpd_remove(void *data)
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{
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struct genpd_onecell_data *celldata = data;
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for (unsigned int i = 0; i < celldata->num_domains; i++)
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pm_genpd_remove(celldata->domains[i]);
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}
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static void rzg2l_cpg_genpd_remove_simple(void *data)
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{
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pm_genpd_remove(data);
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}
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static int rzg2l_cpg_power_on(struct generic_pm_domain *domain)
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{
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struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
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struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
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struct rzg2l_cpg_priv *priv = pd->priv;
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/* Set MSTOP. */
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if (mstop.mask)
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writel(mstop.mask << 16, priv->base + mstop.off);
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return 0;
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}
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static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
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{
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struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
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struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
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struct rzg2l_cpg_priv *priv = pd->priv;
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/* Set MSTOP. */
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if (mstop.mask)
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writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off);
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return 0;
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}
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static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on)
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{
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struct dev_power_governor *governor;
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pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
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pd->genpd.attach_dev = rzg2l_cpg_attach_dev;
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pd->genpd.detach_dev = rzg2l_cpg_detach_dev;
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if (always_on) {
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pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON;
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governor = &pm_domain_always_on_gov;
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} else {
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pd->genpd.power_on = rzg2l_cpg_power_on;
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pd->genpd.power_off = rzg2l_cpg_power_off;
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governor = &simple_qos_governor;
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}
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return pm_genpd_init(&pd->genpd, governor, !always_on);
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}
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|
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static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
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{
|
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struct device *dev = priv->dev;
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struct device_node *np = dev->of_node;
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struct generic_pm_domain *genpd = &priv->genpd;
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struct rzg2l_cpg_pd *pd;
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int ret;
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genpd->name = np->name;
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genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
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GENPD_FLAG_ACTIVE_WAKEUP;
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genpd->attach_dev = rzg2l_cpg_attach_dev;
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genpd->detach_dev = rzg2l_cpg_detach_dev;
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ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
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pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
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if (!pd)
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return -ENOMEM;
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pd->genpd.name = np->name;
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pd->priv = priv;
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ret = rzg2l_cpg_pd_setup(pd, true);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
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ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd);
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if (ret)
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return ret;
|
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|
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return of_genpd_add_provider_simple(np, genpd);
|
||||
return of_genpd_add_provider_simple(np, &pd->genpd);
|
||||
}
|
||||
|
||||
static struct generic_pm_domain *
|
||||
rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data)
|
||||
{
|
||||
struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
|
||||
struct genpd_onecell_data *genpd = data;
|
||||
|
||||
if (spec->args_count != 1)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
for (unsigned int i = 0; i < genpd->num_domains; i++) {
|
||||
struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd,
|
||||
genpd);
|
||||
|
||||
if (pd->id == spec->args[0]) {
|
||||
domain = &pd->genpd;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return domain;
|
||||
}
|
||||
|
||||
static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
|
||||
{
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
struct device *dev = priv->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct rzg2l_cpg_pm_domains *domains;
|
||||
struct generic_pm_domain *parent;
|
||||
u32 ncells;
|
||||
int ret;
|
||||
|
||||
ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* For backward compatibility. */
|
||||
if (!ncells)
|
||||
return rzg2l_cpg_add_clk_domain(priv);
|
||||
|
||||
domains = devm_kzalloc(dev, struct_size(domains, domains, info->num_pm_domains),
|
||||
GFP_KERNEL);
|
||||
if (!domains)
|
||||
return -ENOMEM;
|
||||
|
||||
domains->onecell_data.domains = domains->domains;
|
||||
domains->onecell_data.num_domains = info->num_pm_domains;
|
||||
domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
|
||||
|
||||
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (unsigned int i = 0; i < info->num_pm_domains; i++) {
|
||||
bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON);
|
||||
struct rzg2l_cpg_pd *pd;
|
||||
|
||||
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
|
||||
if (!pd)
|
||||
return -ENOMEM;
|
||||
|
||||
pd->genpd.name = info->pm_domains[i].name;
|
||||
pd->conf = info->pm_domains[i].conf;
|
||||
pd->id = info->pm_domains[i].id;
|
||||
pd->priv = priv;
|
||||
|
||||
ret = rzg2l_cpg_pd_setup(pd, always_on);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (always_on) {
|
||||
ret = rzg2l_cpg_power_on(&pd->genpd);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
domains->domains[i] = &pd->genpd;
|
||||
/* Parent should be on the very first entry of info->pm_domains[]. */
|
||||
if (!i) {
|
||||
parent = &pd->genpd;
|
||||
continue;
|
||||
}
|
||||
|
||||
ret = pm_genpd_add_subdomain(parent, &pd->genpd);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
|
||||
@ -1697,7 +1868,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = rzg2l_cpg_add_clk_domain(priv);
|
||||
error = rzg2l_cpg_add_pm_domains(priv);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
|
||||
@ -27,6 +27,18 @@
|
||||
#define CPG_PL6_ETH_SSEL (0x418)
|
||||
#define CPG_PL5_SDIV (0x420)
|
||||
#define CPG_RST_MON (0x680)
|
||||
#define CPG_BUS_ACPU_MSTOP (0xB60)
|
||||
#define CPG_BUS_MCPU1_MSTOP (0xB64)
|
||||
#define CPG_BUS_MCPU2_MSTOP (0xB68)
|
||||
#define CPG_BUS_PERI_COM_MSTOP (0xB6C)
|
||||
#define CPG_BUS_PERI_CPU_MSTOP (0xB70)
|
||||
#define CPG_BUS_PERI_DDR_MSTOP (0xB74)
|
||||
#define CPG_BUS_REG0_MSTOP (0xB7C)
|
||||
#define CPG_BUS_REG1_MSTOP (0xB80)
|
||||
#define CPG_BUS_TZCDDR_MSTOP (0xB84)
|
||||
#define CPG_MHU_MSTOP (0xB88)
|
||||
#define CPG_BUS_MCPU3_MSTOP (0xB90)
|
||||
#define CPG_BUS_PERI_CPU2_MSTOP (0xB94)
|
||||
#define CPG_OTHERFUNC1_REG (0xBE8)
|
||||
|
||||
#define CPG_SIPLL5_STBY_RESETB BIT(0)
|
||||
@ -234,6 +246,55 @@ struct rzg2l_reset {
|
||||
#define DEF_RST(_id, _off, _bit) \
|
||||
DEF_RST_MON(_id, _off, _bit, -1)
|
||||
|
||||
/**
|
||||
* struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure
|
||||
* @off: register offset
|
||||
* @mask: register mask
|
||||
*/
|
||||
struct rzg2l_cpg_reg_conf {
|
||||
u16 off;
|
||||
u16 mask;
|
||||
};
|
||||
|
||||
#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) })
|
||||
|
||||
/**
|
||||
* struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
|
||||
* @mstop: MSTOP register configuration
|
||||
*/
|
||||
struct rzg2l_cpg_pm_domain_conf {
|
||||
struct rzg2l_cpg_reg_conf mstop;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct rzg2l_cpg_pm_domain_init_data - PM domain init data
|
||||
* @name: PM domain name
|
||||
* @conf: PM domain configuration
|
||||
* @flags: RZG2L PM domain flags (see RZG2L_PD_F_*)
|
||||
* @id: PM domain ID (similar to the ones defined in
|
||||
* include/dt-bindings/clock/<soc-id>-cpg.h)
|
||||
*/
|
||||
struct rzg2l_cpg_pm_domain_init_data {
|
||||
const char * const name;
|
||||
struct rzg2l_cpg_pm_domain_conf conf;
|
||||
u32 flags;
|
||||
u16 id;
|
||||
};
|
||||
|
||||
#define DEF_PD(_name, _id, _mstop_conf, _flags) \
|
||||
{ \
|
||||
.name = (_name), \
|
||||
.id = (_id), \
|
||||
.conf = { \
|
||||
.mstop = (_mstop_conf), \
|
||||
}, \
|
||||
.flags = (_flags), \
|
||||
}
|
||||
|
||||
/* Power domain flags. */
|
||||
#define RZG2L_PD_F_ALWAYS_ON BIT(0)
|
||||
#define RZG2L_PD_F_NONE (0)
|
||||
|
||||
/**
|
||||
* struct rzg2l_cpg_info - SoC-specific CPG Description
|
||||
*
|
||||
@ -252,6 +313,8 @@ struct rzg2l_reset {
|
||||
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
|
||||
* should not be disabled without a knowledgeable driver
|
||||
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
|
||||
* @pm_domains: PM domains init data array
|
||||
* @num_pm_domains: Number of PM domains
|
||||
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
|
||||
*/
|
||||
struct rzg2l_cpg_info {
|
||||
@ -278,6 +341,10 @@ struct rzg2l_cpg_info {
|
||||
const unsigned int *crit_mod_clks;
|
||||
unsigned int num_crit_mod_clks;
|
||||
|
||||
/* Power domain. */
|
||||
const struct rzg2l_cpg_pm_domain_init_data *pm_domains;
|
||||
unsigned int num_pm_domains;
|
||||
|
||||
bool has_clk_mon_regs;
|
||||
};
|
||||
|
||||
|
||||
@ -200,5 +200,57 @@
|
||||
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
|
||||
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
|
||||
|
||||
/* Power domain IDs. */
|
||||
#define R9A07G043_PD_ALWAYS_ON 0
|
||||
#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */
|
||||
#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */
|
||||
#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */
|
||||
#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */
|
||||
#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */
|
||||
#define R9A07G043_PD_DMAC 6
|
||||
#define R9A07G043_PD_GTM0 7
|
||||
#define R9A07G043_PD_GTM1 8
|
||||
#define R9A07G043_PD_GTM2 9
|
||||
#define R9A07G043_PD_MTU 10
|
||||
#define R9A07G043_PD_POE3 11
|
||||
#define R9A07G043_PD_WDT0 12
|
||||
#define R9A07G043_PD_SPI 13
|
||||
#define R9A07G043_PD_SDHI0 14
|
||||
#define R9A07G043_PD_SDHI1 15
|
||||
#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */
|
||||
#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */
|
||||
#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */
|
||||
#define R9A07G043_PD_SSI0 19
|
||||
#define R9A07G043_PD_SSI1 20
|
||||
#define R9A07G043_PD_SSI2 21
|
||||
#define R9A07G043_PD_SSI3 22
|
||||
#define R9A07G043_PD_SRC 23
|
||||
#define R9A07G043_PD_USB0 24
|
||||
#define R9A07G043_PD_USB1 25
|
||||
#define R9A07G043_PD_USB_PHY 26
|
||||
#define R9A07G043_PD_ETHER0 27
|
||||
#define R9A07G043_PD_ETHER1 28
|
||||
#define R9A07G043_PD_I2C0 29
|
||||
#define R9A07G043_PD_I2C1 30
|
||||
#define R9A07G043_PD_I2C2 31
|
||||
#define R9A07G043_PD_I2C3 32
|
||||
#define R9A07G043_PD_SCIF0 33
|
||||
#define R9A07G043_PD_SCIF1 34
|
||||
#define R9A07G043_PD_SCIF2 35
|
||||
#define R9A07G043_PD_SCIF3 36
|
||||
#define R9A07G043_PD_SCIF4 37
|
||||
#define R9A07G043_PD_SCI0 38
|
||||
#define R9A07G043_PD_SCI1 39
|
||||
#define R9A07G043_PD_IRDA 40
|
||||
#define R9A07G043_PD_RSPI0 41
|
||||
#define R9A07G043_PD_RSPI1 42
|
||||
#define R9A07G043_PD_RSPI2 43
|
||||
#define R9A07G043_PD_CANFD 44
|
||||
#define R9A07G043_PD_ADC 45
|
||||
#define R9A07G043_PD_TSU 46
|
||||
#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */
|
||||
#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */
|
||||
#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */
|
||||
#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
|
||||
|
||||
@ -217,4 +217,62 @@
|
||||
#define R9A07G044_ADC_ADRST_N 82
|
||||
#define R9A07G044_TSU_PRESETN 83
|
||||
|
||||
/* Power domain IDs. */
|
||||
#define R9A07G044_PD_ALWAYS_ON 0
|
||||
#define R9A07G044_PD_GIC 1
|
||||
#define R9A07G044_PD_IA55 2
|
||||
#define R9A07G044_PD_MHU 3
|
||||
#define R9A07G044_PD_CORESIGHT 4
|
||||
#define R9A07G044_PD_SYC 5
|
||||
#define R9A07G044_PD_DMAC 6
|
||||
#define R9A07G044_PD_GTM0 7
|
||||
#define R9A07G044_PD_GTM1 8
|
||||
#define R9A07G044_PD_GTM2 9
|
||||
#define R9A07G044_PD_MTU 10
|
||||
#define R9A07G044_PD_POE3 11
|
||||
#define R9A07G044_PD_GPT 12
|
||||
#define R9A07G044_PD_POEGA 13
|
||||
#define R9A07G044_PD_POEGB 14
|
||||
#define R9A07G044_PD_POEGC 15
|
||||
#define R9A07G044_PD_POEGD 16
|
||||
#define R9A07G044_PD_WDT0 17
|
||||
#define R9A07G044_PD_WDT1 18
|
||||
#define R9A07G044_PD_SPI 19
|
||||
#define R9A07G044_PD_SDHI0 20
|
||||
#define R9A07G044_PD_SDHI1 21
|
||||
#define R9A07G044_PD_3DGE 22
|
||||
#define R9A07G044_PD_ISU 23
|
||||
#define R9A07G044_PD_VCPL4 24
|
||||
#define R9A07G044_PD_CRU 25
|
||||
#define R9A07G044_PD_MIPI_DSI 26
|
||||
#define R9A07G044_PD_LCDC 27
|
||||
#define R9A07G044_PD_SSI0 28
|
||||
#define R9A07G044_PD_SSI1 29
|
||||
#define R9A07G044_PD_SSI2 30
|
||||
#define R9A07G044_PD_SSI3 31
|
||||
#define R9A07G044_PD_SRC 32
|
||||
#define R9A07G044_PD_USB0 33
|
||||
#define R9A07G044_PD_USB1 34
|
||||
#define R9A07G044_PD_USB_PHY 35
|
||||
#define R9A07G044_PD_ETHER0 36
|
||||
#define R9A07G044_PD_ETHER1 37
|
||||
#define R9A07G044_PD_I2C0 38
|
||||
#define R9A07G044_PD_I2C1 39
|
||||
#define R9A07G044_PD_I2C2 40
|
||||
#define R9A07G044_PD_I2C3 41
|
||||
#define R9A07G044_PD_SCIF0 42
|
||||
#define R9A07G044_PD_SCIF1 43
|
||||
#define R9A07G044_PD_SCIF2 44
|
||||
#define R9A07G044_PD_SCIF3 45
|
||||
#define R9A07G044_PD_SCIF4 46
|
||||
#define R9A07G044_PD_SCI0 47
|
||||
#define R9A07G044_PD_SCI1 48
|
||||
#define R9A07G044_PD_IRDA 49
|
||||
#define R9A07G044_PD_RSPI0 50
|
||||
#define R9A07G044_PD_RSPI1 51
|
||||
#define R9A07G044_PD_RSPI2 52
|
||||
#define R9A07G044_PD_CANFD 53
|
||||
#define R9A07G044_PD_ADC 54
|
||||
#define R9A07G044_PD_TSU 55
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
|
||||
|
||||
@ -226,4 +226,62 @@
|
||||
#define R9A07G054_TSU_PRESETN 83
|
||||
#define R9A07G054_STPAI_ARESETN 84
|
||||
|
||||
/* Power domain IDs. */
|
||||
#define R9A07G054_PD_ALWAYS_ON 0
|
||||
#define R9A07G054_PD_GIC 1
|
||||
#define R9A07G054_PD_IA55 2
|
||||
#define R9A07G054_PD_MHU 3
|
||||
#define R9A07G054_PD_CORESIGHT 4
|
||||
#define R9A07G054_PD_SYC 5
|
||||
#define R9A07G054_PD_DMAC 6
|
||||
#define R9A07G054_PD_GTM0 7
|
||||
#define R9A07G054_PD_GTM1 8
|
||||
#define R9A07G054_PD_GTM2 9
|
||||
#define R9A07G054_PD_MTU 10
|
||||
#define R9A07G054_PD_POE3 11
|
||||
#define R9A07G054_PD_GPT 12
|
||||
#define R9A07G054_PD_POEGA 13
|
||||
#define R9A07G054_PD_POEGB 14
|
||||
#define R9A07G054_PD_POEGC 15
|
||||
#define R9A07G054_PD_POEGD 16
|
||||
#define R9A07G054_PD_WDT0 17
|
||||
#define R9A07G054_PD_WDT1 18
|
||||
#define R9A07G054_PD_SPI 19
|
||||
#define R9A07G054_PD_SDHI0 20
|
||||
#define R9A07G054_PD_SDHI1 21
|
||||
#define R9A07G054_PD_3DGE 22
|
||||
#define R9A07G054_PD_ISU 23
|
||||
#define R9A07G054_PD_VCPL4 24
|
||||
#define R9A07G054_PD_CRU 25
|
||||
#define R9A07G054_PD_MIPI_DSI 26
|
||||
#define R9A07G054_PD_LCDC 27
|
||||
#define R9A07G054_PD_SSI0 28
|
||||
#define R9A07G054_PD_SSI1 29
|
||||
#define R9A07G054_PD_SSI2 30
|
||||
#define R9A07G054_PD_SSI3 31
|
||||
#define R9A07G054_PD_SRC 32
|
||||
#define R9A07G054_PD_USB0 33
|
||||
#define R9A07G054_PD_USB1 34
|
||||
#define R9A07G054_PD_USB_PHY 35
|
||||
#define R9A07G054_PD_ETHER0 36
|
||||
#define R9A07G054_PD_ETHER1 37
|
||||
#define R9A07G054_PD_I2C0 38
|
||||
#define R9A07G054_PD_I2C1 39
|
||||
#define R9A07G054_PD_I2C2 40
|
||||
#define R9A07G054_PD_I2C3 41
|
||||
#define R9A07G054_PD_SCIF0 42
|
||||
#define R9A07G054_PD_SCIF1 43
|
||||
#define R9A07G054_PD_SCIF2 44
|
||||
#define R9A07G054_PD_SCIF3 45
|
||||
#define R9A07G054_PD_SCIF4 46
|
||||
#define R9A07G054_PD_SCI0 47
|
||||
#define R9A07G054_PD_SCI1 48
|
||||
#define R9A07G054_PD_IRDA 49
|
||||
#define R9A07G054_PD_RSPI0 50
|
||||
#define R9A07G054_PD_RSPI1 51
|
||||
#define R9A07G054_PD_RSPI2 52
|
||||
#define R9A07G054_PD_CANFD 53
|
||||
#define R9A07G054_PD_ADC 54
|
||||
#define R9A07G054_PD_TSU 55
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
|
||||
|
||||
@ -239,4 +239,74 @@
|
||||
#define R9A08G045_I3C_PRESETN 92
|
||||
#define R9A08G045_VBAT_BRESETN 93
|
||||
|
||||
/* Power domain IDs. */
|
||||
#define R9A08G045_PD_ALWAYS_ON 0
|
||||
#define R9A08G045_PD_GIC 1
|
||||
#define R9A08G045_PD_IA55 2
|
||||
#define R9A08G045_PD_MHU 3
|
||||
#define R9A08G045_PD_CORESIGHT 4
|
||||
#define R9A08G045_PD_SYC 5
|
||||
#define R9A08G045_PD_DMAC 6
|
||||
#define R9A08G045_PD_GTM0 7
|
||||
#define R9A08G045_PD_GTM1 8
|
||||
#define R9A08G045_PD_GTM2 9
|
||||
#define R9A08G045_PD_GTM3 10
|
||||
#define R9A08G045_PD_GTM4 11
|
||||
#define R9A08G045_PD_GTM5 12
|
||||
#define R9A08G045_PD_GTM6 13
|
||||
#define R9A08G045_PD_GTM7 14
|
||||
#define R9A08G045_PD_MTU 15
|
||||
#define R9A08G045_PD_POE3 16
|
||||
#define R9A08G045_PD_GPT 17
|
||||
#define R9A08G045_PD_POEGA 18
|
||||
#define R9A08G045_PD_POEGB 19
|
||||
#define R9A08G045_PD_POEGC 20
|
||||
#define R9A08G045_PD_POEGD 21
|
||||
#define R9A08G045_PD_WDT0 22
|
||||
#define R9A08G045_PD_XSPI 23
|
||||
#define R9A08G045_PD_SDHI0 24
|
||||
#define R9A08G045_PD_SDHI1 25
|
||||
#define R9A08G045_PD_SDHI2 26
|
||||
#define R9A08G045_PD_SSI0 27
|
||||
#define R9A08G045_PD_SSI1 28
|
||||
#define R9A08G045_PD_SSI2 29
|
||||
#define R9A08G045_PD_SSI3 30
|
||||
#define R9A08G045_PD_SRC 31
|
||||
#define R9A08G045_PD_USB0 32
|
||||
#define R9A08G045_PD_USB1 33
|
||||
#define R9A08G045_PD_USB_PHY 34
|
||||
#define R9A08G045_PD_ETHER0 35
|
||||
#define R9A08G045_PD_ETHER1 36
|
||||
#define R9A08G045_PD_I2C0 37
|
||||
#define R9A08G045_PD_I2C1 38
|
||||
#define R9A08G045_PD_I2C2 39
|
||||
#define R9A08G045_PD_I2C3 40
|
||||
#define R9A08G045_PD_SCIF0 41
|
||||
#define R9A08G045_PD_SCIF1 42
|
||||
#define R9A08G045_PD_SCIF2 43
|
||||
#define R9A08G045_PD_SCIF3 44
|
||||
#define R9A08G045_PD_SCIF4 45
|
||||
#define R9A08G045_PD_SCIF5 46
|
||||
#define R9A08G045_PD_SCI0 47
|
||||
#define R9A08G045_PD_SCI1 48
|
||||
#define R9A08G045_PD_IRDA 49
|
||||
#define R9A08G045_PD_RSPI0 50
|
||||
#define R9A08G045_PD_RSPI1 51
|
||||
#define R9A08G045_PD_RSPI2 52
|
||||
#define R9A08G045_PD_RSPI3 53
|
||||
#define R9A08G045_PD_RSPI4 54
|
||||
#define R9A08G045_PD_CANFD 55
|
||||
#define R9A08G045_PD_ADC 56
|
||||
#define R9A08G045_PD_TSU 57
|
||||
#define R9A08G045_PD_OCTA 58
|
||||
#define R9A08G045_PD_PDM 59
|
||||
#define R9A08G045_PD_PCI 60
|
||||
#define R9A08G045_PD_SPDIF 61
|
||||
#define R9A08G045_PD_I3C 62
|
||||
#define R9A08G045_PD_VBAT 63
|
||||
|
||||
#define R9A08G045_PD_DDR 64
|
||||
#define R9A08G045_PD_TZCDDR 65
|
||||
#define R9A08G045_PD_OTFDE_DDR 66
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user