ASoC: amd: ps: add comments for DMA irq bits mapping

Add comments for DMA stream id and IRQ bit mapping in
ACP_EXTERNAL_CNTL & ACP_EXTERNAL_CNTL1 registers for
SDW0 and SDW1 manager instances.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://lore.kernel.org/r/20230626105356.2580125-1-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vijendar Mukunda 2023-06-26 16:23:49 +05:30 committed by Mark Brown
parent 7b51620801
commit 7beda6a256
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@ -116,8 +116,28 @@
#define ACP63_SDW0_DMA_MAX_STREAMS 6
#define ACP63_SDW1_DMA_MAX_STREAMS 2
#define ACP_P1_AUDIO_TX_THRESHOLD 6
/*
* Below entries describes SDW0 instance DMA stream id and DMA irq bit mapping
* in ACP_EXTENAL_INTR_CNTL register.
* Stream id IRQ Bit
* 0 (SDW0_AUDIO0_TX) 28
* 1 (SDW0_AUDIO1_TX) 26
* 2 (SDW0_AUDIO2_TX) 24
* 3 (SDW0_AUDIO0_RX) 27
* 4 (SDW0_AUDIO1_RX) 25
* 5 (SDW0_AUDIO2_RX) 23
*/
#define SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i)))
#define SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * (i)))
/*
* Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping
* in ACP_EXTENAL_INTR_CNTL1 register.
* Stream id IRQ Bit
* 0 (SDW1_AUDIO1_TX) 6
* 1 (SDW1_AUDIO1_RX) 5
*/
#define SDW1_DMA_IRQ_MASK(i) (ACP_P1_AUDIO_TX_THRESHOLD - (i))
#define ACP_DELAY_US 5