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dt-bindings: PCI: dwc: Add dma-coherent property
DW PCIe EP/RP AXI- and TRGT1-master interfaces are responsible for the application memory access. They are used by the RP/EP PCIe buses (MWr/MWr TLPs emitted by the peripheral PCIe devices) and the eDMA block. Since all of them mainly involve the system memory and basically mean DMA we can expect the corresponding platforms can be designed in a way to make sure the transactions are cache-coherent. As such the DW PCIe DT-nodes can have the 'dma-coherent' property specified. Let's permit it in the DT-bindings then. Link: https://lore.kernel.org/r/20221113191301.5526-13-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
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@ -259,6 +259,8 @@ properties:
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configuration space registers, Port Logic registers, DMA and iATU
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registers. This feature has been available since DWC PCIe v4.80a.
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dma-coherent: true
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additionalProperties: true
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...
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